6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 45 Multilevel Modular onverter for VS-HVD Transmission Appliations: ontrol and Operational Aspets dana. Gnanarathna, Aniruddha M. Gole Dept. of Eletrial and omputer Engineering niversity of Manitoba Winnipeg, anada udana@ee.umanitoba.a gole@ee.umanitoba.a Sanjay K. haudhary Dept. of Energy Tehnology Aalborg niversity Aalborg, Denmark sk@et.aau.dk Abstrat ontrol methods for a new lass of onverter, the multilevel modular onverter (MM), reently introdued for HVD transmission are disussed. The paper disusses onverter-level ontrols inluding firing pulse generation and apaitor voltage balaning. It also overs higher level ontrols for inorporating the onverter into a larger power network, with a weak a reeiving end. The performane behavior is studied using eletromagneti transients simulation. Keywords-Voltage Soure onvert (VS), Multilevel Modular onverter (MM), HVD Transmission, Weak a networks I. ITRODTIO Voltage soured onverter (VS) based HVD systems exhibit many attrative features over the onventional line ommutated onverter (L) based systems in high voltage high power appliations []. These unique features suh as independent ontrol of ative and reative power [2], operation in weak a systems [3], blak start apability [4], and multi terminal onnetion [5] have led to their inreased adoption in modern shemes. Till reently, two-level or three-level VS topologies were used for HVD transmission appliations, with pulse-width modulation (PWM) ontrol to redue the lower harmoni ontent. The ratings were typially limited to below 4 MW beause of the higher swithing losses inherent in suh topologies. umerous multilevel topologies and modulation strategies have been introdued for mahine drive appliations [6]-[8]. Diode lamped multilevel onverters [6] [7] synthesize a stepped a waveform resembling a sine wave, by staking fixed magnitude voltage steps on top of eah other. This topology typially has lower losses than two level PWM onverters. However, the number of levels has been limited to 3 (in HVD appliations) due to the iruit omplexity. Also apaitor voltage balaning is a ritial and hallenging issue. The reently initiated modular multilevel onverter (MM) is a major step forward in VS onverter tehnology for HVD transmission [9]. This topology is designed to make lower swithing frequeny, avoid onneting the devies in series. The modular struture easily sales to higher voltage Supported by the atural Sienes and Engineering Researh ounil (SER) of anada, IR Program and power levels, with the addition of more modules. A power rating of GW and above now beomes possible. Although the MM topology has been presented in earlier literature [9], [], the disussion on ontrol methods is sparse. This paper disusses ontrol approahes and investigates their performane using eletromagneti transients (EMT) simulation. The paper also investigates the ontrol and performane of a HVD transmission sheme feeding to a weak a system. II. MODLAR MLTILEVEL OVERTER TOPOLOGY A. iruit Struture of Modular Multilevel onverter The basi building blok of the MM onverter is the submodule shown in Fig., whih onsists of two IGBT swithes T and T 2 and a apaitor. In normal operation, exatly one swith (T or T 2 ) is O at any instant, giving a sub-module output voltage of V or (): V OT () t V T -O, T -OFF 2 = () T-OFF, T2-O When the sub-module voltage is V, it is said to be in the O state, and when it is zero, it is onsidered to be OFF. B. Output Voltage Waveform Synthesis The single phase blok diagram of the MM (modular multi-level onverter) is shown in Fig. 2. The MM phase inludes upper and lower multi-valves, eah with a number () of sub modules (SM j ). The number is hosen based on the d voltage rating (V d ) and individual sub-module rating (V ). High speed bypass swith V OT I OT T T 2 Fig.. Sub-module of MM onverter V Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.
6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 46 V d SM SM 2 SM SM SM 2 SM I MV,T I MV,B V,T V,T2 V,T V,B V,B2 V,B Multi-valve V d /2 A V A V d /2 Fig. 2. Phase module of an MM sheme for an -level arrangement Thus, this modular struture an be saled for different voltage and power levels [9]. By ontrolling the O/OFF state of the sub-modules, the output voltage waveform, V A, an be synthesized to trak a given sinusoidal voltage referene V ref as shown in Fig. 3. The referene V ref is ompared with disrete equidistant quantization thresholds (see Fig.4, top left). The number of sub-modules and L required to be O in the upper and lower multi-valves respetively is thus determined as: L = round( Vref ) = ( pu ).5 45 9 35 8 225 27 35 36.5 ωt (deg) L Vref VA Fig. 3: Referene and output waveforms for MM with 8 sub-modules per multi-valve Here it is assumed that V ref is, when output voltage is at its maximum possible value of V d /2. With the above waveform synthesis method at any given instant, the full d bus voltage appears aross + L = sub-modules [9]. Hene, sine all apaitor voltages are required to be the same, eah must be equal to: (2) sub-modules in the multi-valve. The apaitor voltages on the remaining sub-modules (and hene the step height of the waveform) is now slightly larger as the number of sub-modules available for generating the waveform is redued. D. apaitor Voltage Balaning In Fig., with T O and T 2 OFF, the apaitor voltage inreases or dereases depending on the diretion of submodule urrent I OT being positive or negative. The apaitor voltage remains unhanged with T 2 O and T OFF. Hene, during the operation, the OFF sub-modules maintain onstant apaitor voltages, whereas the O sub-modules experiene an inrease or derease of their apaitor voltages. Hene a apaitor voltage balaning algorithm is required. ote that the output waveform synthesis algorithm merely states that and L sub-modules are O in the upper and lower multivalves. Assuming all sub-module apaitors to have equal voltages provides a measure of freedom in seleting the individual O state sub-modules, whih are utilized in the apaitor voltage balaning algorithm desribed below. The funtion of this apaitor balaning algorithm is to generate firing pulses for eah sub-module in a multi-valve by maintaining the sub-module s apaitor voltages at a value, given by equation (3). A table is reated in whih the apaitors are ranked in order of inreasing d voltages. The table is onsulted when the quantization algorithm demands a step hange (i.e. hange in and ). onsider the upper multi-valve whih requires submodules to be O. If the urrent I OT is positive (see Fig. ), then turning on a sub-module will result in apaitor voltage inrease. In that ase, the sub-modules ranked lowest in voltage are turned on, so that they an be re-harged. If I OT is negative, then the highest-voltage sub-modules are turned on, so that their voltages may disharge. The same is done for the lower multi-valve. The apaitor voltages of sub-modules an be ontrolled in a narrow band by applying this methodology for all three phases []. The overall ontrol struture for the onverter, inluding the waveform quantizer and the apaitor balaning ontroller is shown shematially in Fig. 4. III. OPERATIOAL ASPETS OF MM OVERTER A detailed model of the single phase MM onverter was developed in the eletro-magneti transient s simulation program PSAD/EMTD. L V V d = (3). Redundant Sub-modules Redundant sub-modules are provided in eah multi-valve. If a sub-module fails during operation, it is quikly removed from the iruit by operating the high-speed bypass swith [] shown in Fig.. ormal operation an ontinue with the remaining sub-modules in the multi-valve. The waveform synthesis algorithm disussed in the previous sub-setion is informed of the failure and now only ontrols the remaining - V ref I MV Quantizer, L apaitor voltages V V 2 V apaitor voltage balaning Firing pulses FP FP 2 Diretion hek Fig. 4. Firing pulse ontrol algorithm of MM FP Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.
6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 47 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2 3 4 5 Time (ms) Fig. 5. a) Sinusoidal referene waveform and onverter output voltage waveforms when number of sub-modules per multi-valve is; b) 2, ) 6, d) 2, e) 24, f) 48, and g) 96 () (d) (e) (f) (g) A. Multi-level A Waveform of MM The output voltage waveforms obtained for different number of sub-modules in a phase unit are presented in Fig. 5. In these simulations, the d bus voltage (pole-pole) is V d = 24kV. Fig. 5 shows the referene sinusoidal waveform, and eah subsequent graph shows the waveform attained with inreasing number of sub-modules ranging from 2 to 96. The sub-module apaitane was set to a high value so that the hange of apaitor voltage in a ondution interval is negligible. As the number of sub-modules is inreased, the steps beome smaller, and the waveform beomes loser to that of the referene sine wave. Standard IEEE 59 reommends two indies for voltage distortion [2]. The individual harmoni distortion Dn is the magnitude of the nth harmoni as a perentage of the fundamental. The total harmoni distortion is the root mean square of all harmonis expressed as a perentage of the fundamental. A ommonly used limit for these in HVD systems is Dn less than % for eah harmoni, and THD less than 2%, onsidering all harmonis up to the 5 th. Fig. 6 shows the maximum Dn and THD values for an ideal MM waveform, with the above thresholds indiated, as the number of sub-modules per multi-valve is inreased. It is quite lear that with more than 22 sub-modules per multi-valve, all harmoni limits are satisfied. The MM with this number of sub-modules an therefore be operated without any a filters, whih is a signifiant advantage. Atual MM installations use a larger number of modules, beause they operate at high d voltages, and the additional modules redue the voltage stress per module. B. Perfomane of apaitor Voltage Balaning ontroller In this setion, the performane of apaitor balaning ontroller, as desribed in setion II-D, is presented by disabling and enabling the ontrol operation for different time intervals. First, the ontroller was disabled at.5 s. apaitor voltages start to diverge from their nominal value. The 4 V V out Dnmx (%) THD (%) 2.5.5 2 (i) (ii) - 5 4 8 2 6 2 24 28 V out -.34.35.36 2.2 2.2 2.22 2.23 Fig. 7. a) apaitor voltages in 2 andidate sub-modules showing effet of enabling/disabling voltage balaning ontrol. b) MM output voltage (i) without and (ii) with voltage balaning in operation. apaitor voltages of two sub-modules that show the widest deviations are shown Fig. 7. These deviations are aused by the different apaitor ondution (harging or disharging) intervals whih depend on the sub-module s duty yle. The sub-modules having the longest O period either overharge or underharge based on the urrent diretion. However, when the balaning ontroller is re-enabled at.5s, the apaitor voltages were quikly restored to their nominal values. The orresponding onverter output voltage waveforms around the.33s mark with apaitor voltage balaning disabled, and at the 2.2s mark with voltage balaning enabled are shown in Fig. 5. In this simulation, there are 2 sub-modules in a multi-valve. The above results show that the voltage balaning ontroller is rapidly able to equalize the apaitor voltages.. Impat of apaaitor Size on Performane A smaller size for the sub-module apaitane results in more d-side ripple voltage. If the ripple is too large, it an distort the a side voltage waveform signifiantly. Fig. 8 shows the variation of a typial sub-module apaitor voltage depending on the size of apaitane used. In order to perunitize the apaitor size, it is ustomary to express it in the form of the total apaitor energy stored at rated d voltage for all apaitors in the onverter, to the omplex power rating of the onverter as shown in (4). 5 2 4 8 2 6 2 24 28 Fig 6. Max. individual harmoni and THD variations with no. of levels Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.
6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 48 (pu) pu = 2 (.5 V )(6 ) P 2 2 + Q Here is the sub-module apaitane, V, its voltage, P and Q, the onverter s rated real and reative powers, and the number of sub-modules. The number 6 in (4) arises from the fat that there are 6 multi-valves with sub-modules per valve. With this definition, the unit of is the seond. The resulting a output voltage for different sub-module apaitane values (from 8 ms to 8 ms) for a 6-level MM is shown in Fig. 9. For a apaitane value 8 ms or larger (Fig. 9(a to e)), the waveform is essentially the same. However, apaitane values smaller than 8 ms (e.g. Fig. 9(f and g) introdue distortion. These results show that the MM apaitor should be larger than 8ms. () (d) (e) (f) (g).2..98 8ms 4ms 2ms ms 4ms.96 2 3 4 5 Time (ms) Fig. 8. Average apaitor voltage flutuation for different apaitane values of 6-level MM - - - - - - - 2 3 4 5 Time (ms) Fig. 9. onverter output voltage waveforms for different apaitane values; a) 8 ms, b) 4 ms, ) 2 ms, d) ms, e) 8 ms, f) 4 ms, g) 8 ms IV. In the MM, the number of sub-modules is very large. Eah of the sub-modules of the 6 multi-valves in a three phase MM ontains 2 swith elements, giving a total of 2 swithes per onverter. With sub-modules, this gives 2 swithes per onverter. Systems of this size pose a signifiant omputational burden in terms of P time to eletromagneti HALLEEGES I MODELLIG MM pu (4) transient (EMT) programs. To overome this omputational effort of MM simulation in EMT simulation programs, a reently introdued model based on the ested Fast and Simultaneous Solution [3] approah was used [4]. This method represents the onverter power eletronis as a time-varying Thévenin's equivalent that is able to maintain the same level of auray as brute-fore EMT simulation, but with muh redued omputation time. nlike averaged models [5], the model used here is still able to represent individual sub-module details, and an simulate phenomena suh as sub-module failure or apaitor voltage balaning. V. SIMLATIO OF A MM BASED HVD SYSTEM In this setion, a point to point MM based HVD transmission system; feeding to a weak a network has been simulated. The d link is onneted to the two a systems. The sending end a system has a short iruit ratio (SR) of 2.5, and is relatively strong. The reeiving end system is weak, with an SR of.. The simulated system is shematially shown in Fig.. In the simulation, MM ats as the retifier and MM2 ats as the inverter. The d system is rated at 4MW, ±2kV. Eah MM has sub-modules in a multi-valve; hene the sub-modules were rated at 4.kV. As there is a total of 24 swithes in the two onverters, it is pratially impossible to model the onverters using the traditional approah using individual swithes in EMT programs. Therefore, omputationally fast model disussed in setion IV, was used for modelling the system [4]. A. HVD System ontrols The diret ontrol strategy [6] was seleted for the higher level ontrollers of the system. The ontrollers output the desired phase shift angle δ and the magnitude M of the referene signal (V ref ). The referene for measuring the angle δ is the a onverter bus-bar (Bus for MM and Bus 2 for MM2). The angle of this bus voltage is traked by a phaseloked loop (PLL) whih provides the synhronizing referene. The details of the individual retifier and inverter side ontrollers are given below. ) Retifier Side ontroller The MM, retifier is responsible for regulating the d side voltage and a side Bus voltage as shown in Fig.. Proportional-integral ontrollers derive magnitude, M, and phase, δ, of the referene waveform to regulate the a bus-bar voltage and the d bus voltage respetively. sing these, three phase referene waveforms are generated and sent to the firing ontrol system shown in Fig. 4. as desribed in setion II-D. 2) Inverter Side ontroller At the inverter, a similar ontrol strategy is used, with the differene that the magnitude, M 2, and phase, δ 2, of the referene waveform are the outputs of proportional-integral ontrollers that regulate a bus voltage and real power respetively, as shown in Fig. 2. Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.
6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 49 L d R d R d L d L Bus BusA d Bus2 L 2 R A SR=2.5 R ' Y Δ TF MM (Retifier) d Δ Y TF2 MM2 (Inverter) R 2 ' R 2 A2 SR =. L d R d R d L d Fig.. MM based HVD system Bus MM MM2 Bus2 v s v d P 2 v s2 v s v d - + + - v d M δ v s (ab) v ref (ab) Sinusoidal referene generator θ PLL Fig.. Retifier side onverter ontroller v ref2 (ab) Sinusoidal referene generator θ 2 PLL M 2 v s2 (ab) Fig. 2. Inverter side onverter ontroller δ 2 - + - + P 2 v s2 P 2 B. Response of HVD System to Power Order hange Fig. 3 shows waveforms for the above HVD transmission system where a power order hange from full power (4 MW) to half power (2 MW) is applied at.4 s. The real and reative power at the reeiving end are shown in Fig. 3, with the inverter side rms a voltage and three phase bus voltage waveforms shown in Figs. 3 and () respetively. From the simulation, it an be seen that when the load is redued, the voltage is immediately ontrolled to the rated value of 5kV and no signifiant overvoltage is seen, even though the inverter side a system is weak. The ontrol of voltage is obtained by rapid ontrol of the reative power to follow the real power hange, as shown in the trae of reative power in Fig. 3. The hange in power to (to 9% of final setting) is seen to be ahieved in approximately 6 ms in Fig. 3. The onverter output a voltage waveforms are shown during this transient and are indeed sinusoidal even though no a filters are used. VI. OLSIO The multi-level modular onverter is an attrative topology for HVD operation. The paper presented the basi ontrol approah for use of this devie in HVD transmission appliations. Through alulation and EMT simulation, it was shown that the MM an provide an essentially sinusoidal waveform that meets aepted guidelines of harmoni ontent, without the need for a filters when the number of submodules per multi-valve exeeds 22. A mehanism for voltage balaning is essential and one (MW, MVar) 4 2 Pa2Ref P2 Q2.4.8.2.5 6 5 4.4 ().8.2.5 -.38.4.42.44.46.48.5 Fig. 3. Waveforms during the inlusion of a redundant sub-module; a) onverter output voltage, b) output urrent, ) defetive sub-module s apaitor voltage, and e) inoming sub-module s voltage possible method for doing this was desribed and demonstrated through the use of simulation. The apaitor voltage balaning ontroller was rapidly able to restore balaned apaitor voltages. The simulation model of the point to point HVD system showed that the MM works well in a full-sale appliation. It an respond rapidly to power order hanges while maintaining a and d voltages at their desired referene values. Also, like other VS onverters, it is able to operate satisfatorily into very weak a networks (SRs of the order of.). Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.
6th ATIOAL POWER SYSTEMS OFEREE, 5th-7th DEEMBER, 2 4 REFEREES [] M. P. Bahrman, J. G. Johansson, B. A. ilsson, Voltage soure onverter transmission tehnologies The right fit for the appliation, IEEE PES General Meeting, vol. 3, pp. 84-847, Jul. 23. [2] H.F. Latorre, M. Ghandhari, L. Söder, Ative and reative power ontrol of a VS-HVd, Eletri Power Systems Researh, vol. 78, issue, pp. 756-763, Ot. 28. [3]. Du, VS-HVD for industrial power systems, Thesis for the degree of Dotor of Philosophy, halmers niversity of Tehnology, Göteborg, Sweden 27. [4] Y. Jiang-Hafner; H. Duhen, M. Karlsson, L. Ronstrom, B. Abrahamsson, HVD with voltage soure onverters - a powerful standby blak start faility, IEEE/PES Transmission and Distribution onferene and Exposition 28, pp. -9. [5] T. M. Haileselassie, M. Molinas, and T. ndeland, Multi-Terminal VS-HVD System for Integration of Offshore Wind Farms and Green Eletrifiation of Platforms in the orth Sea, ordi Workshop on Power and Industrial Eletronis, June 9-, 28. [6] A. abae, I. Takahashia, and H. Akagi, ew eutral-point-lamped PWM Inverter, IEEE Trans. on Industry Appliations, vol. IA-7, no. 5, pp. 58-523, Sep./Ot. 98. [7] J. S. Lai, and F. Z. Peng, Multilevel onverters-a ew Breed of Power onverters, IEEE Trans. on Industry Appliations, vol. 32, no. 3, pp. 59-57, May/Jun. 996. [8] J. Rodríguez, J. S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, ontrols, and appliations, IEEE Trans. on Industrial Eletronis, vol. 49, no. 4, pp. 724-738, Aug. 22. [9] R. Marquardt and A. Lesniar, A new modular voltage soure inverter topology, EPE'3, Toulouse, Frane, 23. [] A. Lesniar and R. Marquardt, An Innovative Modular Multilevel onverter Topology Suitable for a Wide Power Range, IEEE Power Teh onferene Pro., Bologna, vol. 3, Jun. 23 [] B. Gemmell, J. Dorn, D. Retzmann, D. Soerangr, Prospets of Multilevel VS Tehnologies for Power Transmission, IEEE T&D onferene and Exposition, 2st - 24th April 28, hiago/sa [2] IEEE Std 59-992, IEEE Reommended Praties and Requirements for Harmoni ontrol in Eletri Power Systems. [3] K. Strunz and E. arlson, ested Fast and Simultaneous Solution for Time-Domain Simulation of Integrative Power-Eletri and Eletroni Systems, IEEE Trans. on Power Delivery, vol. 22, pp. 277 287, Jan. 27. [4].. Gnanarathna, A. M. Gole, and R. P. Jayasinghe, Effiient Modeling of Modular Multi-Level HVD onverters (MM) on Eletromagneti Transient Simulation Programs, paper no. TPWRD- 26-2.R aepted (July 2) for publiation in the IEEE Trans. on Power Delivery. [5] S. P. Teeuwsen, Simplified Dynami Model of a Voltage-Soured onverter with Modular Multilevel onverter design, IEEE/PES Power Systems onferene and Exposition, Mar. 29. [6] IGRE, S B4 HVD and Power Eletronis, WG B4-37, VS Transmission, igré Tehnial Brohure, o. 269, April 25 Department of Eletrial Engineering, niv. ollege of Engg., Osmania niversity, Hyderabad, A.P, IDIA.