Lecture 9: Diode coected devices, mirrors, cascode coectios Prof J. S. Smith Cotext Today we will be lookig at more sigle trasistor active circuits ad example problems, ad the startig multi-stage amplifiers 1
Lecture Outlie Summary of sigle-trasistor amplifiers Diode coected MOSFETs Curret Mirrors Biasig Schemes Sigle Stage Amplifiers Commo-source is the oly stage that provides both curret ad voltage gai Miller effect limits high frequecy respose Commo-drai ca buffer a poor voltage source ito a very good voltage source oe Commo-gate ca buffer a poor curret source ito a very good curret source, or replicate a curret source ito may curret sources (curret mirror)
NMOS pullup Rather tha usig a big (ad expesive) resistor, let s look at a NMOS trasistor as a active pullup +V device v out Note that whe the trasistor is coected this way, it is ot a amplifier, it is a two termial device. Whe the gate is coected to the drai of this NMOS device, it will be i saturatio, so we get the equatio for the drai curret: I D W = µ C SG T 1 + L ( V V ) ( λ V ) SD Small sigal model So we have: The N chael MOSFET s trascoductace is: Ad so the small sigal model for this device will be a resistor with a resistace: W I D = µ C L W = µ C L SG ( V V ) ( 1 + λ V ) SG W L ( V V ) ( 1 + λ V ) µ C ( V V ) T W W g m = D µ SG T µ v L L T ( i ) = C ( V V ) C ( I ) Q SD 1 r = g m D T 3
IV for NMOS pull-up The I-V characteristic of this pull-up device: I W = µ C L ( V V ) D1 DD T I ( V ) DD V t V V DD Active Load We ca use this as the pullup device for a NMOS commo source amplifier: V DD W 1 I ( ) D1 = C V gs1 VT1 L µ 1 M I D W = L µ C ( V V ) gs T + v i M 1 + v out V V 0 = V DD V 0 gs = V DD V t I µ C ( W / L ) 4
Active Load Sice I =I 1 we have: V DD V 0 = V DD V t I1 µ C ( W / L ) M Ad sice: V = V gs1 i + v i M 1 + v out V 0 = V DD V t1 ( W1 / L1 ) ( ) ( V ) i Vt1 W / L Behavior If the output voltage goes higher tha oe threshold below VDD, trasistor goes ito cutoff ad the amplifier will clip. If the output goes too low, the trasistor 1 will fall out of the saturatio mode. Withi these limitatios, this stage gives a good liear amplificatio. 5
CMOS Diode Coected Trasistor Short gate/drai of a trasistor ad pass curret through it Sice VGS = VDS, the device is i saturatio sice VDS > VGS-VT Sice FET is a square-law (or weaker) device, the I-V curve is very soft compared to PN juctio diode Diode Equivalet Circuit R D di dv OUT = 0 1 OUT = = R OUT D I 1 g m vt i t Equivalet Circuit: R D i OUT V D + - + v OUT - 6
The Itegrated Curret Mirror High Res Low Resis M 1 ad M have the same V GS If we eglect CLM (λ=0), the the drai currets are equal Sice λ is small, the currets will early mirror oe aother eve if V out is ot equal to V GS1 We say that the curret I REF is mirrored ito i OUT Notice that the mirror works for small ad large sigals! Curret Mirror as Curret Source The output curret of M is oly weakly depedet o v OUT due to high output resistace of FET M acts like a curret source to the rest of the circuit 7
Small-Sigal Resistace of I-Source Improved Curret Sources Goal: icrease r oc Approach: look at amplifier output resistace results to see topologies that boost resistace R out >> r o Looks like the output impedace of a commosource amplifier with source degeeratio 8
Effect of Source Degeeratio R eq 1 g m ( 1 ) t o m S o it v = ( i g v ) r + v t t m gs o R S gs R S Equivalet resistace loadig gate is domiated by the diode resistace assume this is a small impedace Output impedace is boosted by factor ( 1+ gmrs) v v v = ir RS t S vt = ( it + gmrsit) ro + ir t S v R = + g R r Cascode (or Stacked) Curret Source Isight: V GS = costat AND V DS = costat Small-Sigal Resistace r oc : ( 1 ) R + g R r o m S o ( 1 ) R + g r r o m o o R g r >> r o m 0 o 9
Drawback of Cascode I-Source Miimum output voltage to keep both trasistors i saturatio: V = V + V i OUT OUT, MIN DS 4, MIN DS, MIN V > V V = V DS, MIN GS T0 DSAT V > V + V = V + V V D4 DSAT GS 4 GS GS 4 T 0 V = V + V V OUT, MIN GS GS 4 T 0 v OUT Curret Siks ad Sources Sik: output curret goes to groud Source: output curret comes from voltage supply 10
Curret Mirrors Idea: we oly eed oe referece curret to set up all the curret sources ad siks eeded for a multistage amplifier. The Itegrated Curret Mirror High Res Low Resis M 1 ad M have the same V GS If we eglect CLM (λ=0), the the drai currets are equal Sice λ is small, the currets will early mirror oe aother eve if V out is ot equal to V GS1 We say that the curret I REF is mirrored ito i OUT Notice that the mirror works for small ad large sigals! 11
Curret Mirror as Curret Source The output curret of M is oly weakly depedet o v OUT due to high output resistace of FET M acts like a curret source to the rest of the circuit Small-Sigal Resistace of I-Source 1
Improved Curret Sources Goal: icrease r oc Approach: look at amplifier output resistace results to see topologies that boost resistace R out >> r o Looks like the output impedace of a commosource amplifier with source degeeratio Effect of Source Degeeratio R eq 1 g m ( 1 ) t o m S o it v = ( i g v ) r + v t t m gs o R S gs R S Equivalet resistace loadig gate is domiated by the diode resistace assume this is a small impedace Output impedace is boosted by factor ( 1+ gmrs) v v v = ir RS t S vt = ( it + gmrsit) ro + ir t S v R = + g R r 13
Cascode (or Stacked) Curret Source Isight: V GS = costat AND V DS = costat Small-Sigal Resistace r oc : ( 1 ) R + g R r o m S o ( 1 ) R + g r r o m o o R g r >> r o m 0 o Drawback of Cascode I-Source Miimum output voltage to keep both trasistors i saturatio: V = V + V i OUT OUT, MIN DS 4, MIN DS, MIN V > V V = V DS, MIN GS T0 DSAT V > V + V = V + V V D4 DSAT GS 4 GS GS 4 T 0 V = V + V V OUT, MIN GS GS 4 T 0 v OUT 14
Curret Siks ad Sources Sik: output curret goes to groud Source: output curret comes from voltage supply Curret Mirrors Idea: we oly eed oe referece curret to set up all the curret sources ad siks eeded for a multistage amplifier. 15