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www.fairchildsemi.com AN-600 Design Guideline for Travel Adaper Applicaions Using FAN630A. Inroducion The FAN630A is a secondary-side synchronous recifier (SR) conroller used o drive an SR MSFET o improve converer efficiency. FAN630A is able o operae under boh Coninuous Conducion Mode (CCM) and Disconinuous Conducion Mode (DCM) while mainaining accurae SR conrol. FAN630A inegraes a shun regulaor and an inernal charge pump circui for low Bill of Maerial (BM) coun and small form facor. The oupu volage of he converer is used for providing bias o he secondary side, FAN630A conroller. Due o he charge pump circui inside, FAN630A can operae from lower converer oupu volage in Consan Curren (CC) mode. I also has an inernal cable drop compensaion funcion for precise consan oupu volage regulaion a he end of he cable. The gain for he cable drop compensaion is programmed exernally for boh high and low line inpu condiions. A ypical applicaion circui is illusraed in Figure. FAN630A is compaible wih variable-frequency as well as fixed-frequency PWM conrollers, and is maximum operaing frequency is 00 khz. In order o improve no-load power consumpion, a green mode funcion is uilized. In green mode operaion, FAN630A sops swiching o reduce he operaing curren o less han 500 µa hus minimizing swiching losses. SR urn-off is deermined by he FAN630A Linear Predic Conrol (LPC) algorihm which uses he principle of volsec balance. Deecing he drain volage of he SR MSFET insead of he drain curren using SR MSFET R DS(N) offers addiional flexibiliy wih regards o MSFET selecion. As a resul, power consumpion on he SR MSFET is significanly reduced. This aricle describes a design procedure and a design example using he FAN630A in a flyback converer for ravel adaper applicaions. A guideline for he Prined Circui Board (PCB) design along wih several design rouble shooing noes are also described. IN n: R 3 R REF L m N P N S RES C R Load R 4 R REF C DL DET Q Q C PN 0 5 6 5 R LPC GATE LPC RES CP CN CATHDE R 3 NC REF 6 7 CLAMP IN 8 9 DD CMRH 4 AGND AGND PGND CMRL 4 3 C CLAMP C DD R CMRL R CMRH Figure. Typical Applicaion Circui for Flyback Converer wih FAN630A 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0.
AN-600. peraion Principle. Power n and ff Sequence During iniial power on, he charge pump circui is enabled when he IN pin volage exceeds approximaely, resuling in DD being wice of IN. When DD = 3.35 (i.e. IN =.675 ), all inernal blocks in he FAN630A are biased and ready for operaion, excep for SR swiching. The SR gae signal will be generaed 3 ms afer DD = 3.35. If IN becomes more han.6, he inernal clamping circui clamps IN a.6 and DD a 5.. The charge pump circui is disabled when IN is higher han 8 (hyseresis ) and he clamping circui clamps IN a 5.5, resuling in DD = 5.5. During power off or when IN decreases below 7, he clamping volage is changed o.6 and he charge pump circui is again enabled clamping DD o 5.. The SR conroller remains acive as long as DD is greaer han 3. Figure shows he waveforms described above. IN 8 7 magneizing curren reurns o is iniial condiion afer one swiching cycle, as follows: L IN m n N, PWM L, DIS () Lm where IN is he inpu volage applied o he primary side of he ransformer, is he oupu volage of he converer (=IN for FAN630A), L m is he magneizing inducance of he ransformer, n is he urns raio of he ransformer, N,PWM is he primary swich urn-on ime, and L,DIS is he discharge ime of L m. GS DET Primary MSFET IN /n Body diode of SR MSFET Synchronous Recifier MSFET IN /n+ Body diode of SR MSFET.6 CLAMP 5.5 LPC DET / Blanking ime.6 I M,max DD 5.5 5..6 3.35 3 I M I DS I SR /n Charge Pump N I M,min Charge Pump FF and bypass CT Power N 3ms SR swiching Figure. Power n and ff Sequence. Linear Predic Conrol for DCM peraion As menioned previously, SR MSFET urn-off is deermined by he Linear Predic Conrol (LPC) algorihm. As such, he average volage applied o he inducor mus be zero over a swiching period during seady-sae operaion. Thus he produc of he charging volage and charging ime is equal o he produc of he discharging volage and discharging ime. AS shown in Figure 3 he ransformer curren (magneizing inducor curren) always ramps up from zero when a new swiching cycle sars. Similarly, he curren ramps back down o zero before he nex swiching cycle sars. Since he slope of he magneizing curren is deermined by he volage applied across he magneizing inducance, he vol-sec balance equaion shows when he 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 N,PWM CT, DIS L, DIS Figure 3. peraion of LPC in DCM Flyback Figure 3 shows he ypical LPC waveforms during DCM operaion, where I DS is he primary MSFET curren, I SR is he SR MSFET curren, and I M is he magneizing curren of L m. The discharge ime of he inernal iming capacior is less han he discharge ime of L m ( CT,DIS < L,DIS ) o guaranee he SR gae is urned off before he SR curren reaches zero. The LPC circui generaes a replica ( CT ) of he flyback ransformer magneizing curren using an inernal iming capacior (C T ), as shown in Figure 4. LPC is obained by dividing DET which is equal o IN /n+. RES is proporional o, while i CHR is proporional o DET and i DISCHR is proporional o RES. Thus C T is charged by i CHR - i DISCHR which is proporional o IN and discharged by
AN-600 i DISCHR which is proporional o, resuling in he waveform of CT being similar o he waveform of I M. IN LPC-TH 70m + - + - n: SEC DET 80 ns Q SR D SET CLR Q Q Turn off SR Gae o SR Gae frequency does no change significanly beween wo consecuive swiching cycles. As can be seen in Figure 6, CPC anicipaes he SR curren o cross zero laer han he acual zero crossing in DCM, while LPC predics he acual SR curren zero crossing insan more precisely. For CCM operaion, LPC anicipaes he SR curren o cross zero laer han he acual zero crossing. n he oher hand, CPC anicipaes he SR curren zero crossing insan properly in CCM. FAN630A uses he zero crossing anicipaion signals from LPC and CPC and whichever signal is inroduced firs riggers he urn-off of he SR swich. LPC TPERID(n) h TPERID(n+) ZCD R LPC S/H.0µA/ CT ichr idischr 0.445µA/ RES R3 LPC.PK(n) CT GS.PR R R4 Figure 4. Simplified LPC inernal block 3. Causal Funcion for Transien Mode Even hough he linear predic mehod anicipaes he SR curren zero crossing insan very effecively in DCM operaion, i has limiaions during ransien CCM operaion. This is because he magneizing curren does no reurn o is iniial condiion a he end of he swiching cycle, as illusraed in Figure 5. Thus, he LPC resuls in lae erminaion of he SR gae, which can cause shoo-hrough since boh primary side and secondary side MSFETs are on a he same. To guaranee reliable SR conrol over all operaing modes, a second SR conrol mehod called Causal Predic Conrol (CPC) is also employed in he FAN630A. GS.SR IM DEAD-CAUSAL CT Anicipaed zero crossing by LPC TPERID(n-) TPERID(n) Anicipaed zero crossing by CPC Figure 6. peraion of CPC in Transien CCM 3. Design Consideraions SEC CT I M I SR no same IN/N SR curren zero crossing insan prediced by LPC. peraing Frequency According o he specificaion for linear operaion range of he causal funcion, CAUSAL_LINEAR, he operaing frequency of he FAN630A is limied from 33 khz o 00 khz. In addiion, he maximum operaing frequency is also deermined by he specificaion of minimum LPC ime o enable he SR gae a high/low line, LPC-EN-H/L. If he urnon ime of he primary side MSFET, N,PWM is shorer han LPC-EN-H/L, he LPC volage is no recognized as a valid signal resuling in SR being disabled and efficiency lowered. Figure 5. Magneizing Curren Waveform during Transien in CCM CPC anicipaes he SR curren zero crossing insan based on he swiching period of he previous swiching cycle as illusraed in Figure 6. The causal predicive SR conrol algorihm is based on he assumpion ha he swiching. Allowable Turns of Transformer For a flyback converer operaing in DCM, he primary side MSFET drain volage ( DS.PRI ) oscillaes when he secondary side diode curren reaches zero. This oscillaion is caused by he resonance beween he effecive oupu capaciance of he primary MSFET and magneizing 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 3
AN-600 inducance of he ransformer. This also causes a similar oscillaion on he SR MSFET drain volage ( DS.SR ) as illusraed in Figure 7 and Figure 8, where he peak-o-peak ampliude of he SR drain volage can be as much as wice he oupu volage. As inpu volage is decreased, causing he oscillaion ampliude ( ) o be larger han he nominal SR drain volage ( IN /n+ ), he oscillaion on he LPC volage can cause inadverenly shrink he SR gae signal in he nex cycle since he oscillaion is clamped a he peak. To avoid abnormal operaion, i is recommended o design he proper urns raio of he ransformer such ha SR gae volage does no shrink when SR MSFET volage of 90% (0.9 DS.SR.PK ) is greaer han. Equaion () shows he maximum allowable urns raio o avoid he shrink of he SR gae signal. IN 0.9 n IN n. 0.9 IN where IN is he minimum inpu volage applied o he primary winding of he ransformer, aking ino consideraion of he ripple on C DL. I is also required o verify he design of he ransformer urns raio aking ino consideraion he funcionaliies of he conroller used in he primary side. DS.PRI DS.SR LPC IN+n IN IN/n+ LPC.PK = DS.SR/ IN > n 0.9 DS.SR.PK 0.9 LPC.PK n n () DS.PRI DS.SR LPC IN+n IN DS.SR.PK IN/n+ LPC.PK IN < n 0.9 DS.SR.PK 0.9 LPC.PK n n Can cause Shrink of SR Gae LPC.EN Figure 8. SR Gae Signal Shrink due o he Resonance wih IN < n 4. Design Procedure The FAN630A is divided ino wo noable pariions: an SR conroller o conrol he SR MSFET and a shun regulaor for providing an error signal used o regulae he oupus. The design procedure for he shun regulaor secion, i.e. feedback nework design procedure is described in he oher Fairchild Applicaion Noes such as AN-437, AN-450. A design procedure for he SR conrol and cable drop compensaion will be presened in his secion. For he design example, he sysem specificaions are as follows: Inpu volage range: 90 ~ 64 AC (50 ~ 60 Hz) Nominal oupu volage: 5 Minimum oupu volage in CC range: (40% of he raed value) Nominal oupu curren in CC Mode:.5 A Figure 9 shows he profile of he oupu volage and curren for he given example. Figure 7. Normal peraion wih IN > n 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 4
AN-600 N (5) min () Full load I N C (.5 A) Figure 9. upu olage and Curren Profile [STEP-] Deermine DD, CLAMP, and PN (beween CN and CP pin) Capaciors The oupu volage of he converer is conneced o he IN pin supplying bias volage, DD, o he FAN630A. If IN is lower han 8, i is clamped a.6 and doubled by he charge pump circui, which is supplied o he inernal bias circui mainained by an exernal capacior. Thus DD is 5.. If IN is higher han 8, i is clamped a 5.5 and supplied o he inernal bias circui direcly. Considering volage ripple, µf capaciors are recommended for DD, CLAMP, and PN capacior values. [STEP-] Deermine he Resisors on REF Pin FAN630A inegraes a shun regulaor wih low bias curren for reducing BM componen coun, as illusraed in Figure 0..5 Cable Comp. Inernal Shun Regulaor + REF 6 CATHDE o I R REF R REF Selecion of % olerance resisors for beer oupu regulaion is recommended. Since he maximum reference inpu curren is 4 µa, R REF can be as large as approximaely MΩ. However, using a lower R REF value will resul in beer response ime wih regards o following he oupu volage. The rade-off beween response ime and power consumpion wih regards o meeing sandby power requiremens mus be considered when opimizing he design of he R REF and R REF divider. (Design Example) The REF resisor is obained as: R R REF REF 5 3.5.5 By seing R REF = 9.09 kω, R REF is obained as 7.4 kω. Then he power consumpion on he resisors is as: 5 loss 0. 68 RREF RREF 9.09k 7.4k P mw [STEP-3] Deermine he Resisors on LPC and RES Pins Figure shows he FAN630A LPC and RES pin circuiry. ne volage divider is used for he LPC pin by dividing he DET volage, while a second volage divider is used for he RES pin by dividing he oupu volage. When calculaing he four resisors, i is firs necessary o deermine he range of he raio of LPC resisors ( = (R +R )/R ). Secondly, i is necessary o deermine he range of he raio of RES resisors ( = (R 3 +R 4 )/R 4 ) considering he deecion range of he RES pin. nce and he volage scaled-down raio, K ( / ), are deermined, is used o calculae he RES divider resisor values. The selecion f he four divider resisors begin by choosing he opimal resisance value for R and R 3 according o he sink curren for each pin. n: SEC Q SR o IN 4, AGND Figure 0. Typical Applicaion Circui for he Shun Regulaor Secion The oupu volage divider R REF and R REF should be deermined such ha he volage of he REF pin is.5, as follows: R R REF.5 REF (3) R R LPC LPC S/H.0µA/ DET i CHR C T CT i DISCHR 0.445µA/ RES R 3 RES R 4 Figure. Typical Applicaion Circui for LPC and RES Pins 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 5
AN-600. Deermine he range of LPC raio: There are hree condiions o deermine he range of he LPC raio, as depiced in Figure. LPC CNDITIN () LINE-L-5(Min) () A minimum inpu volage wih full load condiion, LPC should be higher han he SR enabled hreshold volage a low line and 5 oupu, LPC-HIGH-L-5, as follows: DET _ 90 AC (4) LPC HIGH L5 (max) where DET_90AC is he minimum DET when he inpu volage is minimized considering he ripple on he primary side inpu capacior C DL depending on he load condiion. DET_90AC is described as follows: DET _ 90 AC IN _ 90 AC (5) n where is he oupu volage, n is he urns raio of he ransformer, and IN_90AC is he minimum inpu volage on C DL applied o he primary side of he ransformer a 90 AC. Thus, IN _ 90AC n LPC HIGH L5 (max) () A low line inpu (5 AC ), LPC should be less han he high-o-low line hreshold volage on LPC pin a 5 oupu, LINE-L-5, o ensure he operaion range a low line, as follows: where Thus, DET _5 AC (max) DET _5 AC (max) LINE L5 (6) (7) IN _5 AC (8) (max) n IN _5 AC n LINEL5 (max) (3) In order o avoid ha he green mode operaion sops and reurns o normal operaion during no load operaion, LPC should be less han he hreshold volage on LPC rising edge a low line and 5 oupu, LPC-TH-L, as follows: (max) LPC TH L5 (9) (0) where (max) is he maximum DC oupu volage plus he maximum peak ripple volage. Thus, (max) () LPC TH L5 CNDITIN (3) CNDITIN () LPC-HIGH-L-5(Max) LPC-TH-L-5(Min) Figure. Condiions for Deermining. Deermine he range of RES raio: There are wo condiions o deermine he range of RES raio for normal operaion of FAN630A, as depiced in Figure 3. RES CNDITIN () CNDITIN ().5A DD - I RES Figure 3. Condiions for deermining () To ensure he linear operaion range of he RES pin, RES should be lower han he minimum value of DD minus. (max) () DD where DD is he minimum supply volage. Thus, (max) (3) DD () RES should be higher han he RES o assure he SR gae signal is enabled normally, as follows: (4) RES where is he minimum DC oupu volage plus he minimum peak ripple volage. Thus, (5) RES Taking an uninenional delay wih inernal parasiic capaciance ino accoun, R 4 is suggesed o be equal or less han 40 k. R is suggesed o be less han he 5 k. As shown in Figure 3, when he secondary sars o conduc curren, he SR MSFET drain-o-source volage, DS, is 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 6
AN-600 negaive. In order o avoid he LPC pin from being damaged by he negaive volage, he LPC pin inernally sources curren when LPC is less han 0. Therefore, R canno be oo small o clamp negaive volage on he LPC pin. Afer he resisance of R and R 4 are deermined, R and R 3 can be calculaed wih proper raio selecion. 3. Deermine he volage scaled-down raio K: The basic idea of he linear predic mehod is o esimae he insan when he magneizing curren of he ransformer goes back o is iniial condiion afer compleing one swiching cycle by emulaing he operaion of he magneizing inducor curren. Two volage-conrolled curren sources and an inernal iming capacior C T are used o emulae he charging and discharging of he magneizing inducance. The curren which charges he inernal capacior C T while LPC is high is given by Equaion (6) as: IN 6 6 i n CT 0 0.4450 (6) Whereas, he curren discharging he inernal capacior C T while LPC is low is given by Equaion (7) as: i CT 0.4450 6 (7) The curren-sec balance of CT which is equivalen o he vol-sec balance of he magneizing inducance is as follows: IN n 0.445 N, PWM 0.445 N, SR (8) where N,PWM is he urn-on ime of he primary side MSFET and N,SR is he urn-on ime of he SR MSFET. By subsiuing he volage scaled-down raio K (= / ) ino Equaion (8), Equaion (9) is obained as follows:.5 IN N, PWM N, SR (9) K n By seing K=.5, he vol-sec balance equaion is obained. Thus, he C T volage decreases o zero when he SR curren decreases o zero. Considering he olerance of he resisor dividers and inernal circui olerances, he coefficien K should be slighly larger han.5 o guaranee ha he SR gae is urned off before he SR curren reaches zero. (Design Example) Assume C DL = 4 µf wih a charging ime raio over a half line cycle period given as 0. (D ch ), he oupu volage ripple is ± 5%, he volage drop due o he load cable is 0., and he esimaed efficiency of he converer is 87%. Then IN_90AC can be obained as follows: IN_90 AC IN _ 90 AC ( 0.4) I D C f 5..5 0. 90 79.6 0.87 4 50 DL ch L,min where f L,min is he minimum line frequency. The firs condiion for he range of is obained using a given ransformer urns raio of 3 as follows: IN _ 90 AC n LPC HIGH L5 (max) 79.6 4.96 3 4.98 0.74 The second and hird condiions for he range of are as follows, respecively: IN _5 AC n LINE L5 (max) LPC TH L5 (max) 5.46 9.93 0.55 5 5.46 n.3.6 Therefore, he range of is obained as follows:.3 4.98 The firs and second condiions for he range of are as follows, respecively: (max) DD RES 5.46.3 5. 4.96.4 0.4 Therefore, he range of is obained as follows:.3.4 Based on experimenal resul, Selec K =.7 and =., hen he is obained as follows: K. 4.4.7 I mees he condiions: higher han.3 and lower han.4. So is chosen as 4.4. Selec R = k and R 4 = 3.4 k, hen R and R 3 can be calculaed as follows, respecively: R R R R 3 4 ( ( LPC RES ) k ) 0 k 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 7
AN-600 [STEP-4] Deermine he Compensaion Gain for he Cable Drop While one end of a charging cable is conneced o he oupu erminals of he ravel adaper, he phone-side baery is locaed a he oher end of he cable. Even if he oupu volage of he converer is regulaed exacly a is nominal value, he phone-side volage a he oher end of he cable is lower due o he cable impedance. As such, he more oupu curren, he more volage drop. In order o compensae for he volage drop measured across he charging cable, he FAN630A has a buil-in cable compensaion circui which provides regulaed consan volage a he phone side end of he cable, when operaing in C Mode. The volage drop across he cable is compensaed by adjusing he reference volage of he inernal shun regulaor in proporion o he oupu curren as shown in Figure 4. DD. In his case, he cable drop compensaion gain for low line and high line is solely deermined by he resisor on he CMRH pin. The CMRH and CMRL pins can be also shored o ground if no cable drop compensaion is required. To make i easy o find he compensaion resisance, a graph based on Equaions (0) and ()is illusraed, as shown in Figure 5. The y-axis is he oupu volage drop due o he cable which should be compensaed and he x-axis is he compensaion resisance. o 6 REF R REF Cable Comp. 4 3 CMRH CMRL PGND + -.5 4, AGND CATHDE R REF Figure 4. Cable olage Drop Compensaion The CATHDE pin of he FAN630A is ypically conneced o an opo-coupler o implemen feedback o he primary side conroller. The cable drop compensaion in FAN630A is programmed by exernal resisors on CMRH and CMRL pins, whose relaionship can be described as follows: R REF N, SR.5 0. 8N, SR RCMRH (0) RREF S R REF N, SR.5 0. 8N, SR RCMRL () RREF S where R CMRH and R CMRL are he exernal resisors on he CMRH and CMRL pins, respecively and S is he swiching frequency of he primary side conroller. I is recommended ha a 47 nf bypass capacior is placed in parallel wih he resisors for CMRH/L when he cable drop compensaion funcion is used for posiive feedback degradaion. Since he oupu curren is esimaed based on he conducion ime of he SR MSFET, he cable drop compensaion gain should be adjused if he operaing mode (CCM or DCM) changes wih line volage. Thus, FAN630A has wo pins for cable drop compensaion gain seing (CMRH and CMRL) for high/low lines, respecively. When he compensaion gain doesn have o be adjused wih line volage, connec he CMRL pin o (Design Example) Figure 5. olage Drop vs. R CMR Assuming a 4 AWG, m cable lengh is used (0.084 Ω/m), he volage drop a maximum oupu curren is obained as follows: R[ / m] l[ m] I 0.084.5 0. 05 According o he graph in Figure 5, R CMR is seleced as 5. kω in parallel wih a 47 nf bypass capacior on boh CMRH and CMRL pins. 5. Trouble Shooing Noes. Dead-Time Needs To Be Adjused If he SR dead-ime is oo large, i is recommended o decrease R or increase R of LPC pin. Then LPC is increased and he discharge ime of he C T capacior ( CT.DIS ) is prolonged o decrease he dead-ime, as shown in Figure 6. However, Equaion (7) mus sill be saisfied when increasing LPC. 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 8
AN-600 CT GS GS Increased LPC CT.DIS riginal Dead-Time Decreased Dead-Time Figure 6. Adjusing SR Dead-Time by increasing LPC In conras, if SR dead-ime is oo small, i is suggesed o decrease R 3 or increase R 4. Then RES is increased and he discharge ime of he C T capacior is reduced o increase he dead-ime, as shown in Figure 7. However, Equaion () mus sill be saisfied when increasing RES. A dead ime of 700 ns a full load is recommended for mass producion (MP). CT GS GS Increased RES CT.DIS riginal Dead-Time. FAN630A Is Unable To Ener Green Mode ne of he condiions o ener green mode is based on he LPC period. If he non-swiching sae remains longer han 330 µs ( GREEN-N ) measured beween LPC falling and LPC rising of he nex cycle, he SR circui eners green mode. If he FAN630A canno ener ino green mode, i is recommended o verify ha he non-swiching sae lass longer han GREEN-N and LPC is lower han LPC-TH under he given operaing condiion (see Equaion (0)). 3. SR Does No Swich If he FAN630A is no in green mode and he SR swich does no operae, ry he following: Firs, verify ha DD is a is nominal regulaed value. If DD < 4 or appears unsable, i is possible ha he IC is damaged, ry o change C DD or increase he capacior value o 0 µf. Second, check if LPC is equal o he DET / and if LPC migh be exceeding LPC-HIGH-L (Equaion (4)). Third, check if RES is equal o /. Addiionally, verify wheher here migh be an overshoo or undershoo during DET rising and falling deecion. If noise on he RES pin is excessive, due o poor PCB layou, a small capacior (several ens of pf) can be added in parallel wih R4. Fourh, add a resisor (around 0 kω) beween he GATE pin and PGND of he FAN630A o proec GATE pin from any negaive volage spikes during urning on. 4. SR Swiched for a while and Shus Down Repeiively In seady-sae, he SR MSFET swiches on and off in a swiching cycle, as deermined by he LPC or CPC funcions. However, since he charging and discharging of inducor curren are no always balanced during load and AC line ransien, he SR gae signal can be overlapped wih he nex gae signal of he primary MSFET. Therefore, FAN630A has several inegraed proecion funcions such as LPC-volage falling deec proecion, causal period proecion, and RES-volage drop proecion ha preven overlapping due o vol-sec imbalance. nce any of hese proecions are riggered, FAN630A will erminae SR swiching or shrink he pulse widh of he SR gae signal immediaely and hen reurn o normal operaion afer he abnormal condiions are cleared. Refer o he FAN630A daashee for he deailed descripions. Increased Dead-Time Figure 7. Adjusing SR Dead-Time by decreasing RES 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 9
AN-600 6. PCB Layou Guidelines Prined Circui Board (PCB) layou and design are very imporan for CCC swiching mode power supplies where he volage and curren can rapidly change. Applying proper PCB layou echniques minimize excessive Elecro- Magneic Inerference (EMI) and preven he power supply from being disruped during surge and Elecro-Saic Discharging (ESD) ess. As shown in Figure 8, C DL and C are he inpu and oupu capaciors, respecively, T is he isolaion ransformer, Q is he primary side main MSFET, and Q is he secondary side SR MSFET conrolled by he FAN630A. For opimal FAN630A performance, he following PCB layou design guidelines are recommended: The main power flows hrough he secondary side winding, C and Q. So i is beer o configure he loop, formed by he secondary side winding, C and Q, as small as possible. The power ground (for LPC ) should be conneced o power ground (for RES ) firs and hen boh are ogeher conneced o PGND pin (Trace PGND). The charge pump oupu provides driving power o he SR MSFET, so i is beer o make he pah from he GATE pin o he gae of he Q, and from he Q source o he ground of C 6 as small as possible. The power ground 3, 4 and 5 are conneced ogeher and hen conneced o he PGND pin of he FAN630A (Trace 3 4 5 PGND). Resisor R REF and R REF sense he oupu volage. The ground of R REF can be conneced o he ground of C o achieve opimal volage regulaion. The ground of he R REF should reurn o AGND of he IC direcly o minimize noise (Trace 6 AGND). Resisor R CMRH and R CMRL are used for cable drop compensaion. The grounds of boh resisors should be conneced ogeher firs and hen conneced o he AGND pin of he IC (Trace 7 AGND). A Y-CAP should be conneced o he C ground using a wide race on he secondary side as indicaed by he red wire shown in Figure 8. Finally, he AGND and PGND of he IC should be conneced ogeher wih one single wire as indicaed by he orange wire shown in Figure 8. I is imporan o make he ground races as wide as possible for lower parasiic inducance and beer noise immuniy. Lm T n: IN IM I SR R UT Y-Cap 3 R 4 R REF C R8 6 C DL DET Q R REF R7 C3 PT Q RES REF CATHDE Primary Side PGND Primary Side PGND R LPC R Secondary Side PGND 4 Secondary Side PGND RES IN REF GATE LPC PGNDDD C DD FAN630A CMRH AGND CMRL CP CN C4 CLAMP C CLAMP 3 R CMRH R CMRL 5 7 Figure 8. Recommended Layou 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 0
AN-600 7. Schemaic of Design Example This secion shows a design schemaic for a.5 W charger (5 /.5 A) using FAN50 and FAN630A as shown in Figure 9. An EPC76 core is used for he ransformer and he winding srucure is shown in Figure 0. L 470uH TX C 390uF/6.3 o (+) AC IN F A/50 U FD87A D~D4 FFM07 C6 470pF R4 34k C uf/400 C uf/400 CL 0 U FAN50 6 4 7 5 FB CMP SD SGND R 56k 8 H PGND GATE 0 CS DD S R 300K 9 3 R3 0 R6 0 C4 uf C3 470pF/k R5 00 R7 0 R8 0 C7 7pF D6 FFM07 D5 N448 R9 56.k R3 7.4k RS 4.3 NP R9A Q 74k FCU900N60Z NA RS.3 CY 00pF DET NS R9 k R 0 C3 nf Q FDMC8650L R0 k U3 FAN630_MLP C8 uf C5 uf 5 6 7 9 C8 uf CN CP GATE CLAMP DD AGND R3 0 0 3 NC AGND C9 390uF/6.3 LPC PGND 4 3 R3 90 R33 3k U FD87A IN 8 RES REF CATHDE CMRH CMRL R 00k 5 6 4 C9 47nF CATHDE R30 4k C4 00nF R0 0k C 47nF R6 N.C C3 470pF R4 3.4k R34 7.4k R4 8.66k R3 8k o (-) C5 6.8nF Figure 9. Schemaic of he FAN630A.5 W Design Example 3 S E Primary Winding 5 E Copper Shielding 6 7 S E Secondary Winding 5 4 S S E E Auxilliary Winding 3 S BBBIN E Primary Winding Figure 0. Transformer srucure Core: EPC-76 PC95, Bobbin: EPC-76. W- & W- are sandwich winding, four layers in oal. W consiss of one layer wih a cancellaion mehod. The number of urns for each layer is specified below. W3 consiss of one layer wih riple-insulaed wire. The leads of posiive and negaive; flying leads are 3.5 cm and.5 cm, respecively. W4 consiss of one layer for wire shielding 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0
AN-600 Winding Margin Tape (mm) Terminal (Pin) Wire Gauge (mm) Turns (T) Noe Bobbin W- 0 3 0.7 ψ* 6 ± 5 %, / k W Insulaion Tape T 0 4 5 0. ψ* 8 Winding by 0 5 X 0. ψ* 8 cancellaion Insulaion Tape T W3 0 7 6 0.6 ψ* 4 TEX-E Insulaion Tape T W4 0 5 X Copper Shielding Tigh Insulaion Tape T W- 0 3 0.7 ψ* Insulaion Tape 3 T Copper shielding o Pin 5 (ψ0.5mm) Insulaion Tape T 6 ± 5%, / K Specificaions Terminal(pin) Inducance(µH) Remark Primary-Side Inducance - 540 H ± 5% 80 khz, Primary-Side Effecive Leakage - < 30 µh Max. Shor All her Pins 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0
AN-600 8. Tes Resuls of Design Example Figure shows he experimenal waveforms under full load condiion (.5 A) and AC low line from a 5 /.5 W evaluaion board. The SR gae is urned off by causal funcion conrol in CCM operaion and has a dead ime beween he primary-side and secondary-side MSFET. Figure 3 shows he experimenal waveforms of CC operaion and he oupu volage reaches o.6 a AC low line. There is no apparen gae signal overlap beween he primary side and secondary side MSFETs, and he SR is sill conducing by he charge pump circui. Figure. Waveforms a Full Load & Low Line Figure 3. SR peraing wih Low (.6 ) in CC Regulaion Mode Figure shows he experimenal waveforms under full load condiion (.5 A) and AC high line. LPC urns he SR MSFET off o preven overlap wih primary MSFET in DCM operaion. Figure 4 shows he measured efficiency for differen load condiions a high/low inpu line volage. The average efficiencies a 5 AC and 30 AC are 87.6% and 86.55%, respecively. Figure 4. Measured Efficiency Figure. Waveforms a Full Load & High Line 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 3
AN-600 Relaed Daashees FAN630AMPX Synchronous Recificaion Conroller for Flyback and Forward Freewheeling Recificaion DISCLAIMER FAIRCHILD SEMICNDUCTR RESERES THE RIGHT T MAKE CHANGES WITHUT FURTHER NTICE T ANY PRDUCTS HEREIN T IMPRE RELIABILITY, FUNCTIN, R DESIGN. FAIRCHILD DES NT ASSUME ANY LIABILITY ARISING UT F THE APPLICATIN R USE F ANY PRDUCT R CIRCUIT DESCRIBED HEREIN; NEITHER DES IT CNEY ANY LICENSE UNDER ITS PATENT RIGHTS, NR THE RIGHTS F THERS. LIFE SUPPRT PLICY FAIRCHILD S PRDUCTS ARE NT AUTHRIZED FR USE AS CRITICAL CMPNENTS IN LIFE SUPPRT DEICES R SYSTEMS WITHUT THE EXPRESS WRITTEN APPRAL F THE PRESIDENT F FAIRCHILD SEMICNDUCTR CRPRATIN. As used herein:. Life suppor devices or sysems are devices or sysems which, (a) are inended for surgical implan ino he body, or (b) suppor or susain life, or (c) whose failure o perform when properly used in accordance wih insrucions for use provided in he labeling, can be reasonably expeced o resul in significan injury o he user.. A criical componen is any componen of a life suppor device or sysem whose failure o perform can be reasonably expeced o cause he failure of he life suppor device or sysem, or o affec is safey or effeciveness. 05 Fairchild Semiconducor Corporaion www.fairchildsemi.com Rev..0 4
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