BTA-6CW3G, BTA-8CW3G Triacs Silicon Bidirectional Thyristors Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. Features Blocking oltage to 8 olts On-State Current Rating of Amperes RMS at 9 C Uniform Gate Trigger Currents in Three Quadrants High Immunity to d/dt / s minimum at C Minimizes Snubber Networks for Protection Industry Standard TO-22AB Package Internally Isolated High Commutating di/dt 4 A/ms minimum at C Internally Isolated ( RMS ) These Devices are PbFree and are RoHS Compliant* MAXIMUM RATINGS (T J = C unless otherwise noted) Rating Symbol alue Unit Peak Repetitive OffState oltage (Note ) (T J = 4 to C, Sine Wave, to 6 Hz, Gate Open) BTA6CW3G BTA8CW3G On-State RMS Current (Full Cycle Sine Wave, 6 Hz, T C = 9 C) Peak Non-Repetitive Surge Current (One Full Cycle Sine Wave, 6 Hz, T C = C) DRM, RRM 6 8 I T(RMS) A I TSM A Circuit Fusing Consideration (t = 8.3 ms) I 2 t 26 A 2 sec NonRepetitive Surge Peak OffState oltage (T J = C, t = 8.3 ms) DSM/ RSM DRM / RRM + Peak Gate Current (T J = C, t 2 s) I GM 4. A Average Gate Power (T J = C) P G(A). W Operating Junction Temperature Range T J 4 to + C Storage Temperature Range T stg 4 to + C RMS Isolation oltage (t = 3 ms, R.H. 3%, T A = C) iso Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. DRM and RRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2 3 TRIACS AMPERES RMS 6 thru 8 OLTS MT2 4 TO22AB CASE 22A STYLE 2 MARKING DIAGRAM BTAxCWG AYWW ORDERING INFORMATION Device Package Shipping BTA6CW3G PIN ASSIGNMENT Main Terminal 2 Main Terminal 2 3 Gate 4 No Connection BTA8CW3G TO22AB (PbFree) TO22AB (PbFree) G x = 6 or 8 A = Assembly Location (Optional)* Y = Year WW = Work Week G = PbFree Package * The Assembly Location code (A) is optional. In cases where the Assembly Location is stamped on the package the assembly code may be blank. Units / Rail Units / Rail Semiconductor Components Industries, LLC, 22 September, 22 Rev. 2 Publication Order Number: BTA6CW3/D
BTA6CW3G, BTA8CW3G THERMAL CHARACTERISTICS Thermal Resistance, Characteristic Symbol alue Unit JunctiontoCase (AC) JunctiontoAmbient R JC.8 R JA 6 Maximum Lead Temperature for Soldering Purposes /8 from Case for seconds T L 26 C C/W ELECTRICAL CHARACTERISTICS (T J = C unless otherwise noted; Electricals apply in both directions) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Peak Repetitive Blocking Current ( D = Rated DRM, RRM ; Gate Open) T J = C T J = C I DRM, I RRM. 3 ma ON CHARACTERISTICS Peak On-State oltage (Note 2) (I TM = ±3 A Peak) TM. Gate Trigger Current (Continuous dc) ( D = 2, R L = 3 ) MT2(+), G() MT2(), G() I GT 3 3 3 ma Holding Current ( D = 2, Gate Open, Initiating Current = ± ma) I H ma Latching Current ( D = 2, I G = 42 ma) MT2(+), G() MT2(), G() I L 7 7 7 ma Gate Trigger oltage ( D = 2, R L = 3 ) MT2(+), G() MT2(), G() GT.3.3.3 Gate NonTrigger oltage (T J = C) MT2(+), G() MT2(), G() DYNAMIC CHARACTERISTICS Rate of Change of Commutating Current, See Figure. (Gate Open, T J = C, No Snubber) Critical Rate of Rise of OnState Current (T J = C, f = 2 Hz, I G = 7 ma, tr ns) Critical Rate of Rise of Off-State oltage ( D =.66 x DRM, Exponential Waveform, Gate Open, T J = C) 2. Indicates Pulse Test: Pulse Width 2. ms, Duty Cycle 2%. GD... (di/dt) c 4 A/ms di/dt A/ s d/dt / s 2
BTA6CW3G, BTA8CW3G oltage Current Characteristic of Triacs (Bidirectional Device) + Current Symbol DRM I DRM RRM I RRM Parameter Peak Repetitive Forward Off State oltage Peak Forward Blocking Current Peak Repetitive Reverse Off State oltage Peak Reverse Blocking Current I RRM at RRM on state I H TM Quadrant MainTerminal 2 + TM I H Maximum On State oltage Holding Current I H off state + oltage I DRM at DRM Quadrant 3 MainTerminal 2 TM Quadrant Definitions for a Triac MT2 POSITIE (Positive Half Cycle) + (+) MT2 (+) MT2 Quadrant II () I GT (+) I GT Quadrant I I GT + I GT () MT2 () MT2 Quadrant III () I GT (+) I GT Quadrant I MT2 NEGATIE (Negative Half Cycle) All polarities are referenced to. With inphase signals (using standard AC lines) quadrants I and III are used. 3
BTA6CW3G, BTA8CW3G 3 T C, CASE TEMPERATURE ( C) 2 9 9 8 P A, AERAGE POWER (W) 2 8 2 I T(RMS), RMS ON-STATE CURRENT (A) 2 I T(RMS), ON-STATE CURRENT (A) Figure. RMS Current Derating Figure 2. On-State Power Dissipation I T, INSTANTANEOUS ON-STATE CURRENT (A) T J = C T J = C r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)... 3 I H, HOLDING CURRENT (ma) 3 2 t, TIME (ms) Figure 4. Thermal Response MT2 NEGATIE MT2 POSITIE 4.... 2. 2. 3. T, INSTANTANEOUS ON-STATE OLTAGE () Figure 3. On-State Typical Characteristics 4 2 3 6 8 9 Figure. Holding Current ariation 4
BTA6CW3G, BTA8CW3G.3 I GT, TRIGGER CURRENT (ma) 2 4 Q Q2 Q3 D = 2 R I = 3 2 3 6 8 9 GT, TRIGGER OLTAGE ()..9.7..3. 4 Q Q3 Q2 D = 2 R I = 3 2 3 6 8 9 Figure 6. Gate Trigger Current ariation Figure 7. Gate Trigger oltage ariation (/ μ s) dv/dt, CRITICAL RATE OF RISE OF OFF STATE OLTAGE 4K 3K 2K K D = 8 pk T J = C R G, TO MAIN TERMINAL RESISTANCE (OHMS) Figure 8. Critical Rate of Rise of Off-State oltage (Exponential Waveform) I L, LATCHING CURRENT (ma) 8 7 Q2 6 Q Q3 4 3 2 4 D = 2 R I = 3 2 3 6 8 9 Figure 9. Latching Current ariation L L N47 2 RMS ADJUST FOR I TM, 6 Hz AC MEASURE I CHARGE TRIGGER CHARGE CONTROL NON POLAR C L TRIGGER CONTROL MT2 N94 G - + 2 Note: Component values are for verification of rated (di/dt) c. See AN48 for additional information. Figure. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt) c
BTA6CW3G, BTA8CW3G PACKAGE DIMENSIONS TO22 CASE 22A7 ISSUE AA H Q Z L G B 4 2 3 N D A K F T U C T SEATING PLANE S R J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.M, 982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.7.62 4.48.7 B.38.4 9.66.28 C.6.9 4.7 4.82 D..3.64.88 F.42.47 3.6 3.73 G.9. 2.42 2.66 H.. 2.8 3.93 J.4.22.36. K..62 2.7 4.27 L.4.6..2 N.9.2 4.83.33 Q..2 2.4 3.4 R.8. 2.4 2.79 S.4...39 T.23..97 6.47 U....27.4 ---. --- Z ---.8 --- 2.4 STYLE 2: PIN. MAIN TERMINAL 2. MAIN TERMINAL 2 3. 4. NOT CONNECTED ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patentmarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 63, Denver, Colorado 827 USA Phone: 336727 or 8344386 Toll Free USA/Canada Fax: 3367276 or 83443867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 828298 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 79 29 Japan Customer Focus Center Phone: 8387 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative BTA6CW3/D