SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING

SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING M Bartek 1, S M Sinaga 1, G Zilber 2, D Teomin 2, A Polyakov 1, J N Burghartz 1 1 Delft University of Technology, Lab of High-Frequency Technology and Components / DIMES Mekelweg 4, 2628 CD Delft, the Netherlands, e-mail: mbartek@ewitudelftnl 2 Shellcase Ltd, Manhat Technology Park, PO Box 48328, Jerusalem 96251, Israel ABSTRACT In this paper, Shellcase WLCSP technology is analyzed for electrical performance and its potential in RF packaging An equivalent circuit model is developed using parameter extraction from a physical model representing typical package geometries (31 x 31 mm 2, 48 I/Os) Analysis of the results indicates that due to its comparably low electrical parasitics (L = 3-11 nh), this package is suitable for lowpower RF/microwave applications Moreover, intrinsic flexibility of this packaging technology provides novel opportunities for RF enhancements As the Si substrate when bonded to a carrier is mechanically stabilized, it can be thinned or selectively removed to any extent Full through-substrate trenches provide an effective way of substrate crosstalk suppression Selective removal of lossy silicon substrate below spiral inductors provides high quality passives Possibility to implement cavities makes this package type also an attractive option for RF MEMS applications Key words: wafer-level packaging, RF packaging, crosstalk suppression, electrical modeling INTRODUCTION As the demand for ever-smaller electronic systems grows, manufacturers are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages The explosive expansion of mobile electronic terminals generates strong demand for high-performance, costeffective and miniaturized RF modules providing desired wireless connectivity Ideally, they should be realized as a single-chip solution and could easily be embedded into any electronic system Such System-on-Chip (SoC) RF ICs have set a challenge for packaging, especially at the low-end market segment where low-cost solutions are required The chip size package (CSP) and wafer-level packaging (WLP) resulting from this effort, have been introduced into manufacturing at an unprecedented rate The driving force behind is not only the reduced size and weight, but primarily the fact that the wafer-level chip-scale packaging (WLCSP) technology has potential of electrical performance improvement at a comparable or even reduced manufacturing cost and thus providing an improved performance-to-price ratio Moreover, the same processing steps that are used to achieve the WLP technology basic packaging goal, can also be adopted for implementation of an additional functionality at no or very limited additional cost As an example, packaging of RF silicon ICs with simultaneous integration of high-quality passives, antennas or isolation structures [1] or protection of MEMS structures [2] can be mentioned The emerging WLCSP technology and related integrated passive devices (IPDs) have proven to have capabilities of significant size reduction at a comparable cost and an improved electrical performance [3], [4] In this paper, results of our work on electrical modeling of Shellcase-type WLP solutions that was performed in the frame of the Blue Whale project [5], [6], are presented Next to that, the capabilities and added value for packaging of RF ICs are analyzed SHELLCASE-TYPE WLP SOLUTIONS The ShellCase-type WLCSP approach [7] is based on sandwiching of a thinned silicon substrate between two plates and redistribution of the electrical contacts from the die periphery into an area-array of solder bumps on the bottom plate Adhesive bonding of and silicon wafers using optical quality adhesives makes this technology highly suitable for optical sensors The ShellOP package is currently the technology of choice for miniature image sensors, eg VGA CMOS image sensor shown in Fig 1 (a) (b) Figure 1 A VGA CMOS image sensor packaged using Shellcase WLP technology: (a) front side; (b) back side This approach is highly flexible and allows variety of modifications as shown in Fig 2 The silicon substrate can be packaged with its active side up or down and the adhesive bonding can be performed selectively allowing for optical cavity implementation The latest package for image sensors is the ShellOC, a cavity type package which can, due to its high flexibility, be used for (RF) MEMS as well ShellOC package enables incorporating of single or double cavity either from one side or from both sides of the substrate It can be used for optical or non-optical applications It allows incorporating of optional optical

filters and selective removal of various areas in the silicon die as part of the packaging process Later we will discus how this features can be used for enhancements in RF applications of pre-formed solder spheres The process is completed by singulation into individual dies using dicing pad extensions adhesive silicon trenches thinned silicon adhesive bottom trenches exposed pads solder balls Figure 2 Overview of basic Shellcase packaging solutions [8] singulation Fig 3 shows schematically a typical WLP fabrication sequence used The processed silicon IC wafer with bonding pad extensions into scribe lanes is adhesively bonded to a wafer If required by application, an adhesive with optical quality in this step is used The substrate serves subsequently as a mechanical carrier allowing silicon substrate thinning down to 5-1 µm and trench forming beneath the pad extensions Then a second substrate is adhesively bonded resulting in silicon islands fully encapsulated by the adhesive At this stage, a compliant polymer layer beneath the future solder bumps is formed (not shown in Fig 3) enhancing the package mechanical reliability A V-shaped dicing blade is subsequently used to perform notching within the scribe lane regions The exposed pad extensions at each die periphery are then redistributed to the area array of solder balls on the bottom substrate This is done by sputtering and patterning of an Al layer, followed by solder mask deposition and solder bump forming using solder paste deposition or attachment Figure 3 Schematic WLCSP fabrication sequence used by Shellcase EQUIVALENT CIRCUIT MODEL OF PACKAGE INTERCONNECT High device speeds require accurate package models to assure the signal integrity of the die within the package and of the packaged die within the system For this purpose, an equivalent circuit model has been developed based on physical modeling of the package 3D structure Although a full validation of the achieved results would require frequency domain measurements on properly prepared samples, the modeling results can be considered as a good indication of the expected package performance The parameter (R, L, and C) extraction was done using Q3D Extractor from Ansoft [9] Q3D extractor is a software package that electrically characterizes three-dimensional interconnect structures, where lumped equivalent circuit models can be generated

Fig 4 shows the 3D physical model of a 48 I/O package used in the extraction process The equivalent lumped circuit model is shown in Fig 5 The input data for the extraction process are, next to the package geometry, also the material properties These were estimated from literature data or where required, own measurements have been performed [1] I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 1 Figure 4 Physical model of a 31x31 mm 2, 48 I/O package used to extract electrical parameters of the equivalent circuit model In 1 In 2 In N C12 C1 C2 C N Out 1 Out 2 Out N Figure 5 Circuit topology of the equivalent lumped circuit model used by Q3D Extractor Simulation results for selected package I/Os (see Fig 4) are summarized in Tables 1, 2 and 3 These data includes the shortest (I/O 1 or 3) and the longest (I/O 4) package I/O traces Table 1 lists the extracted capacitances in ff The capacitance to ground (Table 1 diagonal elements) was calculated as the capacitance between a particular I/O trace and a reference ground within the package positioned at the backside of the Si substrate Table 2 shows self- and mutual inductances in ph Table 3 lists the resistances in mohm at various frequencies (considering the skin effect) Table 1 Extracted capacitance values (in ff) for selected package I/Os (see Fig 4) Note: the diagonal elements are the capacitances between the n-th I/O and the reference ground at the backside of Si substrate I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 1 46 23 46 17 79 48 I/O 2 23 84 27 25 44 44 I/O 3 46 27 44 22 43 15 I/O 4 17 25 22 11 27 21 I/O 5 79 44 43 27 45 23 I/O 6 48 44 15 21 23 73 Table 2 Extracted self- and mutual inductances (in ph) of selected package I/Os at 1 GHz I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 1 24 85 35 45 18 24 I/O 2 85 84 85 26 38 89 I/O 3 35 85 23 9 35 37 I/O 4 45 26 9 11 93 22 I/O 5 15 38 35 93 24 84 I/O 6 24 89 37 22 84 59 Table 3 Extracted resistances (mω) of selected I/Os as function of the frequency R DC R total 1GHz 1GHz 5GHz 1GHz I/O 1 66 82 12 18 22 I/O 2 25 27 27 58 73 I/O 3 64 8 11 17 22 I/O 4 262 33 47 73 92 I/O 5 66 82 12 18 23 I/O 6 152 19 27 42 53 When Q3D Extractor calculates the AC resistance, it fixes the reference frequency at a default value of 1 MHz A reasonable estimate of resistance at any frequency f is then obtained by adding the AC and the DC resistance values: f R ( f ) = RDC + RAC, f s where R DC is the DC resistance component, R AC the AC component and f s is the reference frequency For the convenience, the values listed in Table 3 are the total resistance values For illustration, the simulated S-parameters of the shortest and the longest package I/O traces are shown in Fig 6 up to 1 GHz These results together with the data in the tables above indicate that the analyzed package has favorable high-frequency properties and is suitable for RF applications as a low-cost packaging solution

-2 2 4 6 8 1 Noise transmitter Noise receiver port 1 port 2-4 s21 (db) -6-8 -1 I/O 1 I/O 4 substrate coupling ~1 µm Silicon substrate -12 (a) 2 4 6 8 1 Figure 7 Schematic illustration of a crosstalk through silicon substrate Two single-ended front-side substrate contacts separated by 1 µm and a backside ground terminal are considered -1 R 2 =1382 Ω s11 (db) -2 I/O 1 port 1 port 2 I/O 4-4 -5 C 2 =22 pf C 2 =52 pf R 2 =234 Ω R 2 =234 Ω (b) Figure 6 Simulated S-parameters comparing the shortest (I/O 1) and the longest (I/O 4) traces of the package from Fig 4 C 2 =22 pf EFFECTS ON SUBSTRATE COUPLING To see the how much effect the parasitics produced by the package interconnect may bring, a substrate coupling problem is employed as an example Substrate coupling is a very common problem in mixed-signal integrated circuit Noise generated by the noisy digital circuit (eg inverter) can couple through the substrate into the analog/rf part (eg Low Noise Amplifier) and deteriorates its signal integrity In our previous work [11], capabilities of this package for crosstalk suppression using substrate thinning and trenching has been explored Figure 7 shows an illustration of substrate coupling for a specific case, which consists of two rectangular substrate contacts on a 1 µm thick, 5 Ωcm silicon substrate where the backside is grounded Its equivalent RC network circuit model is shown in Fig 8 To investigate influence of parasitics contributed by the package traces, these were added to the equivalent circuit model as shown schematically in Fig 9 Then some illustrative cases were selected and analysed using circuit simulator Overview of all cases is listed in Table 4 Cases 1-4 represent influence of the internal ground connection Cases 5 and 6 represent influence of short, not-coupled input/output traces And Cases 7 and 8 show the influence of coupled input/output traces Figure 8 An equivalent RC network circuit model of substrate coupling from Fig 7 port 1 port 2 substrate model Internal ground ground connection I/O Figure 9 Lumped circuit model used to investigate influence of package parasitics on crosstalk between two circuit terminals

Table 4 Overview of various cases compared in this study for their influence on substrate coupling For the lumped circuit model and I/O assignment, see Fig 9 and Fig 4, respectively Port 1 I/O Port 2 I/O Ground connection I/O Case 1 - - - Case 2 - - I/O 1 (short) Case 3 - - I/O 6 (medium) Case 4 - - I/O 4 (long) Case 5 I/O 1 I/O 1 - Case 6 I/O 1 I/O 1 I/O 4 (long) Case 7 I/O 1 I/O 2 - Case 8 I/O 1 I/O 2 I/O 6 (medium) The results for all cases summarized in Table 4 are shown in Figures 1a-c Case 1 (without any additional package traces) is used as a reference Figure 1a compares the cases where the noise signal is injected directly into the substrate, without any influence of package interconnect The internal package ground is connected through one of the package traces: the shortest, a medium-length and the longest trace are compared The results show that the impedance caused by the ground interconnect worsens the isolation and a proper grounding scheme is very important The longer the connecting trace, the higher is the crosstalk between the input and output ports Each case in Fig 1a uses a single independent interconnect, therefore, coupling with other interconnects is not considered In Figure 1b, the isolations achieved from structure using Case 5 and Case 6 are shown In these cases the signal is injected via the shortest package traces (I/O 1 and I/O 1 ) Optionally a long ground connection (Case 6) is used In all cases, the coupling between the package traces is neglected since the distance between them is considerably large The results indicate that the short, uncoupled input/output traces have only a small influence and that proper grounding scheme is of outmost importance In Fig 1c, isolations achieved for Case 7 and Case 8 are shown Here, the interconnects taken for input and output (I/Os 1 and 2) are next to each other, therefore, the capacitive and inductive coupling between them is taken into account (not shown in the lumped circuit model in Fig 9) Since the ground interconnect is considerably far, the coupling to it is neglected The results indicate that coupled input/output traces for critical signals should be avoided In summary, the results of above evaluation clearly illustrate that for the critical signal paths the shortest package I/Os having low parasitics and no mutual coupling have to be selected Particular attention is required to realize the connection of the internal package ground Isolation (db) Isolation (db) Isolation (db) -5-1 -15-2 -25-1 -15-2 -25 1 1 1 1 1-5 case 1 (ideal) case 2 (short I/O) case 3 (medium I/O) case 4 (long I/O) (a) 1 1 1 1 1-5 -1-15 -2-25 case 1 case 5 case 6 (b) 1 1 1 1 1 case 1 case 7 case 8 (c) Figure 1 Influence of package I/O parasitics on crosstalk between two substrate single-ended contacts (for the lumped circuit model and the description of the cases under investigation see Fig 9 and Table 4, respectively) (a) Influence of internal ground connection I/O trace length (b) Influence of short, not coupled traces and a long ground connection (c) Influence of coupled input/output traces and mediumlength ground connection POSSIBLE RF ENHANCEMENTS Due to its intrinsic fabrication flexibility, the Shellcase packaging solutions can easily be modified or extended to provide additional RF enhancements Some basic possibilities are shown in Fig 11 The silicon substrate after its bonding to one of the substrates, is mechanically stabilized and can be structured from the backside as needed

(thinned, trenched, selectively removed) As already mentioned, the through-substrate trenches are an effective way of substrate crosstalk suppression at low and medium frequencies Further improvement is possible by using shielding in the form of metallized and grounded trenches [11] REFERENCES [1] Mendes, P M, S M Sinaga, A Polyakov, M Bartek, J N Burghartz, and J H Correia, Wafer-Level Integration of On-Chip Antennas and RF Passives Using High-Resistivity Polysilicon Substrate Technology, Proc 54th ECTC, June 24, pp 1879-1884 [2] Reichl, H, and V Grosser, Overview and Development Trends in the Field of MEMS Packaging, Proc MEMS 21, pp 1-5, January 21 [3] Pienimaa, S K, and N I Martin, High density packaging for mobile terminals, Proc 51st ECTC, pp 1127-1134, 29 May-1 June 21 Figure 11 Schematic illustration of possible RF enhancements that at a minimum additional cost will significantly improve the package RF performance Silicon integrated planar inductors suffer from the substrate losses [12] Selective substrate removal of lossy silicon substrate beneath integrated spiral inductors can significantly improve their quality factor CONCLUSIONS In this work, suitability of a Shellcase-type WLCSP package for RF packaging has been analyzed and its potential for implementation of RF enhancements is shown The Shellcase-type WLP solutions, which is based on sandwiching of an IC silicon substrate between two plates, provide high fabrication flexibility and many optional features (eg one or two-side cavities for packaging of MEMS applications) In the fabrication sequence, the Si substrate is mechanically supported by a plate and can therefore be 3D structured allowing eg its thinning and partitioning by through-substrate trenches or its selective removal These features can be used for crosstalk suppression between various circuit blocks or integration of high-quality passives (spiral inductors) Although this package type has rather limited thermal dissipation capabilities, due to its high flexibility and low electrical interconnect parasitics, it is highly suitable for low-power RF applications including RF MEMS devices ACKNOWLEDGMENT The authors wish to acknowledge the technical staff of Dimes Technology Center for their technical assistance, and the Blue Whale project partners for technical support and input This work is supported by European Commission (project Blue Whale, IST-26) [4] Larson, L, and D Jessie, Advances in RF packaging technologies for next-generation wireless communications applications, Proc IEEE 23 Custom Integrated Circuits Conference, pp 323-33, 21-24 Sept 23 [5] http://hitecewitudelftnl/scripts/detailasp?id=414 (Blue Whale project description) [6] Van Veen, C, H J Bergveld, and T van den Ackerveken, Shellcase Packaging: A Novel Approach of Cross-Talk Suppression for System-on-Chip, Proceedings of European Microelectronics and Packaging Symposium, Prague, Czech Republic, 24, pp 125-13 [7] Badihi, A, Ultrathin Wafer Level Chip Size Package, IEEE Trans on Advanced Packaging, Vol 23, No 2, May 2, pp 212-214 [8] http://wwwshellcasecom/ [9] http://wwwansoftcom/ [1] Mendes, P M, A Polyakov, M Bartek, J N Burghartz, and J H Correia, Extraction of Glass- Wafers Electrical Properties Based on S-Parameters Measurements of Coplanar Waveguides, Proc ConfTele 23, June 18-2, 23, Aveiro, Portugal, pp 51-54 [11] Sinaga, S M, A Polyakov, M Bartek, and J N Burghartz, Substrate Thinning and Trenching as Crosstalk Suppression Techniques, Proceedings of European Microelectronics and Packaging Symposium, Prague, Czech Republic, 24, pp 131-136 [12] Burghartz, J N, and B Rejaei, On the Design of RF Spiral Inductors on Silicon, IEEE Transactions on Electron Devices, Vol 5, No 3, 23, pp 718-729