The Case for Oversampling

EE47 Lecture 4 Oversampled ADCs Why oversampling? Pulse-count modulation Sigma-delta modulation 1-Bit quantization Quantization error (noise) spectrum SQNR analysis Limit cycle oscillations nd order ΣΔ modulator Dynamic range Practical implementation Effect of various nonidealities on the ΣΔ performance EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1 The Case for Oversampling Nyquist sampling: Signal f s B Freq narrow transition AA-Filter f s >B +δ Sampler Nyquist ADC DSP Oversampling: Signal f s >> f N?? B Freq wide transition AA-Filter f s Mf N Sampler Oversampled ADC DSP Nyquist rate f N B Oversampling rate M f s /f N >> 1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page

Nyquist v.s. Oversampled Converters Antialiasing X(f) Input Signal f B frequency Nyquist Sampling f B f s f S ~f B Anti-aliasing Filter f s Oversampling frequency f B f S >> f B f s frequency EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3 Oversampling Benefits No stringent requirements imposed on analog building blocks Takes advantage of the availability of low cost, low power digital filtering Relaxed transition band requirements for analog anti-aliasing filters Reduced baseband quantization noise power Allows trading speed for resolution EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4

ADC Converters Baseband Noise For a quantizer with step size Δ and sampling rate f s : Quantization noise power distributed uniformly across Nyquist bandwidth ( f s /) N e (f) N B -f B f s / -f s / f B Power spectral density: e Δ 1 N(f) e fs 1 fs Noise is aliased into the Nyquist band f s / to f s / EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5 Oversampled Converters Baseband Noise fb fb Δ 1 SB N e( f )df df fb fb 1 fs N e (f) Δ fb 1 f N B s where for fb f s/ Δ SB0 -f s / -f B f B f s / 1 fb SB0 SB SB0 f s M fs where M oversampling ratio f B EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6

Oversampled Converters Baseband Noise fb SB0 SB SB0 f s M fs where M oversampling ratio fb X increase in M 3dB reduction in S B ½ bit increase in resolution/octave oversampling To increase the improvement in resolution: Embed quantizer in a feedback loop Predictive (delta modulation) Noise shaping (sigma delta modulation) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 7 Pulse-Count Modulation V in (kt) Nyquist ADC 0 1 t/t V in (kt) Oversampled ADC, M 8 0 1 t/t Mean of pulse-count signal approximates analog input! EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 8

Pulse-Count Spectrum Magnitude f Signal: low frequencies, f < B << f s Quantization error: high frequency, B f s / Separate with low-pass filter! EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 9 Oversampled ADC Predictive Coding v IN + _ ADC D OUT Predictor Quantize the difference signal rather than the signal itself Smaller input to ADC Buy dynamic range Only works if combined with oversampling 1-Bit digital output Digital filter computes average N-Bit output EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 10

Oversampled ADC Signal B Freq wide transition Analog AA-Filter f s Mf N Sampler E.g. Pulse-Count Modulator Modulator 1-Bit Digital f s1 M f N Decimator narrow transition Digital AA-Filter N-Bit Digital f s f N + δ DSP Decimator: Digital (low-pass) filter Removes quantization error for f > B Provides most anti-alias filtering Narrow transition band, high-order 1-Bit input, N-Bit output (essentially computes average ) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 11 Modulator Objectives: Convert analog input to 1-Bit pulse density stream Move quantization error to high frequencies f >>B Operates at high frequency f s >> f N M 8 56 (typical).104 Since modulator operated at high frequencies need to keep circuitry simple ΣΔ ΔΣ Modulator EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1

Sigma- Delta Modulators Analog 1-Bit ΣΔ modulators convert a continuous time analog input v IN into a 1-Bit sequence d OUT f s v IN + _ H(z) d OUT DAC Loop filter 1b Quantizer (comparator) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 13 Sigma-Delta Modulators The loop filter H can be either switched-capacitor or continuous time Switched-capacitor filters are easier to implement + frequency characteristics scale with clock rate Continuous time filters provide anti-aliasing protection Loop filter can also be realized with passive LC s at very high frequencies f s v IN + _ H(z) d OUT DAC EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 14

Oversampling A/D Conversion f s f s /M Input Signal Bandwidth Bf s /M Oversampling Modulator 1-bit @ f s Decimation Filter n-bit @ f s /M f s sampling rate M oversampling ratio Analog front-end oversampled noise-shaping modulator Converts original signal to a 1-bit digital output at the high rate of (MXB) Digital back-end digital filter Removes out-of-band quantization noise Provides anti-aliasing to allow re-sampling @ lower sampling rate EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 15 1 st Order ΣΔ Modulator In a 1 st order modulator, simplest loop filter an integrator H(z) z -1 1 z -1 v IN + _ d OUT DAC EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 16

1 st Order ΣΔ Modulator Switched-capacitor implementation φ 1 φ φ V i - + d OUT 1,0 +Δ/ -Δ/ EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 17 1 st Order ΔΣ Modulator v IN + -Δ/ v IN +Δ/ _ dout -Δ/ or +Δ/ DAC Properties of the first-order modulator: Analog input range is equal to the DAC reference The average value of d OUT must equal the average value of v IN +1 s (or 1 s) density in d OUT is an inherently monotonic function of v IN linearity is not dependent on component matching Alternative multi-bit DAC (and ADCs) solutions reduce the quantization error but loose this inherent monotonicity & relaxed matching requirements EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 18

1 st Order ΣΔ Modulator Analog input -Δ/ V in +Δ/ Tally of quantization error 1 X Q 1-Bit quantizer 3 Y Sine Wave z -1-1 1-z Integrator Comparator 1-Bit digital output stream, -1, +1 Instantaneous quantization error Implicit 1-Bit DAC +Δ/, -Δ/ (Δ ) M chosen to be 8 (low) to ease observability EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 19 1 st Order Modulator Signals 1.5 1 1st Order Sigma-Delta X Q Y X analog input Q tally of q-error Y digital/dac output Amplitude 0.5 0 Mean of Y approximates X -0.5-1 T 1/f s 1/ (M f N ) -1.5 0 10 0 30 40 50 60 Time [ t/t ] EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 0

ΣΔ Modulator Characteristics Quantization noise and thermal noise (KT/C) distributed over f s / to +f s / Total noise within signal bandwidth reduced by 1/M Very high SQNR achievable (> 0 Bits!) Inherently linear for 1-Bit DAC To first order, quantization error independent of component matching Limited to moderate & low speed EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 1 Output Spectrum Amplitude [ dbwn ] 30 0 10 0-10 -0-30 -40 Input -50 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] Definitely not white! Skewed towards higher frequencies Notice the distinct tones dbwn (db White Noise) scale sets the 0dB line at the noise per bin of a random -1, +1 sequence EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page

Quantization Noise Analysis Integrator Quantization Error e(kt) x(kt) Σ H( z) z 1 1 + z Σ Quantizer Model y(kt) Sigma-Delta modulators are nonlinear systems with memory difficult to analyze directly Representing the quantizer as an additive noise source linearizes the system EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3 Signal Transfer Function z H( z) 1 + z ω0 H( jω ) jω x(kt) Σ - Integrator H(z) y(kt) Signal transfer function low pass function: 1 HSig ( jω ) 1 + s ω0 Y( z) H( z) HSig ( z) z X( z) 1 + H( z) Delay Magnitude f 0 Frequency EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4

v i Σ - ω 0 jω Noise Transfer Function Qualitative Analysis v n v o v eq v i Σ - v f n f 0 ω0 jω v o f f 0 eq vn v f f 0 eq vn v Σ v i - ω0 jω v o f 0 Frequency Input referred-noise zero @ DC (s-plane) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5 STF and NTF Integrator Quantization Error e(kt) x(kt) Σ z H( z) 1 + z Σ Quantizer Model y(kt) Signal transfer function: Y( z) H( z) STF z X( z) 1 + H( z) Delay Noise transfer function: Y ( z) 1 NTF 1 z E( z) 1+ H ( z) Differentiator EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6

Noise Transfer Function Y( z) 1 NTF 1 z Ez ( ) 1 + Hz ( ) jωt / jωt / jωt / jωt jωt / e e NTF( jω) (1 e )e ( ω ) ( ω ) e jsin T / jωt / jπ / e e sin T / j( ωt π) / sin ( ωt /) e where T 1/ fs Thus: ( ω ) ( π ) NTF( f ) sin T / sin f / f s N ( f ) NTF( f ) N ( f ) y e EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 7 First Order ΣΔ Modulator Noise Transfer Characteristics Noise Shaping Function Low-pass Digital Filter N ( f ) NTF( f) N ( f ) y ( π f f ) 4sin / First-Order Noise Shaping s e f B f N Frequency f s / Key Point: Most of quantization noise pushed out of frequency band of interest EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 8

First Order ΣΔ Modulator Simulated Noise Transfer Characteristic Amplitude [ dbwn ] 30 0 10 0-10 -0-30 Signal Simulated output spectrum Computed NTF ( π ) N ( f) 4 sin f / f y s -40-50 0 0.1 0. 0.3 0.4 0.5 Frequency [f/f s ] EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 9 Quantizer Error For quantizers with many bits e Δ ( kt) 1 Let s use the same expression for the 1-Bit case Use simulation to verify validity Experience: Often sufficiently accurate to be useful, with enough exceptions to be very careful EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 30

First Order ΣΔ Modulator In-Band Quantization Noise ( ) ( ) ( π ) fs M fs M NTF z 1 z s NTF f 4sin f / f for M >> 1 Y B B Q ( ) ( ) S S f NTF z df 1 Δ f 1 s z e ( sinπ ft ) π jft df S Y π 1 Δ M 3 3 1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 31 Dynamic Range peak signal power S X DR 10log 10log peak noise power SY S S S S X Y X Y 1 Δ sinusoidal input, STF 1 π 1 Δ 3 3 M 1 9 3 M π 9 3 9 DR 10log M 10log + 30log M π π M DR 16 33 db 3 4 db 104 87 db DR 3.4dB ++ 30log M X increase in M 9dB (1.5-Bit) increase in dynamic range EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 3

Oversampling and Noise Shaping ΣΔ modulators have interesting characteristics Unity gain for input signal V IN Large in-band attenuation of quantization noise injected at quantizer input Performance significantly better than 1-Bit noise performance possible for frequencies << f s Increase in oversampling (M f s /f N >> 1) improves SQNR considerably 1 st order ΣΔ: DR increases 9dB for each doubling of M To first order, SQNR independent of circuit complexity and accuracy Analysis assumes that the quantizer noise is white Not true in practice, especially for low-order modulators Practical modulators suffer from other noise sources also (e.g. thermal noise) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 33 DC Input Amplitude [ dbwn ] 30 0 10 0-10 -0-30 -40-50 0 0.1 0. 0.3 0.4 0.5 Frequency [ f /f s ] DC input A 1/11 Doesn t look like spectrum of DC at all Tones frequency shaped the same as quantization noise More prominent at higher frequencies Seems like periodic quantization noise EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 34

Output 0. 0 Limit Cycle First order sigma-delta, DC input 0.6 0.4-0. -0.4 0 10 0 30 40 50 Time [t/t] DC input 1/11 Periodic sequence: 1 +1 +1 3-1 4 +1 5-1 6 +1 7-1 8 +1 9-1 10 +1 11-1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 35 Limit Cycle Noise Shaping Function Ideal Low-pass Digital Filter In-band spurious tone with f ~ DC input First-Order Noise Shaping f B f N Frequency f s / Problem: quantization noise is periodic Solution: Use dithering: randomizes quantization noise - Thermal noise acts as dither Second order loop EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 36

1 st Order ΣΔ Modulator ( ) 1 1 Y( z) z X( z) + 1 z E( z) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 37 nd Order ΣΔ Modulator Two integrators 1st integrator non-delaying Feedback from output to both integrators Tones less prominent compared to 1st order EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 38

nd Order ΣΔ Modulator ( ) Recursive drivation: Y X + E E + E n n n n n ( ) Using the delay operator z : Y( z) z X( z) + 1 z E( z) EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 39 nd Order ΣΔ Modulator In-Band Quantization Noise ( ) ( 1 z ) ( f ) 4 z H( z) 1 z G 1 NTF z NTF ( π ) sin f / f for M >> 1 B Y Q( ) ( ) z e B S S f NTF z df f s f s M M 1 Δ f 1 4 1 Δ 5 π 5 M 1 s s 4 ( sinπ ft) π jft 4 df EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 40

Quantization Noise nd Order ΣΔ Modulator Noise Shaping Function Ideal Low-pass Digital Filter nd -Order Noise Shaping First-Order Noise Shaping f B Frequency f s / EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 41 nd Order ΣΔ Modulator Dynamic Range peak signal power S X DR 10log 10log peak noise power SY S S S S X Y X Y 1 Δ sinusoidal input, STF 1 4 π 1 Δ 5 5 M 1 15 5 M 4 π 15 5 15 DR 10log M 10log + 50log M 4 4 π π M DR 16 49 db 3 64 db 104 139 db DR 11.1dB + + 50log M X increase in M 15dB (.5-bit) increase in DR EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 4

Digital audio application Signal bandwidth 0kHz Resolution 16-bit nd Order ΣΔ Modulator Example 16 bit 98 db Dynamic Range M DR 11.1dB ++ 50log M min 153 M 56 8 to allow some margin & also for ease of digital filter implementation Sampling rate (x0khz + 5kHz)M 1MHz EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 43 Higher Order ΣΔ Modulator Dynamic Range ( ) L 1 Y( z) z X( z) + 1 z E( z), L ΣΔ order S S S S X Y X Y Δ L 1 sinusoidal input, STF 1 π 1 L M 3 ( L + 1) M L π + 1 L+ 1 1 L+ 1 ( L + ) 3 1 DR 10log M L π DR L+ 1 3 ( L + 1) 10log +( L ) π L Δ + 1 10 logm X increase in M (6L+3)dB or (L+0.5)-bit increase in DR EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 44

ΣΔ Modulator Dynamic Range As a Function of Modulator Order L3 L L1 Potential stability issues for L > EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 45 Tones in 1 st Order & nd Order ΣΔ Modulator Higher oversampling ratio lower tones nd order much lower tones compared to 1 st Xincrease in M decreases the tones by 6dB for 1 st order loop and 1dB for nd order loop 1dB 6dB 1 st Order ΣΔ Modulator nd Order ΣΔ Modulator Ref: B. P. Brandt, et al., "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 6, pp. 618-67, April 1991. R. Gray, Spectral analysis of quantization noise in a single-loop sigma delta modulator with dc input, IEEE Trans. Commun., vol. 37, pp. 588 599, June 1989. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 46

nd Order ΣΔ Modulator Switched-Capacitor Implementation IN Dout EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 47 Switched-Capacitor Implementation nd Order ΣΔ Phase 1 Sample inputs Compare output of nd integrator At the end of phase1, S3 opens prior to S1 opening EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 48

Switched-Capacitor Implementation nd Order ΣΔ Phase Enable feedback from output to input of both integrators Integrate Reset comparator At the end of phase S4 opens before S EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 49 ΣΔ Implementation Practical Design Considerations Internal nodes scaling & clipping Finite opamp gain & linearity Capacitor ratio errors KT/C noise Opamp noise Power dissipation considerations EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 50

Switched-Capacitor Implementation nd Order ΣΔ Nodes Scaled for Maximum Dynamic Range Modification (gain of ½ in front of integrators) reduce & optimize required signal range at the integrator outputs ~ 1.7x input fullscale (Δ) Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 51 nd Order ΣΔ Modulator Switched-Capacitor Implementation The ½ loss in front of each integrator implemented by choice of: C C 1 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 5

nd Order ΣΔ Effect of Integrator Maximum Signal Handling Capability on SNR Effect of 1 st Integrator maximum signal handling capability on converter SNR Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 53 nd Order ΣΔ Effect of Integrator Maximum Signal Handling Capability on SNR Effect of nd Integrator maximum signal handling capability on SNR Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 54

nd Order ΣΔ Effect of Integrator Finite DC Gain V i φ 1 φ Cs - a + CI V o ( ) H z ( ) H z ideal Finit DC Gain Cs z 1 CI 1 z a z Cs 1+ a + Cs CI CI 1+ a 1 z Cs 1+ a + CI EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 55 nd Order ΣΔ Effect of Integrator Finite DC Gain log H ( s) a Ideal Integ. (ainfinite) Max signal level ω P1 0 a ω 0 a Integrator magnitude response f 0 /a Low integrator DC gain Increase in total in-band noise Can be shown: If a > M (oversampling ratio) Insignificant degradation in SNR Normally DC gain designed to be >> M in order to suppress nonlinearities EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 56

nd Order ΣΔ Effect of Integrator Finite DC Gain M / a Example: a M 0.4dB degradation in SNR Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 57 nd Order ΣΔ Effect of Integrator Overall Integrator Gain Inaccuracy Gain of ½ in front of integrators determined by ratio of C1/C Effect of inaccuracy in ratio of C1/C inspected by simulation EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 58

nd Order ΣΔ Effect of Integrator Overall Gain Inaccuracy Simulation show gain can vary by 0% w/o loss in performance Confirms insensitivity of ΣΔ to component variations Note that for gain >0.65 system becomes unstable & SNR drops rapidly EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 59 nd Order ΣΔ Effect of Integrator Nonlinearities u(kt) Ideal Integrator Delay v(kt) v(kt+ T) u(kt) + v(kt) With non-linearity added: 3 v(kt + T ) u(kt ) + α u( kt ) + α 3 u( kt )... 3 + v(kt ) + β v( kt ) + β 3 v( kt ) +... Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988 EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 60

nd Order ΣΔ Effect of Integrator Nonlinearities α β 0.01, 0.0, 0.05, 0.1% Simulation for single-ended topology Even order nonlinearities can be significantly attenuated by using differential circuit topologies Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 61 nd Order ΣΔ Effect of Integrator Nonlinearities α 3 β 3 0.05, 0.,1% 6dB 1Bit Simulation for single-ended topology Odd order nonlinearities (3 rd in this case) Ref: B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation A/D Converters, IEEE J. Solid-State Circuits, vol. 3, no. 6, pp. 198-1308, Dec. 1988. EECS 47 Lecture 4: Oversampling Data Converters 005 H. K. Page 6