1. Multivibrators A multivibrator circuit oscillates between a HIGH state and a LOW state producing a continuous output. Astable multivibrators generally have an even 50% duty cycle, that is that 50% of the cycle time the output is HIGH and the remaining 50% of the cycle time the output is LOW. In other words, the duty cycle for an astable timing pulse is 1:1 that use the clock signal for synchronization are dependent upon the frequency and clock pulse width to activate there switching action. Sequential circuits may also change their state on either the rising or falling edge, or both of the actual clock signal.
3 The following list are terms associated with a timing pulse or waveform: Active HIGH: if the state change occurs from a LOW to a HIGH at the clock s pulse rising edge or during the clock width. Active LOW: if the state change occurs from a HIGH to a LOW at the clock s pulses falling edge. Duty Cycle: this is the ratio of the clock width to the clock period. Clock Width: this is the time during which the value of the clock signal is equal to a logic 1, or HIGH. Clock Period: this is the time between successive transitions in the same direction, i.e, between two rising or two falling edges. Clock Frequency: the clock frequency is the reciprocal of the clock period, frequency = 1/clock period Clock pulse generation circuits can be a combination of analogue and digital circuits that produce a continuous series of pulses (these are called astable multivibrators) or a pulse of a specific duration (these are called monostable multivibrators). Combining two or more of multivibrators provides generation of a desired pattern of pulses (including pulse width, time between pulses and frequency of pulses).
4 There are basically three types of clock pulse generation circuits: Astable A free-running multivibrator that has NO stable states but switches continuously between two states this action produces a train of square wave pulses at a fixed frequency. Monostable A one-shot multivibrator that has only ONE stable state and is triggered externally with it returning back to its first stable state. Bistable A flip-flop that has TWO stable states that produces a single pulse either positive or negative in value. One way of producing a very simple clock signal is by the interconnection of logic gates. As NAND gates contains amplification, they can also be used to provide a clock signal or timing pulse with the aid of a single Capacitor and a single Resistor to provide the feedback and timing function. These timing circuits are often used because of there simplicity and are also useful if a logic circuit is designed that has unused gates which can be utilized to create the monostable or astable oscillator. This simple type of RC Oscillator network is sometimes called a Relaxation Oscillator.
5 Monostable Multivibrator Circuits Monostable Multivibrators or one-shot pulse generators are generally used to convert short sharp pulses into wider ones for timing applications. Monostable multivibrators generate a single output pulse, either HIGH or LOW, when a suitable external trigger signal or pulse T is applied. This trigger pulse signal initiates a timing cycle which causes the output of the monostable to change state at the start of the timing cycle, t 1 and remain in this second state until the end of the timing period, t 2 which is determined by the time constant of the timing capacitor, C and the resistor, R. The monostable multivibrator now stays in this second timing state until the end of the RC time constant and automatically resets or returns itself back to its original (stable) state. Then, a monostable circuit has only one stable state.
6 Suppose that initially the trigger input T is held HIGH at logic level 1 by the resistor R 1 so that the output from the first NAND gate U1 is LOW at logic level 0 (NAND gate principals). The timing resistor, R T is connected to a voltage level equal to logic level 0, which will cause the capacitor C T to be discharged. The output of U1 is LOW, timing capacitor C T is completely discharged therefore junction V 1 is also equal to 0 resulting in the output from the second NAND gate U2, which is connected as an inverting NOT gate will therefore be HIGH. The output from the second NAND gate, ( U2 ) is fed back to one input of U1 to provide the necessary positive feedback. Since the junction V 1 and the output of U1 are both at logic 0 no current flows in the capacitor C T. This results in the circuit being Stable and it will remain in this state until the trigger input T changes. If a negative pulse is now applied either externally or by the action of the push-button to the trigger input of the NAND gate U1, the output of U1 will go HIGH to logic 1 (NAND gate principles). Since the voltage across the capacitor cannot change instantaneously (capacitor charging principals) this will cause the junction at V 1 and also the input to U2 to also go HIGH, which in turn will make the output of the NAND gate U2 change LOW to logic 0 The circuit will now remain in this second state even if the trigger input pulse T is removed. This is known as the Meta-stable state.
7 The voltage across the capacitor will now increase as the capacitor C T starts to charge up from the output of U1 at a time constant determined by the resistor/capacitor combination. This charging process continues until the charging current is unable to hold the input of U2 and therefore junction V 1 HIGH. When this happens, the output of U2 switches HIGH again, logic 1, which in turn causes the output of U1 to go LOW and the capacitor discharges into the output of U1 under the influence of resistor R T. The circuit has now switched back to its original stable state. Thus for each negative going trigger pulse, the monostable multivibrator circuit produces a LOW going output pulse. The length of the output time period is determined by the capacitor/resistor combination (RC Network) and is given as the Time Constant of the circuit in seconds: T = 0.69RC Since the input impedance of the NAND gates is very high, large timing periods can be achieved.
8 As with the NAND gate circuit above, initially the trigger input T is HIGH at a logic level 1 so that the output from the first NOT gate U1 is LOW at logic level 0. The timing resistor, R T and the capacitor, C T are connected together in parallel and also to the input of the second NOT gate U2. As the input to U2 is LOW at logic 0 its output at Q is HIGH at logic 1. When a logic level 0 pulse is applied to the trigger input T of the first NOT gate it changes state and produces a logic level 1 output. The diode D 1 passes this logic 1 voltage level to the RC timing network. The voltage across the capacitor, C T increases rapidly to this new voltage level, which is also connected to the input of the second NOT gate. This in turn outputs a logic 0 at Q and the circuit stays in this Meta-stable state as long as the trigger input T applied to the circuit remains LOW.
9 When the trigger signal returns HIGH, the output from the first NOT gate goes LOW to logic 0 (NOT gate principals) and the fully charged capacitor C T starts to discharge itself through the parallel resistor R T connected across it. When the voltage across the capacitor drops below the lower threshold value of the input to the second NOT gate, its output switches back again producing a logic level 1 at Q. The diode D 1 prevents the timing capacitor from discharging itself back through the first NOT gates output. Then, the Time Constant for a NOT gate Monostable Multivibrator is given as: T = 0.8RC + Trigger in seconds One main disadvantage of Monostable Multivibrators is that the time between the application of the next trigger pulse T has to be greater than the RC time constant of the circuit.
10 Suppose initially that the trigger input is LOW at a logic level 0 so that the output from the first NOR gate U1 is HIGH at logic level 1. The resistor, R T is connected to the supply voltage so is also equal to logic level 1, which means that the capacitor, C T has the same charge on both of its plates. Junction V 1 is therefore equal to this voltage so the output from the second NOR gate U2 will be LOW at logic level 0. This then represents the circuits Stable State with zero output. When a positive trigger pulse is applied to the input at time t 0, the output of the first NOR gate U1 goes LOW taking with it the left hand plate of capacitor C T thereby discharging the capacitor. As both plates of the capacitor are now at logic level 0, so too is the input to the second NOR gate, U2 resulting in an output equal to logic level 1. This then represents the circuits second state, the Unstable State with an output voltage equal to +V cc. The second NOR gate, U2 will maintain this second unstable state until the timing capacitor now charging up through resistor, R T reaches the minimum input threshold voltage of U2 (approx. 2.0V) causing it to change state as a logic level 1 value has now appeared on its inputs. This causes the output to be reset to logic 0 which in turn is fed back (feedback loop) to one input of U2. This action automatically returns the monostable back to its original stable state and awaiting a second trigger pulse to restart the timing process once again.
11 This then gives us an equation for the time period of the circuit as: T = 0.7RC Where, R is in ohms and C in Farads We can also make monostable pulse generators using special IC s and there are already integrated circuits dedicated to this such as the 74LS121 standard one shot monostable multivibrator or the 74LS123 or the 4538B re-triggerable monostable multivibrator which can produce output pulse widths from as low as 40 nanoseconds up to 28 seconds by using only two external RC timing components with the pulse width given as: T = 0.69RC in seconds.
12 In this figure shows the circuit of a monostable multivibrator using NPN transistors. Here, the output of transistor Q 2 is coupled to the base of transistor Q 1 through the resistance R 1. On the other hand, the output of transistor Q 1 is coupled to the base of transistor Q 2 through the capacitor C 2. The capacitor C 1 is known as commutating capacitor or speed up capacitor. Its function is to speed up the circuit in making abrupt transitions between the ON and OFF states. The base of transistor Q 2 is returned to the V cc supply through a resistor R 3, while the base of transistor Q 1 is connected to the negative supply through a resistor R 2. The advantage of this biasing is that it keeps the transistor Q 1 OFF and Q 2 ON. This state is known as a stable state of the monostable multivibrator. The output of a monostable multivibrator is available at the collector terminal of either transistor (i.e., Q 1 or Q 2 ) as shown in the figure. However, the two outputs are the complement of each other i.e., when one of the output is at V cc level, the other is at V CE (sat) level.
13 Monostable Multivibrator Circuits Example 1 A 20 khz, 75% duty cycle square wave is used to trigger continuously, a monostable multivibrator with a triggered pulse duration t p of 5 μs. What will be the duty cycle of the waveform at the output (Q) of the monostable? Solution Since the duty cycle of the square wave is 75%, therefore the waveform for this is as shown in next figure (a). Now the monostable multivibrator is triggered once each time a new pulse arrives. The monostable multivibrator remains triggered only for a duration, t p = 5 μs. The waveform of the output Q of the monostable multivibrator is as shown next figure (b). It is evident from the Fig. (b) that the duty cycle of the output (Q) of the Monostable multivibrator is: 5 μs 100% = 10% 50 μs
14 Monostable Multivibrator Circuits Example 2 A monostable multivibrator is required to convert a 100 khz, 30% duty cycle square wave to a 100 khz, 50% duty cycle square wave. Find the values of R and C. Solution We know that a 100 khz, 30% duty cycle square wave is applied at the trigger input of the monostable multivibrator. This waveform is shown in next Fig. (a). In order to convert it to a square waveform with 50% duty cycle, we want that the monostable multivibrator should have, t p = 50% of the time period of 100 khz waveform. Now time period of 100 khz square wave: T = 1 f = 1 = 10 μs 100 khz t p = 0.5 10 μs = 5 μs
15 Astable Multivibrator Circuits Astable Multivibrators are the most commonly used type of multivibrator circuit. An astable multivibrator is a free running oscillator that have no permanent meta or steady state but are continually changing there output from one state LOW to the other state HIGH and then back again. This continual switching action from HIGH to LOW and LOW to HIGH produces a continuous and stable square wave output that switches abruptly between the two logic levels making it ideal for timing and clock pulse applications. As with the previous monostable multivibrator circuit mentioned earlier, the timing cycle is determined by the RC time constant of the resistor-capacitor, RC Network. Then the output frequency can be varied by changing the value(s) of the resistors and capacitor in the circuit.
16 The astable multivibrator circuit uses two CMOS NOT gates such as the CD4069 or the 74HC04 hex inverter ICs, or as in our simple circuit below a pair of CMOS NAND such as the CD4011 or the 74LS132 and an RC timing network. The two NAND gates are connected as inverting NOT gates. Suppose that initially the output from the NAND gate U2 is HIGH at logic level 1, then the input must therefore be LOW at logic level 0 (NAND gate principles) as will be the output from the first NAND gate U1. Capacitor, C is connected between the output of the second NAND gate U2 and its input via the timing resistor, R 2. The capacitor now charges up at a rate determined by the time constant of R 2 and C. As the capacitor, C charges up, the junction between the resistor R 2 and the capacitor, C, which is also connected to the input of the NAND gate U1 via the stabilizing resistor, R 2 decreases until the lower threshold value of U1 is reached at which point U1 changes state and the output of U1 now becomes HIGH. This causes NAND gate U2 to also change state as its input has now changed from logic 0 to logic 1 resulting in the output of NAND gate U2 becoming LOW, logic level 0.
17 Capacitor C is now reverse biased and discharges itself through the input of NAND gate U1. Capacitor, C charges up again in the opposite direction determined by the time constant of both R 2 and C as before until it reaches the upper threshold value of NAND gate U1. This causes U1 to change state and the cycle repeats itself over again. Then, the time constant for a NAND gate Astable Multivibrator is given as: T = 2.2RC For example: if the resistor R 2 = 10 kω and the capacitor C = 45 nf, the oscillation frequency of the circuit would be given as: f = 1 T = 1 2.2RC = 1 2.2 10 kω 45 nf = 1 khz Then the output frequency is calculated as being 1kHz, which equates to a time constant of 1mS so the output waveform would look like:
18 In this figure shown the circuit of a collector-coupled astable multivibrator using two identical NPN transistors Q 1 and Q 2. It is possible to have R c1 = R C2 = R c, R 1 = R 2 = R and C 1 = C 2 = C. In this case, the circuit is known as symmetrical astable multivibrator. The transistor Q 1 is forward biased by the V cc supply through resistor R 1. Similarly, the transistor Q 2 is forward biased by the V cc supply through resistor R 2. The output of transistor Q 1 is coupled to the input of transistor Q 2 through the capacitor C 1. Similarly, the output of transistor Q 2 is coupled to the input of transistor Q 1 through the capacitor C 2. As a matter of fact, the astable multivibrator may be thought of as two common-emitter amplifying stages. Each stage provides a feedback through a capacitor at the input of the other. Since the amplifying stage introduces a 180 phase-shift and another 180 phase-shift is introduced by a capacitor, therefore the feedback signal has a total phase-shift of 360 or 0. Thus the feedback is positive and the circuit works as an oscillator. In other words, because of capacitive coupling, none of the transistor can remain permanently cut-off or saturated. Instead the circuit has two quasi-stable states (ON and OFF) and it makes periodic transition between these two states. The output of an astable multivibrator is available at the collector terminal of either transistor (i.e., Q 1 and Q 2 ) as shown in the figure. However, the two outputs are 180 out of phase with each other. Therefore one of the output is said to be the complement of the other.
19 Switching Times and Frequency of Oscillation We have already discussed the waveforms at the base and collector of the transistors Q 1 and Q 2 in the circuit astable multivibrator. Each cycle of the waveform consists of time period T 1 and T 2. The time period T 1 represents the duration for which the transistor Q 1 is ON and Q 2 OFF Similarly, time period T 2 represents the duration for which the transistor Q 2 is ON and Q 1 is OFF. Both the time periods T 1 and T 2 depend upon charge of capacitors C 1 and C 2. It can be proved that the time periods: T 1 = 0.69 R 1 C 1 ON time for Q 1 and Total period of the wave: T 2 = 0.69 R 2 C 2 T = T 1 + T 2 = 0.69[ R 1 C 1 + R 2 C 2 ] ON time for Q 2 If R 1 = R 2 = R and C 1 = C 2 = C, then we have a symmetrical astable multivibrator, whose time periods T 1 = T 2 and the total time period: T = 0.69 R C + 0.69 R C = 1.38 R C
20 Home Work An astable multivibrator has component values, R 1 = R 2 = 20 kω and C 1 = C 2 = 100 pf Calculate the frequency of oscillator. Determine the period and frequency of oscillation for an astable multivibrator with component values R 1 = 2 kω ; R 2 = 20 kω and C 1 = 0. 01 μf, C 2 = 0. 05 μf. Determine the value of capacitors to be used in an astable multivibrator to provide a train of pulse 1 μs wide at a repetition rate of 100 khz. Given R 1 = R 2 = 20 kω.
21 Bistable Multivibrator Circuits The Bistable Multivibrators circuit is basically a SR flip-flop with the addition of an inverter or NOT gate to provide the necessary switching function. As with flip-flops, both states of a bistable multivibrator are stable, and the circuit will remain in either state indefinitely. This type of multivibrator circuit passes from one state to the other only when a suitable external trigger pulse T is applied and to go through a full (SET-RESET) cycle two triggering pulses are required. This type of circuit is also known as a Bistable Latch, Toggle Latch or simply T-latch. The simplest way to make a Bistable Latch is to connect together a pair of Schmitt NAND gates to form a SR latch. The two NAND gates, U2 and U3 form the bistable which is triggered by the input NAND gate, U1. When the input pulse goes LOW the bistable latches into its SET state, with its output at logic level 1, until the input goes HIGH causing the bistable to latch into its RESET state, with its output at logic level 0. The output of a bistable multivibrator will stay in this RESET state until another input pulse is applied and the whole sequence will start again. Then a Bistable Latch or Toggle Latch is a two-state device in which both states either positive or negative, (logic 1 or logic 0) are stable. Bistable Multivibrators have many applications such as frequency dividers, counters or as a storage device in computer memories but they are best used in circuits such as Latches and Counters.
Schmitt Trigger 22 In this figure shows the circuit of a Schmitt trigger (after the name of its inventor). It may be noted that the circuit, is, somewhat, like multivibrator circuits. The Schmitt trigger is used for wave-shaping circuits. It can be used for generation of square wave from a sine-wave input. Basically, the circuit has two opposite operating states as in all other multivibrator circuits. However, the trigger signal is not, typically, a pulse waveform but a slowly varying AC voltage. The Schmitt trigger is level sensitive and switches the output state at two distinct trigger levels. One of the triggering levels is called a lower-trigger level (abbreviated as L.T.L) and the other as uppertrigger level (abbreviated asu.t.l.).
Schmitt Trigger 23 The circuit of a Schmitt trigger consist of two identical transistors Q 1 and Q 2 coupled through an emitter R E. The resistors R 1 and R 2 form a voltage divider across the V cc supply and ground. These resistors provide a small forward bias on the base of transistor Q 2. These days Schmitt trigger is also available in the form of integrated circuit (IC). Fig. below shows a Schmitt trigger inverter connected as an oscillate (i.e. as an astable multivibrator) The signal at Knit is an approximate square wave with a frequency that depends upon the values of R and C. The relationship between the frequency and RC values is shown in Fig. below for these different Schmitt trigger integral circuits.
IC 555 timer is a one of the most widely used IC in electronics and is used in various electronic circuits for its robust and stable properties. It works as square-wave form generator with duty cycle varying from 50% to 100%, Oscillator and can also provide time delay in circuits. The 555 timer got its name from the three 5k ohm resistor connected in a voltage-divider pattern which is shown in the figure below. A simplified diagram of the internal circuit is given below for better understanding as the full internal circuit consists of over more than 16 resistors, 20 transistors, 2 diodes, a flip-flop and many other circuit components. 2. The IC 555 Timer
25 Comparator: The Comparator are the basic electronic component which compares the two input voltages i.e. between the inverting (-) and the noninverting (+) input and if the non-inverting input is more than the inverting input then the output of the comparator is high. Also the input resistance of an ideal comparator is infinite. Voltage Divider: As we know that the input resistance of the comparators is infinite hence the input voltage is divided equally between the three resistors. The value being V in 3 across each resistor. Flip-Flop: Flip-Flop is a memory element of Digitalelectronics. The output Q of the flip/flop is HIGH if the input at S terminal is HIGH and R is at LOW and the output Q is LOW when the input at S is LOW and at R is HIGH.
Astable Operation 26 One popular application of the 555 timer IC is as an astable multivibrator or clock circuit. The following analysis of the operation of the 555 as an astable circuit includes details of the different parts of the unit and how the various inputs and outputs are utilized. Figure next shows an astable circuit built using an external resistor and capacitor to set the timing interval of the output signal. Capacitor C charges toward V cc through external resistors R A and R B. The capacitor voltage rises until it goes above 2 3 V cc. This voltage is the threshold voltage at pin 6, which drives comparator 1 to trigger the flip-flop so that the output at pin 3 goes LOW. In addition, the discharge transistor is driven on, causing the output at pin 7 to discharge the capacitor through resistor R B. The capacitor voltage then decreases until it drops below the trigger level V cc 3. The flipflop is triggered so that the output goes back high and the discharge transistor is turned off, so that the capacitor can again charge through resistors R A and R B toward V cc.
Astable Operation 27 Figure (a) shows the capacitor and output waveforms resulting from the astable circuit. Calculation of the time intervals during which the output is high and low can be made using the relations: T high = 0.7 R A + R B C T low = 0.7R B C T period = T high + T low The period can be directly calculated from T period = 0.7 R A + 2R B C The frequency of the astable circuit is then calculated using F = 1 T = 1.44 R A + 2R B C
Astable Operation 28 Example 3 Determine the frequency and draw the output waveform for the circuit shown below. Solution T high = 0.7 R A + R B C = 0.7 7.5 10 3 + 7.5 10 3 0.1 10 6 = 1. 05 ms T low = 0.7R B C = 0.7 7.5 10 3 0.1 10 6 = 0. 525 ms T = T high + T low = 1.05 ms + 0.525 ms = 1. 575 ms F = 1 T = 1 1.575 10 3 635 Hz The waveform are drawn in the above slide.
29 Monostable Operation The 555 timer can also be used as a one-shot or monostable multivibrator circuit, as shown in Figure below. When the trigger input signal goes negative, it triggers the one-shot, with output at pin 3 then going high for a time period: Referring back to the main Figure, the negative edge of the trigger input causes comparator 2 to trigger the flip-flop, with the output at pin 3 going high. Capacitor C charges toward V cc through resistor R A. During the charge interval, the output remains high. When the voltage across the capacitor reaches the threshold level of 2 3 V cc, comparator 1 triggers the flip-flop, with output going low. The discharge transistor also goes low, causing the capacitor to remain at near 0 V until triggered again. Figure next (b) shows the input trigger signal and the resulting output waveform for the 555 timer operated as a one-shot. Time periods for this circuit can range from microseconds to many seconds, making this IC useful for a range of applications. T high = 1.1R A C
30 Monostable Operation Example 3 Determine the period of the output waveform for the circuit shown below, when triggered by a negative pulse. Solution T high = 1.1R A C = 1.1 7.5 10 3 0.1 10 6 = 0. 825 ms
31 Q1 An output pulse of 3 ms duration is to be generated by a 74LS122 one-shot. Using a capacitor of 50,000 pf, determine the value of external resistance required. Q1 Create a one-shot using a 555 timer that will produce a 0.5 s output pulse. Q1 Determine the values of the external resistors for a 555 timer used as an astable multivibrator with an output frequency of 10 khz, if the external capacitor C is 0.004 mf and the duty cycle is to be approximately 80%.
32 Q2 A 555 timer is configured to run as an astable multivibrator as shown in Figure. Determine its frequency.