Analog to Digital Conversion Florian Erdinger Lehrstuhl für Schaltungstechnik und Simulation Technische Informatik der Uni Heidelberg VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 1
Content Introduction ADC Characteristics / Terminology Sampling & Quantization ADC Properties: ENOB, INL, DNL ADC Architectures VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 2
Analog to Digital Conversion analoge Information ADC DSP DAC analoge Information Digitale Signal Processor Why process signals in the digital domain? Effect of reduced CMOS feature size and supply voltages: Do not really improve performance of analog signal processing, same Cs needed (see later) (kt/c noise) Digital circuits: more compact, faster, automated design less power dissipation à Convert analog signals into the digital domain for processing Rapid progress in digital signal progress has put high demands on AD converters VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 3
Basic Principle of Conversion ADC function: quantize signal, find digital representation digital output codes represent analog values converter finds output code which best matches input signal Basic ADC components: Sample & hold (S&H) circuit for the input signal Reference circuit to define the conversion steps A DAC to provide comparison levels Comparator to compare the input signal to the reference levels Some (digital) logic to store intermediate values, control switches etc. VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 4
ADC Characteristics (1) Resolution N: number of bits (8 bit à 2 8 = 256 steps) resolution is often confused with accuracy Signal to Noise Ratio SNR Effective Number Of Bits ENOB number of bits that are noise free lower bits can be used when averaging over many samples SNR, determines ENOB Transfer Characteristic: Missing codes, monotonicity Differential Non-Linearity DNL: quality of bin sizes Integral Non-Linearity INL: deviation from straight line Sampling Rate f s à speed Bandwidth BW, usually 0..f s /2 (Nyquist criterion) VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 5
ADC Characteristics (2) Accuracy Offset Error Gain Error can usually be fixed by calibration VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 6
ADC Characteristics (3) Full Scale Range FSR (max. / min. input) V fs = analog full scale signal that can be converted LSB / MSB: Least and Most Significant Bit A LSB = FSR / 2 N : step size in analog domain P ADC : power consumption FoM: Figure of Merit FoMs try to incorporate ADC properties in a single number for quick comparison give an estimate of the quality of the design most importantly: P ADC, BW and ENOB (SINAD) different FoMs exist classical: Walden FoM, newer: Schreier FoM definitions later VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 7
Sampling & Quantization ADC circuit performs two step process: sampling & quantization Sampling: conversion of a time continuous signal to a time discrete signal Nyquist CriterionSignal can be reconstructed if: f s > 2 x f max,sig Quantization: conversion of an analog (amplitude continuous) signal to a discrete value from a finite set of values Quantization is a non-linear operation, many input values are mapped to the same output value VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 8
Sampling Switch and sampling cap form an RC, R is noisy vn2 = sqrt(4ktr) The RC circuit filters the noise of the resistor Choose C so that thermal noise is less than quant. noise N req. C hold (*) V ktc 8 0.3 ff 1.2 mv 10 0.5 pf 0.3 mv 12 0.8 pf 70 uv 14 13 pf 17uV 16 213 pf 4.4uV (*) for V fs = 1V Oversampling converters can use smaller Cs à see later VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 9
Quantization Error low resolution (N<7) à quantization strongly depends on the signal, shows up as distortion for larger resolution: quantization can be approximated as white noise (in the band 0..f s /2) assumption: probability density of the signal is uniform across the conversion range à error varies linearly from -0.5 LSB to +0.5 LSB Quantization error power (Q 2 ) is estimation value of the variance: VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 10
Signal to Noise Ratio (SNR) Signal-to-quantization-noise: compares power of full scale sine wave to quant. error power With and we can approximate SN Q R = 62 db for a 10 bit ADC 74 db for a 12 bit ADC VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 11
Effective Number of Bits How many bits are noise free? Calculation uses signal-to-noise-and-distortion ratio (SINAD or SNDR) Effective Number of Bits (ENOB) is given by: (using eq. on prev. slide and solving for N) @ 8 bit, 0.5 LSB if loss is tolerable, @ 12 bit, 1bit ENOB is used in figure of merits to compare the performance of different ADCs (see later slides) VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 12
Differential Linearity The Differential Non-Linearity (DNL) is the deviation of each step to the ideal step A LSB : usually specified as max(dnl) sometimes: DNL rms VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 13
Integral Linearity The Integral Non-Linearity (INL) is deviation of the actual conversion curve from the ideal curve INL is calculated with where A(i) is the actual conversion curve usually, the extremes are stated: min,max(inl) VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 14
ADC ARCHITECTURES VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 15
ADC Architectures Two main categories: Nyquist rate / oversampled Nyquist rate ADCs: f sig,max = f s / 2 maximum achievable signal bandwidth determined by Nyquist criterion larger bandwidth achievable than with oversampled converters usually limited to 12-14 bits Oversampled ADCs: f sig,max << f s oversampling trades speed versus resolution very high resolution up to 18-20 bits achievable VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 16
Nyquist Rate ADCs Parallel Search (Flash Converters) one step à very fast requires 2 N reference levels and comparators à very expensive (power & area) scaling bad, exponential growth in power and area Sequential Search (Successive Approximation) reference level is switched, for instance in binary fashion N clock cycles for N bits scales better than flash converter Linear Search Converter compare to ALL reference levels must provide all reference levels successively extremely slow but with minimum amount of hardware can be made very robust w.r.t component variation VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 17
Flash ADC V in compared simultaneously to 2 N reference levels à therm. code. Very fast Expensive in power & area usually only 6-7 bit Design challenges: cap load @ input all comp. switch @ same time à XTALK matching of Rs Comp may not draw current VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 18
Two Stage Flash ADC 2 flash stages: coarse & fine 1 st stage: coarse conversion to for inst. half range for MSBs conversion to analog & subtraction from input signal 2 nd stage: fine conversion for LSBs U in 4 Bit Flash DAC x 16 4 Bit Flash 4 MSB 4 LSB slower than full flash architecture but substantially reduces cost (power & hardware) error correction possible in 2 nd stage by using more bits VLSI very Design popular - Mixed Mode for Simulation fast ADCs F. Erdinger, ZITI, Uni Heidelberg Page 19
Successive Approximation Compare input signal to DAC voltage (binary search) Output = DAC code generates V that is closest to V in 1 st : compare to V ref / 2 V in < V ref /2 V in < V ref /2 2 nd step: compare to V ref /4 compare to 3/2 V ref... N step required Comparator V in S&H Needs a precise DAC (matching) no way back if an early decision was wrong DAC V ref Logik VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 20
Single Slope ADC Principle: Convert input voltage to current Integrate current à V ramp Measure time until V ramp reaches V ref using dig. counter Use digital counter to measure time V rmp T = (V ref -V in )*C/I rmp V ref V in Slopes constant V in V ref time meas, dig. logic T t Problem: time depends on devices characteristic integration capacitor, current source sample V in VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 21
Dual Slope ADC Trick to solve dependency on devices: dual slope architect. Integrator Comparator V in V ref V sig = T 1 V in /RC R time meas. dig. logic V int Slope depend s on V in constant slopes 2 integrations to cancel out RC: Q sig = -T 1 x V in /R = -T 2 x V ref /R à V in = T 2 / T 1 x V ref Reset T 1 T 2 t à T 2 = V in /V ref x T 2 T1 is fixed, measure T2 for digital output value VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 22
Exersice In the mixed-mode simulation tutorial, you have designed a simple single slope ADC. Implement the current source with real devices and simulate the transfer characteristic. What determines the INL of your ADC? Estimate the INL, then simulate. Can you improve it? What determines the DNL? Make a simple dual slope design as shown in the slides. Make an analog simulation first. Change R and C. If you still have time, implement a comparator. Hint: start with a differential amplifier. VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 23
Algorithmic ADCs Type: sequential search SAR: uses DAC to provide reference levels Here: signal is modified and reference is constant Operation principle: N steps required for N bits, start with MSB if (Vin > Vref) dig[i] = 1; out = 2 x (Vin-Vref); else dig[i] = 0; out = 2 x Vin U in Comparator next stage U ref x 2 U ref Bit i VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 24
Algorithmic ADCs U in Comparator next stage U ref x 2 U ref Bit i Principle is quite simple à very popular Can stage single stage stage or pipeline with more stages Implementation: current mode (SPADIC), capacitive Quality of stage (comparator, x2) determines number of bits Error correction possible in every stage VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 25
Pipelining Use several (possibly identical) stages Compute result and forward to next stage Usually 1 bit / stage Very fast sample rate possible Digital output appears with latency, usually N clock cycles Well suited for algorithmic ADCs VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 26
Sigma Delta ADC Concepts: Oversampling Noise shaping Digital filtering Decimation à f clk >> f s à shift quant. noise out of signal band à filter out of band noise à output rate = f s 1 st order and higher order ΣΔ Modulators can be used à can get very complex Two principal topologies of ΣΔ Modulators exist: Time continuous Time discrete Here: time discrete modulators, 1 st order... VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 27
Oversampling Oversampling ratio is defined as Nyquist converter: Quantization power is uniformly distributed over frequency till half the sample rate Total noise power is found by integrating from 0 to f b BW f b f s = f s,ny f s = 4 x f s,ny VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 28
Reduced quantization error results in a reduced SNR and more ENOB: Oversampling is only effective when the quantization error can be approximated as white à not effective for DC signals A helper signal can be added to DC signals to be able to exploit oversample, for inst. white noise Oversampling can be employed to improve ENOB not only valid for ΣΔ-ADCs but for any ADC VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 29
Noise Shaping Basic idea: Oversampling creates an additional frequency range mirror images of the signal in the frequency domain around f s (created by DTFT) are shifted further away due to oversampling BW f s = f s,ny f b f s,ny 4 x f s,ny BW mirrors due to sampling f s = 4 x f s,ny f b f s,ny 4 x f s,ny VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 30
Noise Shaping Push the quantization noise to higher frequencies Filter in later stage to remove out of band noise In Z-domain we get: using a unit delay for J(z) we get: VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 31
Noise Shaping Noise transfer to the output in the frequency domain using z -1 = e jωπ : (NTF = Noise Transfer Function) total noise in band from 0 to f/2: Org. quantization energy Shaped quantization energy f b f s /2 freq (linear) VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 32
Noise Shaping In band noise: Reminder: this is only possible with oversampling In band noise power is related with a cube power OSR 1 from oversampling OSR 2 from noise shaping loop OSR x 2 à noise power / 8 (=9dB) à ENOB += 1.5 VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 33
Sigma Delta Modulator Scheme Basic Scheme: Input signal (X(s)) is oversampled with f s >> f b Signal component and quantization error are circulated in a loop Construct transfer function such that signal passes, quantization error filtered (in signal band) Output: bit stream, average is the input signal Simplest form, 1 st order modulator with 1 bit quantizer (ADC) and 1 bit DAC VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 34
Exercise 2 Implement a simple Sigma Delta Modulator using VerilogA Simulate for a couple of DC input values Reconstruct the input signal from the bit stream using an analog low pass filter VLSI Design - Mixed Mode Simulation F. Erdinger, ZITI, Uni Heidelberg Page 35