Low-Power Pipelined ADC Design for Wireless LANs

Low-Power Pipelined ADC Design for Wireless LANs J. Arias, D. Bisbal, J. San Pablo, L. Quintanilla, L. Enriquez, J. Vicente, J. Barbolla Dept. de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Univ. de Valladolid, Spain. V. Boccuzzi, M. Banu Agere Systems, 555 Union Boulevard, Allentown, Pennsylvania, 1819, USA

INDEX Design Functional Blocks Simulation Experimental Results Architecture Operational Amplifiers Monte Carlo Nonlinearity measurements Single Stage Flash ADCs Spectre SNR & SNDR measurements DACs EVM measurements Digital logic

Block Diagram of the ADC Digital Delay & Correction Logic Analog Input Even Samples Odd samples Stage Stage Stage Stage #1 #2 #8 #9 Stage Stage Stage Stage #1 #2 #8 #9 MUX Digital Output Digital Delay & Correction Logic

Simplified Pipeline Stage SHA Transfer function Vin +Vref/4 Φ1 Φ1 C2 C1 (Cs) (Cs) Φ1 Vres +Vref +Vref 2 1 11 Vref/4 Digital Output 1.5 bit Flash ADC +Vref Vref 1.5 bit DAC + Vref 2 Vref Vref Vref 4 +Vref 4 +Vref

Operational Amplifiers VDD First stage is a telescopic cascode: Vo+ Cc1 Cc2 Vi+ SC OUTER CMFB Vbpc CT INNER CMFB Vbnc Vbn GND Cc1 Cc2 Vi Vo Large DC gain: Short channel devices are OK Low Parasitics 2 cascode nodes available for compensation: Split Compensation Capacitors give more Gain Bandwidth or Phase Margin Two Common Mode Feedback loops: Good stability Outer loop is a SC circuit due to linearity requirements. Main Specs: Slew rate: 166 V/µ s Gain Bandwidth: 2 MHz

1.5 Bit, Flash, sub ADC Vi+ Vi Vref/4 Vref/4+ Φ1 Φ1 Φ1 Φ1 Cs Vcm Cs Cs Vcm bit 1 /bit 1 bit /bit Thermometer output Cs No charge pumping. Low Power Sensitive to charge injection from switches, but: Charge injection generate offsets Offsets are removed through digital correction

Comparator VDD M3 M4 CLK m11 Low gain Preamplifier Isolates input from kick back noise M7 M9 fast settling Out+ Full Swing Latch Fast regeneration. No metastability Out Rail to rail output Vi+ M1 M2 Vi M6 M8 Clocked output Avoids non CMOS levels Vbn M5 /CLK M1

1.5 Bit sub DAC Sb Thermometer input Ι I1 /I /I1 /φ2 a b c Switch control +Vref Vcm Vref Sc Sa Sa Sc +Dac Dac Sb High impedance output during phase 1. This saves 2 series switches in the S&H circuit High linearity thanks to wire crossing inversion

Digital Delay and Correction Circuit p2 p1 Analog Pipeline p2 p1 p2 p1 p2 p1 p2 p1 D9 p1 p2 p1 p2 p1 p2 p1 p2 d1 stage 1 d d1 stage 2 d d1 stage 3 d d1 stage 4 d d1 stage 5 d d1 stage 6 d d1 stage 7 d d1 stage 8 d c Σ s c Σ s c Σ s c Σ s c Σ s c Σ s c Σ s D8 D7 D6 D5 D4 D3 D2 p1 d1 stage 9 d D1 D (no amps)

System level Simulation Single INL run Monte Carlo.4 6 5 INL DNL.2 4 INL (LSB) Counts 3 -.2 2 1 -.4 128 256 384 512 64 768 896 124 ADC code.2.4.6.8 1 Max. nonlinearity Effects simulated: Capacitor mismatch Comparator offset Finite opamp gain Digital correction logic.

Transistor level Simulation (Spectre) Ampl. (db) -2-4 -6-8 2 4 6 8 1 12 14 16 18 2 Freq. (MHz) Simulated from extracted circuit Distortion < 6 db Power: 11.5 mw Analog: 9.75 mw Digital: 1.75 mw Effects not included: Mismatch Circuit noise

Area: 15 x 88 µm 2, including pads. Chip photograph

Measurements

Measured Nonlinearity Graphs 1 1.5.5 DNL (LSB) DNL (LSB) -.5 -.5-1 128 256 384 512 64 768 896 124 ADC code -1 128 256 384 512 64 768 896 124 ADC code 1 1.5.5 INL (LSB) INL (LSB) -.5 -.5-1 128 256 384 512 64 768 896 124 ADC code -1 128 256 384 512 64 768 896 124 ADC code - Code density measurement with sinusoidal input.

Frequency-domain measurements -2 6 55 1 MHz, CT 13.3 MHz, CT 13.3 MHz, sampled 19.3 MHz, sampled, INL corr. Amplitude (db) -4-6 -8 SNDR (db) 5 45 4-1 35-12 9 9.5 1 1.5 11 Frequency (MHz) 3-3 -25-2 -15-1 -5 Input amplitude (db) - Single and two-tone tests - Continuous time and sampled sinusoids.

EVM measurements with real OFDM signals IQ constellation 1 7 6 DUT E1439A -1 EVM (percent, rms) 5 4 3 2 1-1 1-25 -2-15 -1-5 5 Input amplitude (db) - 54-Mbit/s OFDM signal (IEEE 82.11a/g). 1 MHz carrier. - Agilent s EVM test equipment & software.

Operational Amplifiers Inner CMFB Outer CMFB Circuit Circuit Φ1 VDD Vcm Vo+ Vo Φ1 Φ1 Φ1 Φ1 CMFB Vo+ Vo Φ1 Φ1 Vbn GND CMFB Continuous time Diff. pair + level shifter Small differential input range Discrete time Highly linear. Large input range Two circuits operate on alternate clock phases

Performance summary Resolution Sampling Rate Power consumption 1 bits 4 MHz ADC: 11.7 mw Pin drivers: 1.3 mw (C L 4.5 pf) 2.5-V,.25-µm, CMOS (MOM cap.) Technology Chip Area (w. pads) 1.5.88 mm 2 (wo. pads) 1.2.58 mm 2 Nonlinearity DNL:.77 LSB SNR (max) SNDR (max) ENOB (max) INL: 1.15 LSB 61.3 db @ 1.6 MHz 57.6 db @ 1 MHz 57.8 db @ 19.3 MHz 59. db @ 19.3 MHz 9.3 bit @ 1 MHz 9.3 bit @ 19.3 MHz 9.6 bit @ 19.3 MHz Notes: Sampled input. Sampled input and static INL correction.

OFDM modulation Large number of subcarriers per channel. Orthogonality = No interference bw. subcarriers. T s A i cos ω i t ϕ i A j cos ω j t ϕ j dt OFDM modulation and demodulation are done via Fast Fourier Transforms (FFT).

OFDM (standard IEEE 82.11a/g) OFDM channel spectrum 64 sub carriers, but No DC carrier (f= Hz) No carriers close to adjadcent channels 1 MHz +1 MHz 54 used subcarriers. 64 QAM subcarrier im 48 carriers for data. Subcarrier modulation: QAM QAM constellations: 64 (54 mb/s), 16 or 4 points. re Symbol time (4 us) 288 bits FFT time (3.2 us)