Closed Loop Contolled LLC Half Bidge Isolated Seies Resonant Convete Sivachidambaanathan.V and S. S. Dash Abstact LLC seies esonant convete is the most suitable convete fo medium powe applications due to its high efficiency and wide input ange. This pape pesents the closed loop contolled LLC half bidge seies-esonant convete with isolated load. LLC esonant convetes display many advantages ove the conventional LC seies esonant convete, such as naow fequency vaiation ove wide ange of load, input vaiation and zeo voltage switching even unde no load conditions. High switching fequency opeation educes switching losses. Resonant tansition convetes ae chaacteized by low switching losses and low conduction losses. Powe facto impovement and high efficiency is achieved with a constant output voltage and is egulated by using closed loop contol and the simulation esults fo the convete is pesented. Index Tems DC-DC High fequency Convete; zeo voltage soft-switching convete (ZVS); LLC esonant tank cicuit. I. INTRODUCTION Nowadays the tend of powe supply maket is moe inclined to high switching fequency, high efficiency and high powe density. To meet this tend, esonant powe supply holds moe attaction, because it can be opeated in high switching fequency with high efficiency. Thee ae many esonant powe supplies such as Seies-Resonant Convete (SRC), Paallel-Resonant Convete (PRC) and Seies-Paallel Resonant Convete (SPRC). All the switching devices ae had-switched with abupt changes of cuents and voltages, which esults in sevee switching losses and noises. Meanwhile, the esonant technique pocess powe in a sinusoidal fom and the switching devices ae softly commutated. Theefoe, the switching losses and noises can be damatically educed. Fo this eason, esonant convetes have dawn a lot of attentions in vaious applications [1]-[2]. In isolated zeo-cuent-switched (ZCS) quasi-esonant convetes (QRC s), the leakage inductance of the tansfome can be utilized as a pat of the esonant switch to achieve zeo-cuent tun off [3]. High efficiency DC-DC convete fo wide load anges is necessay fo the applications which ae battey-poweed and have enegy consumption constains [4]. Fo a high efficiency DC-DC convete, the LLC seies-esonant half-bidge (SRHB) convete is gaining its populaity [5]. The main advantages of this soft-switching bidiectional convete with PWM ae minimum inducto size, zeo tun-on loss, low EMI without diode evese ecovey, and ease of contolle implementation [6]. The tend in powe convetes is towads inceasing powe densities. In ode to achieve this goal, it is necessay to educe powe losses, oveall system size and weight by inceasing the switching fequency [7]. Output voltage egulation is achieved by switching-fequency modulation [8]. Howeve, switching fequency inceases, as the output load deceases. Powe efficiency deceases because switching losses dominate at light load condition. In ecent decades, eseach on AC-DC convetes with powe facto coection and low total hamonic distotion (THD) is consistently enjoying inceasing inteests [9]. Soft switching technique is one of the most effective solutions to educe the switching loss in high-fequency opeations, which is an appoach made by eseaches and enginees in the field of powe electonics cicuits and systems [10]. Vaious types of soft switching cicuits have been poposed and applied to the powe convetes, opeated at a high switching fequency, leading to a geat eduction of the switching loss as well as mitigation of electomagnetic noise. Resonant convete topology has been used fo telecommunications and aeospace applications and it has been ecently poposed fo electic vehicles. Seconday batteies ae widely used in the application of esidential, industial, and commecial enegy stoage systems to stoe electicity and supply the load fo vaious types of electonic equipment [11]. On the othe hand, intoducing powe devices with a low on state voltage/esistance is the only way to educe the on-state losses. Supe junction stuctues make it possible to decease the on-state voltage and/o esistance dastically, which has been intoduced to MOSFETs and insulated gate bipola tansistos (IGBTs) [12]. Analysis and Design of a Half-Bidge Paallel Resonant Convete Opeating Above Resonance was given by Young-Goo Kang et al, [13]. Analysis and Design of High-Fequency Isolated Dual-Bidge Seies Resonant DC/DC Convete was given by Xiaodong Li and and Ashoka K. S. Bhat, [14]. Analysis and Design of a Double-Output Seies-Resonant DC DC Convete was pesented by Yu-Kang Lo et al, [15]. In the pesent wok open loop opeation and closed loop contolled LLC half bidge isolated seies esonant convete ae simulated and the esults ae pesented. Manuscipt eceived Novembe 9, 2011; evised Novembe 22, 2011. Sivachidambaanathan V is with Sathyabama Univesity, Chennai, India, (e-mail: sivachidambaam_eee@ya;hoo). S. S. Dash is the with EEE Deptament, SRM Univesity, Chennai, India. II. HALF BRIDGE RESONANT CONVERTER The cicuit diagam of a half bidge Seies Resonant Convete is shown in Fig.1. The esonant inducto L and 265
esonant capacito C ae in seies. They fom a seies esonant tank cicuit. The esonant inducto L m is connected acoss the pimay of the tansfome. The esonant tank will then in seies with the load. Fom this configuation, the esonant tank and the load act as a voltage divide. The cicuit consists of two switches Q 1 and Q 2. The convete cicuit switching losses and noises ae vey high due to had switching with abupt changes of cuents and voltages, the switching losses and noises can be damatically educed. Fo this eason, esonant convetes have dawn a lot of attentions in vaious applications. cicuit duing this peiod. In this mode, the cicuit woks like a Seies Resonant Convete with esonant inducto L and esonant capacito C. When the cuent in both inductos L and L m ae same, this mode ends. Also the cuent in output eaches zeo value. The opeation of mode 2, fo the half bidge esonant convete cicuit is shown in Fig.3. Fig. 3. Mode 2 opeation of Half Bidge Resonant Convete Fig. 1.Half bidge esonant convete By changing the fequency of input voltage, the impedance of esonant tank will change. This impedance will divide the input voltage with load. Since it is a voltage divide, the DC gain of SRC is always lesse than 1. At esonant fequency, the impedance of seies esonant tank will be vey small and all the input voltage will dop on the load. So, fo seies esonant convete, the maximum gain happens at esonant fequency. C. Mode 3 Mode 3 begins when the cuent in two inductos L and Lm ae equal. At the same time the output cuent eaches zeo value. The seconday side ectifie diodes D 1 and D 2 ae in evese biased. Tansfome seconday voltage is lowe than the output voltage. The inducto L, capacito C and inducto L m foms a esonant tank in seies. The Fig.4 shows the opeation of half bidge esonant convete in mode 3. When the MOSFET Q 1 is tuned off, this mode ends. III. HALF BRIDGE RESONANT CONVERTER OPERATION A. Mode 1 Fig. 2 shows the mode 1 opeation of half bidge esonant convete. This mode begins when Q 2 is tuned off. Immediately, esonant inducto L cuent is eveses and it will flow though the diode which is connected anti-paallel to the MOSFET Q 1, This povides a ZVS condition fo Q 1. Gate signal of Q 1 is applied duing this mode. When esonant inducto L cuent flow though the diode of Q 1, begins to ise, this will foce seconday diode D 1 conduct and the load cuent Io begin to incease. The inducto Lm is chaged with constant voltage. Fig. 4. Mode 3 opeation of Half Bidge Resonant Convete The next half cycle epeats the same set of modes by conducting and disconnecting MOSFET Q 2. IV. HALF BRIDGE LC SERIES RESONANT INVERTER Fig. 5 shows the half-bidge esonant invete fo the condition when M 1 is off and M 2 is ON. Since C 1 = C 2, the load cuent will be shaed equally by C 1 with the supply voltage. If the loop of V 1, C 1, R and L is consideed, the load cuent can be obtained by the equation di 1 L + Ri+ idt+ Vc 1 t= 0 = V1 (1) dt 2C 1 Fig. 2. Mode 1 opeation of Half Bidge Resonant Convete B. Mode 2 The MOSFET Q 1 is tuned on duing mode 1, cuent will flow though MOSFET Q 1. This mode begins when the esonant inducto L cuent becomes positive. Output ectifie diode D 1 conducts. The tansfome voltage is clamped at Vo. The paallel inducto L m is linealy chaged with output voltage, and hence it is inactive with esonant Fig. 5. Half Bidge LC Seies Resonant Invete The equation of cuent in the esonant cicuit fo C 1 = C 2 = 266
C is given by, V + V Rt 1 c 2 L i = sin ω te ω L The peak MOSFET cuent is equal to the peak load cuent and is expessed as, R V t 1 + V c 2 L I p = sin ω t p e ω L The ms load cuent I L (ms) is = I (4) I L 2 ( ms ) ms ( MOSFET The peak supply cuent is I 0.5 peak load cuent (5) s = ( p) p (2) (3) Fig. 7. Diving Pulse and Voltage acoss MOSFET M 1 V. LLC SERIES RESONANT HALF BRIDGE CONVERTER Fig. 6 shows the LLC-SRHB DC-DC convete. The cicuit consists of DC input souce, half bidge invete, LLC Resonant Convete, high fequency tansfome, full bidge ectifie, filte and load. The DC input voltage is inveted by means of high fequency AC using MOSFET half bidge invete. The pimay of the tansfome is connected to the invete tho LLC esonant tank cicuit. The tansfome seconday voltage is ectified using diode bidge ectifie then filte cicuit and load. Fig. 8. Diving pulse and Voltage acoss MOSFET M 2 Output voltage and cuent wavefoms ae shown in Fig.9 and Fig.10 espectively. Fom the esults, it is clea that the output voltage and cuent wavefoms ae smooth and ipple fee. Fig. 9. Output voltage Fig. 6. LLC SRHB convete The filte cicuit consists of capacito C f1, Inducto L f and capacito C f2 foms a pi filte. Scopes ae connected in the cicuit to measue the pulses and voltage acoss MOSFET M 1 and M 2, output of the esonant invete, output voltage, output cuent, etc. The esonant fequency f is detemined as (6) Fig. 10. Output cuent VI. SIMULATION RESULTS The Half bidge LLC seies esonant DC to DC convete is simulated using Matlab and the esults ae pesented. The diving pulses and the voltage acoss the MOSFET M 1 ae shown in Fig. 7 and MOSFET M 2 is in Fig.8. The esults shows that, when the pulse applied to the MOSFET s ae high the voltage acoss the MOSFETs ae low and vice vesa. VII. OPEN LOOP SYSTEM Fig.11 shows LLC half bidge convete with step input. A distubance is intoduced at the input by using two switches.the input DC voltage is changed by intoducing a step input. Due to this distubance, the input voltage is inceased. The voltage at the invete and hence the output voltage inceases. This gives an eo voltage at the output. In ode to get the desied output voltage and to educe the eo signal, closed loop pefomance is essential. 267
loop system. Fig.16 shows the input and output voltage wavefoms fo the open loop system. A step input voltage is intoduced at 0.15 sec. Due to this, the input voltage inceased at 0.15 sec onwads. The voltage acoss the invete and hence both pimay and seconday voltages ae also inceases at 0.15 sec. Results in output voltage inceased at the same time. Fig. 11. LLC Half Bidge Resonant convete with step input A. Cicuit Desciption fo Step Input Fig.12 shows the cicuit fo step input. It consists of two DC souce, one fo nomal voltage and the othe fo eo voltage which is to be added with the nomal ated voltage souce. The step vaiation of input voltage can be intoduced by two switches and two times. If the switch one is closed the nomal voltage is being applied to the cicuit. When the switch two is closed the two DC souces ae get connected in seies and the input voltage is inceased. Fig. 15. Tansfome pimay and seconday side amplitude wavefoms with step vaiation at input DC of open loop system Fig. 16. Input voltage and output voltage of open loop system Fig.12. Cicuit fo step input IX. CLOSED LOOP CONTROLLED CONVERTER VIII. SIMULATION RESULTS FOR OPEN LOOP SYSTEM Input DC voltage wavefom with step input vaiation is shown in Fig. 13. Peak value of pulse and output of the MOSFET M 1 with step vaiation at input DC wavefoms ae shown in Fig. 14. Fig. 17. Closed loop contol of LLC SRHB convete Fig. 13. Input DC voltage with step input The closed-loop cicuit model of the LLC Seies-Resonant Half-Bidge DC-DC Convete is shown in Fig.17. The closed loop system consists of compaato and PI contolle. The output voltage is sensed and it is compaed with the efeence voltage. The eo signal is sent to the PI contolle. The output of the PI contolle is given to the MOSFET. The output of the PI contolle contols the dependent souce. The steady state eo signal is educed by popely tuning the PI contolle. Scopes and displays ae connected to measue the input voltage, output voltage, etc. Fig. 14. Peak value of Pulse and output of MOSFET M 1 with step input Fig. 15 shows the tansfome pimay and seconday amplitude wavefoms with step vaiation at input fo the open X. SIMULATION RESULTS FOR CLOSED LOOP CONTROLLED CONVERTER Tansfome pimay and seconday side peak to peak voltage wavefoms fo the closed loop system ae shown in Fig.18. Fom the esults, as the input voltage inceases at 0.15 268
sec due to the step input, the amplitude of tansfome pimay and seconday side voltage would inceases at 0.15 sec. This eo voltage is educed in steps fom 0.2 sec onwads. Invete output voltage and cuent wave foms ae shown in Fig.22. Fom the wave fom it is clea that when the voltage cosses zeo, the cuent also cosses zeo point. The voltage is in phase with cuent wavefom. This esults in impoved powe facto. Fig. 18. Tansfome pimay and seconday side peak to peak voltage wavefoms fo closed loop system Output voltage and cuent wavefoms fo the closed loop convete ae shown in Fig.19 and Fig. 20. The esults shows that the output voltage and cuent inceases fom 0.15 sec, due to the step input vaiation. The same ae educed step by step due to the closed loop contol opeation. Fig. 22. Invete output voltage and cuent wavefom XI. CONCLUSION In this pape, ZVS based LLC SRHB DC-DC convete has with isolated load cicuit, fo both open loop opeation and the closed loop contolled convete ae simulated using MATLAB simulink and the esults ae pesented. The esults shows that the output voltage wave fom is smooth without ipple. The closed-loop system educes the steady state eo. High efficiency is achieved with a constant output voltage. Resonant convete topologies can be used to incease cicuit switching speeds, impoved powe facto and educed switching losses. Fig. 19. Output voltage fo closed loop system Fig. 20.Output cuent fo closed loop system Fig. 21. Input voltage fo open loop system and closed loop output voltage Fig.21 shows the input voltage fo the open loop system and closed loop output voltage. Fom the esults we obseved that, open-loop system has steady state eo. Fo closed-loop system, the contol cicuit takes pope action to educe the amplitude to the set value. The settling time is negligible. Fom the wave foms it is clea that the smooth DC output is obtained with LC filte. Thus, the closed-loop system educes the steady state eo. REFERENCES [1] Robet L. Steigewald, A Compaison of Half-bidge esonant convete topologies, IEEE Tansactions on Powe Electonics, Vol. 3, No. 2, Apil 1988. [2] A. F. Witulski and R. W. Eickson, Design of the seies esonant convete fo minimum stess, IEEE Tansactions on Aeosp. Electon. Syst, Vol. AES-22, pp. 356-363, July 1986. [3] Milan M.Jovanovic and Fed C. Y. Lee, DC Chaacteistics and Stability of Push-Pull and Bidge-Type Zeo-Cuent- Switched Quasi-Resonant Convetes, IEEE Tans. Powe Electon., vol. 4, no. 3, pp. 339-347, July 1989. [4] J. P. Lee, B. D. Min, T. J. Kim, D. W. Yoo, and B. K. Lee, A novel topology fo photovoltaic seies connected dc/dc convete with high efficiency unde wide load ange, in IEEE 2007 Powe Electonics Specialist Confeence, 2007, pp. 152-155. [5] Y. T. Jang, M. M. Jovanovic, and D. L. Dillman, Light-load efficiency optimization method, in IEEE 2009 Applied Powe Electonics Confeence and Exposition, 2009, pp. 1138-1144. [6] Wensong Yu and Jih-Sheng Lai, Ulta high-efficiency bidiectional dc-dc convete with multi-fequency pulse-width modulation, in IEEE 2008 Applied Powe Electonics Confeence and Exposition, 2008, pp. 1079-1084. [7] W. S. Choi and S. M. Young, Impoving system eliability using FRFET in LLC esonant convetes, in IEEE 2008 Powe Electonics Specialist Confeence, 2008, pp. 2346-2351. [8] M. Z. Youssef and P. K. Jain, A font-end self-sustained LLC esonant convete, in IEEE 2004 Powe Electonics Specialist Confeence, 2004, pp. 2651-2656. [9] M.M.A. Rahman, Single-phase single-stage 3-Level AC-to-DC seies esonant convete, IEEE EIT poceedings, 2004, pp, 569, 573. [10] D. M. Divan, The esonant dc link convete A new concept in static powe convesion, in Poc. Conf. Rec. IEEE IAS Annu. Meet, 1986, pp. 648 656. [11] Ying-Chun Chuang, Yu-Lung Ke, Hung-Shiang Chuang and Yu-Min Chen, Analysis and Implementation of Half-Bidge Seies Paallel Resonant Convete fo Battey Chages, IEEE Tans on Industial Appl, VOL. 47, NO. 1, 2011, pp 258 270. [12] J. S. Lai, B. M. Song, R. Zhou, A. Hefne, D.W. Bening, and C. C. Shen, Chaacteistics and utilization of a new class of low 269
on-esistance MOSgated powe device, IEEE Tans. Ind. Appl, vol. 37, no. 5, pp. 1282 1289, Sep./Oct. 2001. [13] Y. G. Kang, A. K. Upadhyay, D. L. Stephens (1991), Analysis and design of a half-bidge paallel esonant convete opeating above esonance, IEEE Tansactions on Industy Applications. Vol. 27, Mach-Apil 1991, pp. 386 395. [14] Xlaodong Li Bhat (2010), Analysis and Design of High fequency Isolated Dual Bidge Seies Resonant DC/DC Convete, IEEE Tans. on Powe Electonics, Vol.25, Issue.4, Apil. 2010, pp 850. [15] Yu-Kang Lo, Shang-Chin Yen, and Tzu-Heng Song (2007), Analysis and Design of a Double-Output Seies-Resonant DC DC Convete, IEEE Tans on Powe Electonics, Vol. 22, No. 3, May 2007, pp 952-959. V.Sivachidambaanathan has completed Diploma in Electical and Electonics Engineeing, DOTE, Chennai, India in 1994, AMIE degee in Electical Engineeing fom the Institution of Enginees (INDIA), Section A and Section B in 1997 and 2002, and M.E.degee in Powe Electonics and Industial Dives fom Sathyabama Institute of Science and Technology, Chennai, India in 2005. He is a life membe of Indian Society fo Technical Education. Pesently he is pusuing Ph.D. pogamme at Sathyabama Univesity, Chennai, India. He has published moe than 10 papes in Intenational Jounal and confeences. His eseach inteests include DC - DC convetes and powe facto coection convetes. D. S.S.Dash is pesently woking as a Pofesso and Head of the Depatment of EEE, SRM Engineeing College, SRM Univesity, Chennai, India. He has completed his gaduation in Electical Engineeing in the yea 1994. He got his M.E. in Powe Systems Engineeing fom Univesity College of Engineeing, Bula, Oissa, India in 1996 and obtained his Ph.D degee fom College of Engineeing, Guindy, Anna Univesity, Chennai, India in the yea of 2004. He was fomely a faculty membe of Anna Univesity, College of Engineeing, Guindy, Chennai, Inda. He has published moe than 50 papes in Intenational Jounal and confeences. His eseach aeas such as Modelling of FACTS Contolle, Powe Electonics and Dives, etc. He is a life membe of Indian Society fo Technical Education and Institution of Enginees, India. 270