CMOS Digital Integrated Circuits 74C4051AFT,74C4052AFT,74C4053AFT Silicon Monolithic 74C4051AFT,74C4052AFT,74C4053AFT 1. Functional Description 74C4051AFT:8-Channel Analog Multiplexer/Demultiplexer 74C4052AFT:Dual 4-Channel Analog Multiplexer/Demultiplexer 74C4053AFT:Triple 2-Channel Analog Multiplexer/Demultiplexer 2. General The 74C4051AFT, 74C4052AFT and 74C4053AFT are high-speed, low-voltage drive analog multiplexer/demultiplexers using silicon gate CMOS technology. In 3 and 5 systems these can achieve highspeed operation with the low power dissipation that is a feature of CMOS. The 74C4051AFT, 74C4052AFT and 74C4053AFT offer analog/digital signal selection as well as mixed signals. The 74C4051AFT has an 8-channel configuration, the 74C4052AFT has an 4-channel 2 configuration, and the 74C4053AFT has a 2-channel 3 configuration. The switches for each channel are turned ON by the control pin digital signals. All control inputs are equipped with a newly developed input protection circuit that avoids the need for a diode on the plus side (forward side from the input to the CC ). As a result, for example, signals can be permitted on the inputs even when the power supply voltage to the circuits is off. As a result of this input power protection, the 74C4051AFT, 74C4052AFT and 74C4053AFT can be used in a variety of applicatio, including in the system which has two power supplies, and in battery backup circuits. 3. Features (1) AEC-Q0 (Rev. ) (Note 1) (2) Wide operating temperature range: T opr = -40 to 5 (3) ow ON-resistance: R ON = 45 Ω (typ.) ( CC = ) R ON = 24 Ω (typ.) ( CC = ) (4) ow power dissipation: I CC = (max) (T a = 25 C) (5) igh noise immunity: I = 0.8 (max) CC = I = (min) CC = (6) Power down protection is provided on all control inputs. Note 1: This device is compliant with the reliability requirements of AEC-Q0. For details, contact your Toshiba sales representative. 4. Packaging TSSOP16B 20 Toshiba Corporation 1 Start of commercial production 2013-06
5. Pin Assignment 74C4051AFT 74C4052AFT 74C4053AFT 20 Toshiba Corporation 2
6. Marking 74C4051AFT 74C4052AFT 74C4053AFT 20 Toshiba Corporation 3
7. System Diagram 74C4051AFT 74C4052AFT 74C4053AFT 20 Toshiba Corporation 4
8. Truth Table Input Inhibit Input C* X Input B X Input A X: Don't care *: Except 74C4052AFT X ON Channel 74C4051AFT 0 1 2 3 4 5 6 7 None 9. Absolute Maximum Ratings (Note) ON Channel 74C4052AFT 0X, 0Y 1X, 1Y 2X, 2Y 3X, 3Y None ON Channel 74C4053AFT 0X, 0Y, 0Z 1X, 0Y, 0Z 0X, 1Y, 0Z 1X, 1Y, 0Z 0X, 0Y, 1Z 1X, 0Y, 1Z 0X, 1Y, 1Z 1X, 1Y, 1Z None Note Rating Supply voltage Input voltage Switch I/O voltage Input diode current I/O diode current Switch through current CC /ground current Power dissipation Storage temperature CC IN I/O I IK I I/OK I T I CC P D T stg (Note 1) -0.5 to 7.0-0.5 to 7.0-0.5 to CC + 0.5-20 ±25 ±25 ± 180-65 to 0 Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditio (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability andbook ( andling Precautio / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: 180 mw in the range of T a = -40 to 85. From T a = 85 to 5 a derating factor of -3.25 mw/ shall be applied until mw.. Operating Ranges (Note) ma ma ma ma mw Test Condition Rating Supply voltage Input voltage Switch I/O voltage Operating temperature Input rise and fall times Note: CC IN S T opr dt/dv CC = CC = CC = 5 ± 0.5 The operating ranges must be maintained to eure the normal operation of the device. Unused inputs must be tied to either CC or GND. to 0 to 0 to CC -40 to 5 0 to 200 0 to 0 0 to 20 / 20 Toshiba Corporation 5
11. Electrical 11.1. DC (Unless otherwise specified, T a = 25 ) Test Condition CC () Min Typ. Max igh-level input voltage I 1.5 3. 3.85 ow-level input voltage I 0.5 0.8 1.35 1.65 ON-resistance R ON IN = I or I I/O = CC to GND 200 45 24 86 37 Ω IN = I or I I/O = CC or GND 28 22 17 73 38 27 Difference of ON-resistance between switches R ON IN = I or I I/O = CC to GND 5 5 25 13 Ω Input/Output leakage current (Switch OFF) I OFF OS = CC or GND IS = GND to CC IN = I or I ±0.1 Input/Output leakage current (Switch ON, Output OPEN) I I/O OS = CC or GND IN = I or I ±0.1 Control input leakage current I IN IN = CC or GND ±0.1 Quiescent supply current I CC IN = CC or GND 20 Toshiba Corporation 6
11.2. DC (Unless otherwise specified, T a = -40 to 85 ) Test Condition CC () Min Max igh-level input voltage I 1.5 3. 3.85 ow-level input voltage I 0. 0.8 1.35 1.65 ON-resistance R ON IN = I or I I/O = CC to GND 8 46 Ω IN = I or I I/O = CC or GND 84 44 31 Difference of ON-resistance between switches R ON IN = I or I I/O = CC to GND 35 20 18 Ω Input/Output leakage current (Switch OFF) I OFF OS = CC or GND IS = GND to CC IN = I or I ±1.0 Input/Output leakage current (Switch ON, Output OPEN) I I/O OS = CC or GND IN = I or I ±1.0 Control input leakage current I IN IN = CC or GND ±1.0 Quiescent supply current I CC IN = CC or GND 20.0 20 Toshiba Corporation 7
11.3. DC (Unless otherwise specified, T a = -40 to 5 ) Test Condition CC () Min Max igh-level input voltage I 1.5 3. 3.85 ow-level input voltage I 0.5 0.8 1.35 1.65 ON-resistance R ON IN = I or I I/O = CC to GND 5 54 Ω IN = I or I I/O = CC or GND 5 55 39 Difference of ON-resistance between switches R ON IN = I or I I/O = CC to GND 45 25 23 Ω Input/Output leakage current (Switch OFF) I OFF OS = CC or GND IS = GND to CC IN = I or I ±4.0 Input/Output leakage current (Switch ON, Output OPEN) I I/O OS = CC or GND IN = I or I ±4.0 Control input leakage current I IN IN = CC or GND ± Quiescent supply current I CC IN = CC or GND 40.0 20 Toshiba Corporation 8
11.4. AC (Unless otherwise specified, T a = 25,, Input: t r = t f = 3 ) Phase difference between input to output Output enable time Output disable time Control input capacitance Common terminal capacitance Switch terminal capacitance Feedthrough capacitance Power dissipation capacitance Part Number 74C4051AFT 74C4052AFT 74C4053AFT 74C4051AFT 74C4052AFT 74C4053AFT 74C4051AFT 74C4052AFT 74C4053AFT 74C4051AFT 74C4052AFT 74C4053AFT ϕ I/O t PZ,t PZ t PZ,t PZ C IN C IS C OS C IOS C PD Test Condition R = 1 kω R = 1 kω Figure 1 R = 1 kω Figure 1 All types Figure 2 Figure 2 Figure 2 Figure 2 (Note 1) CC () C (pf) Note 1: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation. I CC(opr) = C PD CC f IN + I CC Min Typ. 1.2 2.6 0.8 1.5 0.3 0.6 3.3 4.2 1.6 2.1 6 9.6 7.2 3.2 5.1 2 23.4 13.1 8.2 5.7 5.6 5.6 0.5 0.5 0.5 24 Max 6 9 4 6 25 11 18 7 25 11 18 7 pf pf pf pf pf 20 Toshiba Corporation 9
11.5. AC (Unless otherwise specified, T a = -40 to 85,, Input: t r = t f = 3 ) Test Condition CC () C (pf) Min Max Phase difference between input to output ϕ I/O R = 1 kω 16 18 7 8 Output enable time t PZ,t PZ R = 1 kω Figure 1 20 32 22 16 Output disable time t PZ,t PZ R = 1 kω Figure 1 23 32 22 16 Control input capacitance C IN pf 11.6. AC (Unless otherwise specified, T a = -40 to 5,, Input: t r = t f = 3 ) Test Condition CC () C (pf) Min Max Phase difference between input to output ϕ I/O R = 1 kω 20 22 13 14 9 9.5 Output enable time t PZ,t PZ R = 1 kω Figure 1 23.5 37 18 25 19 Output disable time t PZ,t PZ R = 1 kω Figure 1 28.5 37 18 25 19 Control input capacitance C IN pf 20 Toshiba Corporation
11.7. Analog Switch (T a = 25 ) ) (Note) Part Number Test Condition CC () Typ. Sine Wave Distortion TD R = 1 kω, C = pf f IN = 1 kz IN = p-p IN = 4.0 p-p 0.1 0.03 % Maximum frequency respoe 74C4051AFT 74C4052AFT 74C4053AFT 74C4051AFT 74C4052AFT 74C4053AFT f MAX(I/O) IN is centered at ( CC /2). Adjust input for 0 dbm. Increase f IN frequency until db meter reads -3 db. R = Ω, C = pf, sine wave Figure 3 0 200 240 180 230 280 Mz Feed through attenuation (switch OFF) FT IN is centered at ( CC /2). Adjust input for 0 dbm. R = 600 Ω, C = pf, f IN = 1 Mz, sine wave Figure 4-45 -45 db IN is centered at ( CC /2). Adjust input for 0 dbm. R = Ω, C = pf, f IN = 1 Mz, sine wave Figure 4-65 -65 Crosstalk (control input to signal output) X talk R = 600 Ω, C = pf, f IN = 1 Mz, square wave (t r = t f = 6 ) Figure 5 60 0 m Crosstalk (between any switches) X talk IN is centered at ( CC /2). Adjust input for 0 dbm. R = 600 Ω, C = pf, f IN = 1 Mz, sine wave Figure 6-45 -45 db Note: These characteristics are determined by design of devices. 20 Toshiba Corporation 11
. AC Test Circuit Figure 1 t PZ, t PZ, t PZ, t PZ Figure 2 C IOS, C IS, C OS Figure 3 Frequency Respoe Figure 4 Feedthrough Attenuation 20 Toshiba Corporation
Figure 5 Cross Talk (control input to output signal) Figure 6 Cross Talk (between any two switches) 20 Toshiba Corporation 13
Package Dimeio : mm Weight: 0.055 g (typ.) Package Name(s) Nickname: TSSOP16B 20 Toshiba Corporation 14
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Please use Product in compliance with all applicable laws and regulatio that regulate the inclusion or use of controlled substances, including without limitation, the EU RoS Directive. TOSIBA ASSUMES NO IABIITY FOR DAMAGES OR OSSES OCCURRING AS A RESUT OF NONCOMPIANCE WIT APPICABE AWS AND REGUATIONS. 20 Toshiba Corporation