P007 Cool-ORing Series Universal High Side Active ORing Controller C Description The P007 Cool-ORing solution is a universal high-speed Active ORing controller C designed for use with N-channel MOSFETs in redundant power system architectures. The P007 Cool-ORing controller enables an extremely low power loss solution with fast dynamic response to fault conditions, critical for high availability systems. The P007 controls single or parallel MOSFETs to address Active ORing applications protecting against power source failures. The P007 has an internal charge pump enabling an ideal solution in 1 or 36-75 bus high-side Active ORing applications. The gate drive output turns the MOSFET on in normal steady state operation, while achieving highspeed turn-off during input power source fault conditions, that causes reverse current flow. The controller auto-resets once the fault clears. The MOSFET drain-to-source voltage is monitored to detect reverse current flow. The P007 has an internal charge pump to drive the gate of a high side N-Channel MOSFET above the C input. There is an internal shunt regulator at the C input for high voltage applications. Features Fast dynamic response to power source failure, with 80ns reverse current turn off delay time. 4A gate discharge current Forward Over Current Fault indication Accurate MOSFET drain-to-source voltage sensing nternal charge pump FET check at initial power-up 100 for 100ms, operation in high side application C under voltage fault detection Applications N+1 Redundant Power Systems Servers & High End Computing Telecom Systems High-side Active ORing High current Active ORing Package nformation The P007 is offered in the following packages: 10 Lead 3mm x 3mm DFN package Typical Applications: Figure 1: P007 High Side Active ORing for 1 Bus applications Figure : P007 referenced to in in high voltage high side Acti ve ORing applications Picor Corporation picorpower.com P007 Rev 1.3 Page 1 of 19
Pin Description Pin Name Pin Number Description PGND 1 GATE C 3 SGND 4 R 5 SP 6 Gate Turn Off Switch Return: This pin is the high current return path for the gate driver during turn off. Connect this pin to the low side of the C coupling capacitor and SGND. Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under normal operating conditions and when SP-SN > 6m, the GATE pin pulls high to approximately *C with respect to the SGND pin. The controller turns the gate off during a reverse current fault that is below the reverse voltage threshold (-6m) and when C is in Under oltage (7.15). Controller nput Supply: This pin is the supply pin for the control circuitry and gate driver. Connect a 1μF capacitor between the C pin and the SGND pin. oltage on this pin is regulated to 11.7 with respect to SGND by an internal shunt regulator. For high voltage supply applications connect a shunt resistor between the SGND and PGND pins and the supply return, as shown in Figure. C Return: This pin is the return (ground) for the control circuitry. Connect this pin to the low side of C decoupling capacitor. Controller nput Supply With Limiting Resistor: This pin is connected internally to C through a 40Ω resistor needed for Bus voltages greater than 10 and less than 14. Leave this pin open if unused. Positive Sense nput: Connect SP pin to the Source pin of the external N-channel MOSFETs. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. NC 7, 10 Not Connected: Leave pins floating. SN 8 FT 9 Negative Sense nput: Connect SN to the Drain pin of the external N-channel MOSFET. The polarity of the voltage difference between SP and SN provides an indication of current flow direction through the MOSFET. Fault Status Output: This open collector pin pulls low to indicate one of the several potential fault conditions may exist. The FT pin will pull low after a reverse or forward fault has been detected with a defined delay time (8μs). n addition, the FT pin will pull low when the controller input voltage is below the C under-voltage threshold C-SGND < 7. When C-SGND > 7.15 and 6m < SP-SN < 75m this pin clears (High). n high voltage applications this output must be translated with reference to the system return with external circuitry, see Figure 19. Leave this pin open if unused. Package Pin-Outs 10 Lead DFN (3mm x 3mm) Top view Picor Corporation picorpower.com P007 Rev 1.3 Page of 19
Absolute Maximum Ratings Note: All voltage nodes are referenced to SGND R SP, FT GATE PGND SGND, C SN (Continuous, T A 85 C) SN (100ms Pulse, T A 85 C) Storage Temperature -0.3 to 17.3 / 40mA -0.3 to 17.3 / 10mA -0.3 to 4 / 5A peak -0.3 to 3 / 5A peak 40mA -0.3 to 80 / 10mA 100 / 10mA -65 o C to 150 o C Operating Junction Temperature -40 o C to 140 C Soldering Temperature for 0 seconds ESD Rating 60 o C k HBM Electrical Specifications Unless otherwise specified: -40C < T J < 15C, C =10.5, R open, C c = 1uF, C GATE_PGND = 1nF, SGND=PGND=0 C Supply Parameter Symbol Min Typ Max Units Conditions Operating Supply Range (3) C-SGND 8.5 10.5 No C limiting Resistor Quiescent Current C 1.5.0 ma C = 10.5 C Clamp oltage C-CLM 11 11.7 1.5 C =3mA C Clamp Shunt Resistance R C 10 Delta C =10mA C Under-oltage Rising Threshold CUR 6.1 7.15 8.0 C Under-oltage Falling Threshold CUF 6 7.00 7.9 C Under-oltage Hysteresis CU-HS 100 150 00 m R Supply (R pin connected to in, C pin to bypass capacitor Figure 1) Recommended for 1 Bus applications Operating Supply Range R-SGND 10 14 Biased from R pin Quiescent Current R 3.0 5.5 10 ma R = 14 Bias Resistor R Bias 300 40 550 Ω DFFERENTAL AMPLFER AND COMPARATORS Common Mode nput oltage CM -3 3 SP to C, SN to C Differential Operating nput oltage (1) SP-SN -80 400 m SP-SN SP nput Bias Current SP 35 55 75 μa SP=SN=C SN nput Bias Current SN 35 55 75 μa SP=SN=C SN Leakage Current SN_Lg 7 9 ma SN = 80,SP=C=0 Picor Corporation picorpower.com P007 Rev 1.3 Page 3 of 19
Electrical Specifications (Continued) Unless otherwise specified: -40C < T J < 15C, C =10.5, R open, C c = 1uF, C GATE_PGND = 1nF, SGND=PGND=0 Parameter Symbol Min Typ Max Units Conditions DFFERENTAL AMPLFER AND COMPARATORS (Continued) Gate Enable Threshold RS-EN +1 +6 +11 m SN = 10.5 @ 5 C Reverse Comparator Threshold RS-TH -11-6 - m SN = 10.5 @ 5 C Reverse Comparator Hysteresis RS-HY 10 1 14 m SN = 10.5 @ 5 C Reverse Fault to Gate Turn-off Response Time t RS 80 150 ns SP-SN = +50m to -50m step to 90% of G max Forward Comparator Threshold FWD-TH 50 75 300 m SN = 10.5 @ 5 C Forward Comparator Hysteresis FWD-HY 15 5 35 m SN = 10.5 @ 5 C GATE DRER Gate Source Current G-SC -0-15 μa G = G-Hi 1, C =3mA Pull Down Peak Current to PGND (1) G-PGND 1.5 4.0 A Pull-down Gate Resistance to PGND (1) R G-PGND 0.3 G-PGND = 1.5 @ 5C AC Gate Pull-down oltage to PGND (1) G-PGND 0. DC Gate Pull-down oltage G-SGND 0.8 1. G =100mA, in reverse fault Gate Drive oltage to C G-Hi 7.0 8.0 11 G =-0μA, C =3mA 8.0 9.0 11 G =-μa, C =3mA Gate Fall Time t G-F 10 5 ns 90% to 10% of G max. Gate oltage G-ULO 0.7 1 0.7 1 GATE DRER (R pin connected to in, C pin to bypass capacitor Figure 1) Gate Drive oltage to R Fault Status: FT Fault Output Low oltage G-Hi G =10μA, SP= SN=open C = 4.5 G =10μA, SP=0; C=0 5.5 SN 80 4.5 7.0 9.5 G =-0μA, 10 R 14 5.0 8.0 9.5 G =-μa, 10 R 14 FT 0. 0.5 FT =1.5mA, C > 4.5 Fault Output High Source Current FT -1 μa FT =14, SP-SN > +6m Fault Delay time T FT-DLY 4 8 16 μs SP-SN = ± 50m step to 90% of GST max Note 1: These parameters are not production tested but are guaranteed by design, characterization, and correlation with statistical process control. Note : Current sourced by a pin is reported with a negative sign. Note 3: Refer to the C Bias section in the Application nformation for details on the C requirement to meet the MOSFET GS requirement. Picor Corporation picorpower.com P007 Rev 1.3 Page 4 of 19
Functional Description: The P007 Cool-ORing controller C is designed to drive single or parallel N-channel MOSFETs in high side Active ORing applications. The P007 used with an external MOSFET can function as an ideal ORing diode in the high side of a redundant power system, significantly reducing power dissipation and eliminating the need for heatsinking. An N-channel MOSFET in the conduction path offers extremely low on-resistance resulting in a dramatic reduction of power dissipation versus the performance of a diode used in conventional ORing applications due to its high forward voltage drop. This can allow for the elimination of complex heat sinking and other thermal management requirements. Due to the inherent characteristics of the MOSFET, current will flow in the forward and reverse directions while the gate remains above the gate threshold voltage. deal ORing applications should not allow reverse current flow, so the controller has to be capable of very fast and accurate detection of reverse current caused by input power source failures, and very fast turn off of the gate of the MOSFET. Once the gate voltage falls below the gate threshold, the MOSFET is off and the body diode will be reverse biased preventing reverse current flow and subsequent excessive voltage droop on the redundant bus. Differential Amplifier: The P007 integrates a high-speed low offset voltage differential amplifier to sense the difference between the Sense Positive (SP) pin voltage and Sense Negative (SN) pin voltage with high accuracy. The amplifier output is connected to the Reverse and Forward comparators. Reverse Current Comparator: RS The reverse current comparator provides the critical function in the controller, detecting negative voltage caused by reverse current. When the SN pin is 6m higher than the SP pin, the reverse comparator will force the gate discharge circuit to turn off the MOSFETs in typically 80ns. The reverse comparator will hold the gate low until the SP pin is 6m higher than the SN pin. The reverse comparator hysteresis is shown in Figure 3. There is a bias current path from SN to SP during the reverse fault condition. The bias current is proportional to the voltage between SN and SP. The maximum SN pin bias current is 9mA when SN =80 and SP =0 and assumes that the MOSFET is in the off condition. Refer to Figure 15 in the Application nformation section for more details. Forward oltage Comparator: FWD The FWD comparator detects when a forward voltage condition exists and SP is above 75m (typical) positive with respect to SN. When SP-SN is more than 75m, the FWD comparator will assert the Gate Status low to report a fault condition. C and nternal oltage Regulator: The P007 has a separate input C that provides power to the control circuitry, charge pump and gate driver. An internal regulator clamps the C voltage ( C-SGND ) to 11.7. The internal regulator circuit has a comparator to monitor the C voltage and pulls the GATE pin low when the C is lower than the C Under-oltage Threshold. n 1 Bus applications (10 to 14) the R input pin can be connected to the input voltage eliminating the need for an external limiter. An internal 40Ω resistor is connected between the R pin and the internal regulator C pin. Charge Pump: The P007 has an integrated charge pump that approximately doubles the C voltage with reference to the SGND pin, to drive the N-Channel MOSFET gate to a voltage higher than the input voltage at 15µA minimum source current. Gate Driver: The gate driver (GATE) output is configured to drive an external N-channel MOSFET. n the high state, the gate driver applies a 0µA typical current source to the MOSFET gate from the integrated charge pump. The Charge Pump voltage is limited to *( C SGND -1). When a reverse current fault is initiated, the gate driver pulls the GATE pin low to the PGND pin and discharges the MOSFET gate with 4A typical peak capability. Fault ndication: FT Figure 3: Reverse comparator hysteresis: SP - SN The FT pin is an open collector NPN that will be pulled low when the Gate pin is low. The FT pin is also pulled low when C-SGND is below ULO or during the following fault conditions as indicated in the table below: Picor Corporation picorpower.com P007 Rev 1.3 Page 5 of 19
Condition ndication of possible faults 1 Reverse: SP - SN -6m nput supply shorted Forward: SP - SN +75m Open FET, Gate short or open, High current 3 Forward SP - SN +6m Shorted FET on power-up Figure 4: P007 Controller nternal Block Diagram Figure 5: P007 State Diagram for gate drive. Picor Corporation picorpower.com P007 Rev 1.3 Page 6 of 19
Figure 6: Timing diagram for two P007 controllers in a high side Active ORing application Picor Corporation picorpower.com P007 Rev 1.3 Page 7 of 19
Typical Characteristics: Figure 7: Controller bias current vs. temperature Figure 10: C ULO threshold vs. temperature Figure 8: Reverse Fault to Gate Turn-off Response Time vs. temperature. Figure 11: Reverse comparator threshold vs. temperature. Figure 9: Gate drive voltage to C vs. temperature. Figure 1: Gate source current vs. temperature Picor Corporation picorpower.com P007 Rev 1.3 Page 8 of 19
Figure 13: P007 performance in response to a fault (input short), configured for a +48 application as shown in Figure 17. Application nformation: The P007 is designed to replace ORing diodes in high current redundant power architectures. Replacing a traditional diode with a P007 controller C and a low on-state resistance N-channel MOSFET will result in significant power dissipation reduction as well as board space reduction, efficiency improvement and additional protection features. This section describes in detail the procedure to follow when designing with the P007 Active ORing controller and N-Channel MOSFETs. Two different Active ORing design examples are presented. C Bias: The P007 has a separate input (C) that provides power to the control circuitry, the charge pump and the gate driver. An internal regulator clamps the C voltage ( C-SGND ) to 11.7. A bypass ceramic capacitor (C C = 1μF) has to be connected between C and SGND to hold C-SGND steady. Also, the Gate turn off return (PGND) should be connected to SGND at the C C termination to keep SGND noise free when the Gate is turned off in response to a fault. n 1 system applications, where the input voltage (in) is between 10 and 14, connect the R pin to in and connect SGND and PGND to the in return. A 40Ω internal resistor is connected between the R pin and the C pin. n high voltage applications, above 14, a bias resistor (R PG ) and low current low forward voltage drop Schottky diode are required. Connect one terminal of R PG to the SGND and PGND and the other terminal to ground (in return). The Schottky diode anode will be connected to the SGND pin and its cathode connected at the C pin. See typical application drawings on page 1. Recommended Schottky: PMEG3005AEA: from NXP or equivalent R PG selection for input voltage greater than 14: Picor Corporation picorpower.com P007 Rev 1.3 Page 9 of 19
Select the resistor (R PG ) value at the minimum input voltage to avoid a voltage drop that may reduce C- SGND lower than C under voltage lockout. Select the value of R PG using the following equations: R PG C min C _ Max CCLMMax 0.1mA R PG maximum power dissipation: PdR PG Where: ( Cmax CCLMMin) R PG : C pin minimum applied voltage with Cmin respect to in return : C pin maximum applied voltage with Cmax respect to in return : Controller maximum clamp voltage, 1.5 C CLMMax : Controller minimum clamp voltage, 11.0 C CLMMin _ : Controller maximum bias current, use C Max.0mA plus 0.1mA for margin Example: 40 < C <50 C min CCLMMax 40 1.5 RPG 13. 1k 0.1mA.1mA C _ Max ( C max C CLMMin) 50 11 PdRPG 116mW R 13.1k PG Alternative Bias Circuit with Device Enable: Constant current circuit n a wide operating input voltage range the size of R PG may be become large to support power dissipation. A simple constant current circuit can be used instead of R PG to reduce power dissipation and can be used as a device enable. As shown in Figure 14, the constant current circuit consists of an NPN transistor (Q), Zener diode D Z, current limit resistor (R LMT ) and Zener bias resistor (R Z ). R LMT and R Z can be very low power resistors and Q is a signal transistor where its Collector- Emitter oltage ( CEO ) is equal or greater than the input operating voltage and supports.5ma at the operating input voltage. Figure 14: Constant current bias circuit Pulling the Q base (EN) to the system return (RTN) will turn off the transistor and the controller returns (SGND pin and PGND pin) will float and eventually the MOSFET will be turned off. An open collector device can be used to enable and disable the P007. The constant current circuit should guarantee current greater than the P007 maximum Quiescent current ( C ),.0mA. R LMT can be calculated from the following equation: R LMT Z _ MN BE ( on) C _ MAX Where: : Minimum Zener diode voltage Z _ MN BE (on) : Q Base-Emitter On maximum voltage, for default use BE (on) =0.7 _ : P007 Quiescent Current, maximum C MAX C =.0mA Zener Diode Selection: Select a Zener diode with a low reverse current requirement to minimize R Z. Zener diodes with higher break down voltage will have lower reverse current and reduce Q collector current variation. Zener diodes with a breakdown voltage of 6 and higher will require low bias current and accurate voltage breakdown. R Z maximum value can be calculated with the following equation: Note that the surface mount resistors have limited operating voltage capability. Be sure to pick a resistor package that can meet the maximum operating voltage (in). Picor Corporation picorpower.com P007 Rev 1.3 Page 10 of 19
R Z in _ MN Z Z _ MAX B _ MAX Where: : Min input voltage in _ MN Z _ MAX Z : B _ MAX C _ MAX FE MN : Zener diode maximum breakdown voltage Zener diode required reverse current : Q required maximum base current which calculated from the following equation: C _ MAX B _ MAX h FE _ MN : Q maximum expected collector current. h _ : Q minimum gain. Fault ndication: FT is an open collector output and its return is referenced to SGND. When SGND is referenced to system ground, FT should be pulled up to the logic voltage via a resistor (10KΩ). When the SGND pin is floating on a bias resistor (R PG ) or in a constant current circuit, a level shift circuit can be added to make the FT pin output referenced to the system ground. See Figure 19. Leave FT unconnected if not used. Note that in case of an input fault condition, where the input voltage (in) and the C pin are at ground and the SN pin is at a high voltage, a parasitic path between SN and C will draw bias current (leakage current) from the output as a function of the voltage between SN and grounded C ( SN-GND ) based on the following equation: SN _ Lg Where: SN Lg SN GND R PAR 1 _ : SN leakage current during input short : oltage difference between SN pin (or load SN GND voltage) and ground. R PAR : Resistor in the parasitic path, 10KΩ typical and 8kΩ minimum Figure 15: SN leakage current vs. SN voltage during input fault condition (input short) N-Channel MOSFET Selection: Several factors affect MOSFET selection including cost, on-state resistance (R DS(on) ), DC current rating, short pulse current rating, avalanche rating, power dissipation, thermal conductivity, drain-to-source breakdown voltage (Bdss), gate-to-source voltage rating (gs), and gate threshold voltage (gs (TH) ). The first step is to select a suitable MOSFET based on the Bdss requirement for the application. The Bdss voltage rating should be higher than the applied in voltage plus expected transient voltages. Stray parasitic inductance in the circuit can also contribute to significant transient voltage conditions, particularly during MOSFET turn-off after a reverse current fault has been detected. n Active ORing applications when one of the input power sources is shorted, a large reverse current is sourced from the circuit output through the MOSFET. Depending on the output impedance of the system, the reverse current may get very high in some conditions before the MOSFET is turned off. Make sure that the MOSFET pulse current capability can withstand the peak current. Such high current conditions will store energy even in a small parasitic element. Note that P007 has a very fast response time to a fault condition achieving 80ns typical and 150ns maximum. This fast response time will minimize the reverse peak current to keep stored energy and MOSFET avalanche energy very low to avoid damage (breakdown) to the MOSFET. Peak current during input short is calculated as follows, assuming that the output has very low impedance and it is not a limiting factor: PEAK L S * t RS PARASTC Picor Corporation picorpower.com P007 Rev 1.3 Page 11 of 19
Where: PEAK : Peak current in the MOSFET right before it is turned off. S : nput voltage or load voltage at MOSFET source before input short condition did occur. t RS : Reverse fault to MOSFET turn-off time. This will include P007 delay and the MOSFET turn off time. L PARASTC : Circuit parasitic inductance And the MOSFET avalanche energy during an input short is calculated as follows: E AS Where: 1 * 1.3* *1.3 ( BR) DSS ( BR) DSS E AS : Avalanche energy BR ) DSS S * L PARASTC ( : MOSFET breakdown voltage * PEAK Trise MOSFET Rth JA Pd MOSFET Rth JA s R, DS ( on) Where: Rth : Junction-to-Ambient thermal resistance JA R DS(on) and P007 sensing: The P007 senses the MOSFET source-to-drain voltage drop via the SP and SN pins to determine the status of the current through the MOSFET. When the MOSFET is fully enhanced, its source-to-drain voltage is equal to the MOSFET on-state resistance multiplied by the source current, SD = R DS(on) *s. The reverse current threshold is set for -6m and when the differential voltage between the SP & SN pins is more negative than -6m, i.e. SP-SN-6m, the P007 detects a reverse current fault condition and pulls the MOSFET gate pin low, thus turning off the MOSFET and preventing further reverse current. The reverse current fault protection disconnects the power source fault condition from the redundant bus, and allows the system to keep running. MOSFET R DS(on) and maximum steady state power dissipation are closely related. Generally the lower the MOSFET R DS(on), the higher the current capability and the lower the resultant power dissipation. This leads to reduced thermal management overhead, but will ultimately be higher cost compared to higher R DS(on) parts. t is important to understand the primary design goal objectives for the application in order to effectively trade off the performance of one MOSFET versus another. Power dissipation in active ORing circuits is derived from the total source current and the on-state resistance of the selected MOSFET. MOSFET power dissipation: Pd s MOSFET R DS ( on) Where : s : Source Current R DS(on) : MOSFET on-state resistance Note: n the calculation use R DS(on) at maximum MOSFET temperature because R DS(on) is temperature dependent. Refer to the normalized R DS(on) curves in the MOSFET manufacturers datasheet. Some MOSFET R DS(on) values may increase by 50% at 15 C compared to values at 5 C. The Junction Temperature rise is a function of power dissipation and thermal resistance. Picor Corporation picorpower.com P007 Rev 1.3 Page 1 of 19
Typical application Example 1: Requirement: Redundant Bus oltage = 1 (±10%, 10.8 to 13.) Load Current = 15A (assume through each redundant path) Maximum Ambient Temperature = 75 C Solution: A single P007 with a suitable external MOSFET for each redundant 1 power source should be used, configured as shown in the circuit schematic in Figure 16. Select a suitable N-Channel MOSFET: Most industry standard MOSFETs have a gs rating of +/- 1 or higher. Select an N-Channel MOSFET with a low R DS(on) which is capable of supporting the full load current with some margin, so a MOSFET capable of at least 18A in steady state is reasonable. An exemplary MOSFET having these characteristic is the FDS616N7 from Fairchild. From FDS616N7 datasheet: N-Channel MOSFET DS = 0 D = 3A continuous drain current D (Pulse) = 60A Pulsed drain current GS(MAX)= 1 R θja = 40 C/W when mounted on a 1in PCB pad of oz copper R DS(on) =.9mΩ typical and 3.5mΩ maximum at D =3A, GS 4.5, T J =5 C T J max 40C 75C (15A) 4.48m 115C W Recalculate based on increased Junction temperature, 115 C. At 115 C R DS(on) will increase by 3%. R DS ( on ) 3.5m1.3 4. 6m T J max 40C 75C (15A) 4.6m 116. 5C W C Bias: in maximum input is 13., this is higher than the 11 C Clamp oltage ( C-SGND ) minimum. Use the high side P007 internal resistor between R pin and C pin will fit for this application. Since the MOSFET requires only 4.5 for full enhancement then the P007 internal resistor between R pin and C pin will fit for this application. Connect R to in at the source of the MOSFET and connect a 1μF ceramic capacitor between C pin and SGND pin. Fault ndication: Connect FT pin to the logic input and to the logic power supply via a 10KΩ resistor. Reverse current threshold is: th. reverse 6m s. reverse. 07A Rds( on).9m Power dissipation: R DS(on) is 3.5mΩ maximum at 5 C & 4.5gs and will increase as the temperature increases. Add 5 C to maximum ambient temperature to compensate for the temperature rise due to power dissipation. At 100 C (75 C + 5 C) R DS(on) will increase by 8%. R ( on ) 3.5m1.8 4. m maximum at 100 C DS 48 Trise Rth s JA R DS ( on) Maximum Junction temperature T J max T Trise A Figure 16: P007 in 1 bus high side Active ORing configuration Picor Corporation picorpower.com P007 Rev 1.3 Page 13 of 19
Typical application Example : Requirement: +48 High Side Redundant Bus oltage = +48 (+36 to +60, 100 for 100ms transient) Load Current = 5A load (assume through each redundant path) Maximum Ambient Temperature = 60 C Solution: A single P007 with a suitable MOSFET for each redundant +48 power source should be used and configured as shown in Figure 17 or Figure 18. Figure 17 is configured with the C biased from the return line through a bias resistor. Figure 18 is configured with the C biased from the return line through the constant current circuit. Select a suitable N-Channel MOSFET: Select the N-Channel MOSFET with voltage rating higher than the input voltage, in, plus any expected transient voltages, with a low R DS(on) that is capable of supporting the full load current with margin. For instance, a 100 rated MOSFET with 10A current capability is suitable. An exemplary MOSFET having these characteristic is RF7853PbF from nternational Rectifier. From the RF7853PbF datasheet: N-Channel MOSFET DS = 100 D = 8.3A maximum continuous drain current at 5 C D-PULSE = 66A pulsed drain current GS(MAX) = 0 R θja = 50 C/W on 1in copper, t 10seconds R θja for continuous operation not provided R DS(on) =14.4mΩ typical at GS =10, T J =5 C R DS(on) =18mΩ maximum at GS =10, T J =5 C Reverse current threshold is: th. reverse 6m s. reverse R 18m DS ( on) 333mA Power dissipation: Rds(on) is 18mΩ maximum at 5 C & 10gs and will increase as the temperature increases. Add 0 C to maximum ambient temperature to compensate for the temperature rise due to power dissipation. At 80 C (60 C + 0 C) Rds(on) will increase by 40%. R DS ( on ) 18m1.40 5. m maximum at 80 C Maximum Junction temperature T J max 50C 60C (5.0A) 5.m 91. 5C W Recalculate maximum R DS(on) at 95 C. At 95 C Rds(on) will increase by 50%: R ( on ) 18m1.50 m maximum at 95 C DS 7 Maximum Junction temperature after 10s T J max 50C 60C (5.0A) 7m 93. 75C W For continuous operation refer the MOSFET datasheet for R θja under continuous operation and plug it in place of 50 C/W. C Bias: Since the bus voltage is higher than 14, connect C pin to the high side of the input voltage and connect a bias resistor (R PG ) or a constant current circuit between P007 SGND pin and ground (in return), as shown in Figure 17 and Figure 18. Place a low forward voltage drop Schottky diode and a 1μF ceramic capacitor between SGND pin and C pin. Also connect PGND pin to SGND at the coupling capacitor terminal. Recommended Schottky: PMEG3005AEA from NXP or equivalent R PG selection: Cmin C R 0.1mA 36 1.5 11..0mA 0.1mA CLMMax PG 19 C _ Max Select R PG =11kΩ 1% k R PG maximum power dissipation: ( Cmax CCLMMin ) 60 11 PdR PG 18mW RPG 11k Use ¼ W Resistor in 106 package Figure 17: P007 in high side +48 application, C is biased through a bias resistor Picor Corporation picorpower.com P007 Rev 1.3 Page 14 of 19
C bias through Constant current circuit Select an NPN transistor with CEO equal or higher than the input voltage (in) plus any expected transient voltage and capable of handling the expected maximum power dissipation. Any NPN transistor with CEO 100 in a small footprint is suitable. An exemplary NPN is FJ1845 from Fairchild: Pd Q.9mA[60 11 (9.8 0.7 )] 91. 37mW The transistor Power De-rating vs. temperature curve in the manufacturer datasheet shows that the device can operate up to 110 C. From the FJ1845 datasheet: NPN Silicon Transistor CEO = 10 Collector-Emitter maximum voltage C = 50mA maximum collector current h FE = 150 minimum at C =3mA BE(sat) = 0.55 to 0.65 Base-Emitter saturation voltage at 5 C Select Zener Diode: Select the Zener diode with low bias current, a Zener diode with Z =10 in small foot print is suitable for this application. An exemplary Zener diode MM3Z10ST1 from ON Semiconductor From the MM3Z10ST1 datasheet: 10, 00mW Zener Diode Z = 9.80 to 10. Zener voltage range R = 10μA will hold the Zener breakdown voltage at 9.8 Z _ MN BE ( on) 9.8 0.7 RLMT 4. 33k.1mA Or 4.3kΩ 1% B _ MAX h C _ MAX C _ MAX FE _ MN 3.5mA 3.33A 150 R Z Calculation: Use 100μA as minimum for the Zener diode reverse leakage current and Q base current combined. in _ MN Z _ MAX 36 10. RZ 58k 100A Z B _ MAX Figure 18: P007 in high side +48 application, C is biased through constant current circuit. Fault ndication: P007 SGND pin in this application is floating and FT is referenced to SGND. The FT output can be referenced to system return (RTN) by adding a level shift circuit as shown in Figure 19. Q1: SA1579T106R, 10 PNP transistor from Rohm. Q: DTC114EET1G, 50 NPN with bias resistors from ON semiconductor. D1: 30 general purpose diode. Select R Z = 49kΩ 1% Maximum Q collector current: Z _ MAX BE _ MN 10. 0.50 C _ MAX. 9mA R 4.3k *0.98 LMT _ MN Maximum Q power dissipation Pd [ in MAX CCLM ( Z _ MN EB _ Q C _ MAX MAX )] Figure 19: FT level shift circuitry Picor Corporation picorpower.com P007 Rev 1.3 Page 15 of 19
High and Low Side Active ORing for the Same Source: P007 and Picor P003 controllers can be configured to meet ATCA application that requires low and high side ORing as shown in Figure 0. See PCOR Application Notes for more details of the design procedure for this application. Figure 0: P007 and P003 configured for a combined high and low side ORing application Picor Corporation picorpower.com P007 Rev 1.3 Page 16 of 19
Layout Recommendation: Use the following general guidelines when designing printed circuit boards. An example of the typical land pattern for a DFN P007 and SO-8/PowerPak MOSFET is shown in Figure 1 and Figure : t is best to connect the gate of the MOSFET to the GATE pin of the controller with a short trace. A gate resistor (R G ) is added to slow down the gate turn off if needed. The C bypass capacitor should be located as close as possible to the C and SGND pins. Place the P007 and C bypass capacitor on the same layer of the board. The C pin and C C PCB trace should not contain any vias. n an application where SGND is floating, a low forward voltage drop Schottky diode has to be added in parallel with C C to protect the controller during an input voltage short fault. PGND pin of the controller carries high peak current during gate pull down, Connect PGND pin with a wide trace to the C C terminal at SGND. Make sure that SGND trace and PGND trace connect only at C C terminal. Connections from the SP and SN pins to the MOSFET source and drain pins respectively should be as short as possible Connect all MOSFET source pins together with a wide trace to reduce trace parasitics and to accommodate the high current input. Similarly, connect all MOSFET Drain pins together with a wide trace to accommodate the high current output. Figure 1: P007 controller and MOSFET layout recommendation in a floating application. Figure : P007 controller and MOSFET layout recommendation in a non-floating application Picor Corporation picorpower.com P007 Rev 1.3 Page 17 of 19
Package Drawing: 10 Lead DFN Thermal Resistance Ratings Parameter Symbol Typical Unit Maximum Junction-to-Ambient (4) θ JA 53 C/W Note 4: n accordance with JEDEC JESD 51 Ordering nformation Part Number Package Transport Media P007-00-QEG 3mm x 3mm 10 Lead DFN T&R Picor Corporation picorpower.com P007 Rev 1.3 Page 18 of 19
Warranty icor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. icor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGONG EXPRESS WARRANTY, COR MAKES NO WARRANTY, EXPRESS OR LMTED, NCLUDNG, BUT NOT LMTED TO, THE WARRANTY OF MERCHANTABLTY OR FTNESS FOR A PARTCULAR PURPOSE. icor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact icor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. icor will pay all reshipment charges if the product was defective within the terms of this warranty. nformation published by icor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. icor reserves the right to make changes to any products without further notice to improve reliability, function, or design. icor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. icor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per icor Terms and Conditions of Sale, the user of icor components in life support applications assumes all risks of such use and indemnifies icor against all damages. icor s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. nformation furnished by icor is believed to be accurate and reliable. However, no responsibility is assumed by icor for its use. icor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to icor s Terms and Conditions of Sale, which are available upon request. Specifications are subject to change without notice. icor Corporation Picor Corporation 5 Frontage Road 51 ndustrial Drive Andover, MA 01810 North Smithfield, R 0896 USA USA Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com Tel: 800-735-600 Fax: 978-475-6715 Picor Corporation picorpower.com P007 Rev 1.3 Page 19 of 19