UNIT III ANALOG MULTIPLIER AND PLL

UNIT III ANALOG MULTIPLIER AND PLL PART A (2 MARKS) 1. What are the advantages of variable transconductance technique? [AUC MAY 2012] Good Accuracy Economical Simple to integrate Reduced error Higher bandwidth 2. VCO is also called as V-f converter. Why? [AUC MAY 2012] VCO converts the applied input voltage to an output frequency. Hence VCO are also called as V-F converter. 3. How is VCO different from oscillators? [AUC MAY 2011] An oscillator is circuit that generates the frequency output of fixed frequency. A voltage controlled oscillator is an circuit in which the frequency of oscillations can be controlled by an external applied voltage. 4. Define lock in and capture range in PLL. [AUC MAY 2011] Lock IN range : The range of frequencies over which the PLL can maintain lock with the incoming signal is called the lock in range. Capture range : The range of frequencies over which the PLL can acquire lock with the incoming signal is called the lock in range. 5. Name two applications of PLL. [AUC April 2004,2010] AM detection FM detection 6. What is a voltage controlled oscillator[auc April2004,2010] This oscillator converts the applied input voltage to an output frequency. 7. What is a two quadrant multiplier. [AUC NOV 2004] Two quadrant multiplier is one in which one input must be held positive and other is allowed to swing between positive and negative. 8. With reference to a VCO, define voltage to frequency conversion factor kv. [AUC MAY 2004] The voltage to frequency conversion is denoted as Kv and defined as Kv=Δf0 / ΔVc ΔVc is the change in control voltage producing corresponding change of Δf0 in the frequency. 9. Define : Lock range [AUC MAY 2005,2009,Nov 2013] The range of frequencies over which the PLL can maintain lock with the incoming signal is called the lock in range. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 1

10. What is a PLL[[AUC Nov 2006] A phase locked loop is basically a closed loop system designed to lock the output frequency and phase to the frequency and phase of the input signal. 11. Define capture range of PLL?[ AUC May 2006] The range of frequencies over which the PLL can acquire lock with the incoming signal is called the lock in range. 12. What is a compander IC? Enlist the features[auc Nov 2006] The IC in which both compression and expansion takes place is called a compander IC. the compression is done in the transmitter and expansion is done in the receiver. Features: Adjustable response time. In build mute circuit for compressor and expander Low opertating voltage 13. Define amplitude modulation. The amplitude of a high frequency carrier signal is varied in accordance with the message signal and this process is called amplitude modulation. 14. Write the significance of lock range of PLL?[ AUC Nov 2007] For maintaining the lock the phase error between the VCO output and incoming signal must be maintained between 0 and П. The lock range is always symmetrically located with respect to the center frequency of the VCO 15. Draw the block diagram of NE566 VCO?[ AUC Nov2007] 16. What is an operational transconductance amplifier? [AUC Nov 2007] An operational transconductance amplifier is a voltage input and current output amplifier. 17. What is frequency synthesizer?[ AUC April 2008,Nov 2013] Frequency synthesizer is one which produce an output signal and the frequency of the output signal can be precisely adjusted to any value in a prescribed range. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 2

18. Draw the circuit of AM detector using PLL.[ AUC April 2008] 19. List the applications of PLL.[ AUC Nov 2008,2009] Frequency multiplication Frequency division AM detection FM detection 20. what is pull-in time?.[ AUC May 2010] The total time taken by the PLL to establish lock is called pull-in time. This depends on the initial phase and frequency difference between the two signals as well as on the overall loop gain and loop filter characteristics. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 3

PART B ( 16 Marks) 1. Explain the purpose and functioning of i) Variable transconductance multiplier ii)frequency synthesizer.[ AUC April 2004,2008] i) Variable transconductance multipliers +VCC RL 1k I1 V0 I2 RL 1k + Q1 Q2 VX Q2N4141 Q2N4141 - + VY IEE Q3 Q2N4141 RE 1k - 0 If the differential input voltage Vx is smaller than the differential output voltage Vo then Vo can be related to the input voltage as Vo = gm rl vx gm trans conductance gm = iee /vt vt thermal equivalent voltage if we apply the second input voltage Vy then the trans conductance gm will vary Applying KVL to the input circuit of Q3 we get Vy = Vbe3 + Iee Re Neglecting Vbe3 we get ( Iee re >> Vbe3) Vy = Iee Re EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 4

Over all transfer expression can be written as Vo = gm Rl. Vx Vo =Iee / Vt * Rl * Vx = Vy / Re. Vt * Rl * Vx Vo= ( Rl / Re.Vt) * Vx Vy Vo = K Vx V y Where k=( Rl / Re.Vt) is the scaling factor Output voltage Vo is proportional to the multiplication of Vx and V y. ii) Frequency synthesizer Operation : The frequency synthesizer is to produce an output signal of which the frequency can be precisely adjusted to any value in a prescribed range. The output frequencies of a synthesizer should be stable. In order to ensure stability of output frequency, a crystal oscillator of frequency fosc is used. The output frequency of crystal oscillator is divided by M with the help of the divide by M network. Thus the input frequency to PLL is fosc/m. The PLL will compare this frequency with the frequency at the output of divide by N network and will try to adjust this frequency equal to fosc / M. In order to obtain the same frequency (fosc/m) at the output of divide by N network,the VCO frequency should be adjusted to, fvco = (fosc /M) * N The equation indicates that by adjusting the ratio (N/M) we can obtain a large number of frequencies. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 5

7 4 V+ V- 7 4 V+ V- 2. Explain the working of a i)vco ii) AM demodulation using PLL[AUC April 2004] Voltage controlled oscillator Circuit whose frequency is determined by the input voltage is called voltage controlled oscillator. Circuit diagram D D1N4001 R3<<R 1k C3 1n R9 1k VIN R 1k AD741 2 - OS1 OUT 3 + OS2 U4 1 6 5 R1 1k AD741 2 - OS1 OUT 3 + OS2 U5 1 6 5 VO 0 0 Operation Voltage controlled oscillator is the combination of an inverting integrator and regenerative comparator. Output voltage from VCO is a rectangular waveform with peak values + / - Vsat. Assume that initially vo= + Vsat. Due to + Vsat diode d1 gets reverse biased.hence,capacitor c begins to charge. When Vc= Vlt of Schmitt trigger, Schmitt changes its state from +vsat to vsat. Hence capacitor begins to discharge through diode. Discharging takes place until Vc= Vut This process is cyclic and charging and discharging of capacitor depends on the value of R and level of Vin. Discharging is much faster than charging of capacitor. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 6

Waveform Closed loop analysis of PLL AM detector AM INPUT PLL MULTIPLIER( PHASE DETECTOR) LPF DEMODULATED OUTPUT PHASE VCO OUTPUT SHIFT 90º EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 7

PLL is locked to the carrier frequency of the incoming AM signal. Once locked the output frequency of VCO is same as the carrier frequency but it is in un modulated form. The modulated signal with 90ºphase shift and the un modulated carrier from output of PLL are fed to multiplier. Since VCO output is always 90º out of phase with the incoming AM signal under locked condition both signals applied to multiplier are in same phase. The low pass filter connected to the output of the multiplier rejects high frequency components which gives demodulated output. 3. With a neat circuit diagram,explain how 565 PLL can be used as a FSK demodulator[auc Nov 2004,2007,2008,Nov09,Nov 2013] FSK Detector Transmission technique which uses two different carrier frequency for logic 1 and logic 0 states of binary signal for data transmission is called frequency shift keying. Let us consider two frequencies f1 represented as 0 and f2 represented as 1. If the PLL is locked with the FSK signal at both f1 and f2 then VCO control voltage which is also supplied to the comparator will be given as Vc1=(f1-f0) / Kv Vc2= (f2 f0) / Kv K v- voltage to frequency transfer coefficient of VCO. The difference between two control voltage levels will be ΔVc = ( f2 f1 ) / Kv EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 8

4. a)explain the working of a four quadrant Gilbert multiplier.[ AUC May 2010,Nov 2013] Analysis of four quadrant Gilbert cell It consist of emitter coupled pair of transistors Q1 and Q2 in series with a cross coupled emitter coupled transistor pair Q3 to Q6. A constant source Iee is connected in the emitter circuit of Q1 and Q2 to bias them. Vx and Vy are two differential inputs which are to be multiplied together. Due to symmetry in the cross coupled devices Iee gets equally divided among various branches of the circuit and eliminates any common mode shift in the output voltage Vo. Analysis : Assume all transistors are of same type I1 = I3 + I4 I2= I5 +I6 Iee=I1+I2 Let gm(3,4) and gm(5,6) are variable Trans conductance of transistor pairs Q3,Q4 and Q5 and Q6 respectively. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 9

Where transconductance gm is given by Iee / Vt Vt- thermal equivalent voltage Current unbalance in the differential pairs of Q3 Q4 and Q5 Q6 are given by I3-I4 = gm(3 4) Vx I5-I6 = gm(5 6) Vx The differential output voltage is given by Vo= ( I3 I4) Rl - ( I5 I6) Rl Vo= Rl[ (I3-I4) (I5 I6)] Substituting values of I3 I4 and I5 - I6 we get Vo=Rl [gm(3 4) Vx - gm(5 6) Vx] But gm(3 4) = I1 / Vt and gm(5 6) = I2/ Vt Vo= Rl[I1 / Vt * Vx - I2/ Vt * Vx] Vo= Rl Vx / Vt[I1 I2] Re is very large I1 Re >> Vt and I2 Re >> Vt I1 I2 = Vy / Re V0 = Rl Vx Vy / Vt Re Let K= Rl / Re Vt where k is a constant Vo= k Vx Vy Output is directly proportional to the product of two inputs Vx and Vy Limitations : Gilbert cell works well when Vx < Vy EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 10

5. Write notes on any one compander IC.[ AUC May 2005,Nov 2006] The process of companding is the combination of 1. Compression 2. Expansion IC SL5020/P PIN NO DESCRIPTION 1 Vref which is produced by a band gap reference. At this pin,we get stable 1.3 V stable voltage as the reference for the internal circuits. 2 & 13 Expander and Compander mute adjust. 3 Expander filter pin. An external filter capacitor is connected to this pin to filter its full wave rectifier output voltage. 4 Output of Expander amplifier 5 Expander input. A coupling capacitor should be connected between the input source and pin No.5 6 Vb hich is an internal reference 7 Ground 8 Compressor feedback which is the input to the compressor variable gain stage for automatic gain adjustment. 9 Compressor CF. it is connected to the compressor output through filtered DC feedback path. 10 Compressor input. A coupling capacitor should be between the input source and this pin. 11 Output of compressor amplifier. 12 Compressor filter. An external filter capacitor needs to be connected at this pin 13 Compressor mute adjust 14 Vcc. The power supply to this IC is 1.8V to 5 V EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 11

6. Explain working of PLL using appropriate block diagram and explain any one application of the same.[ AUC May 2005,Nov 2006,May 2010,Nov 2013] Phase locked loop construction and operation: The PLL consists of i) Phase detector ii) LPF iii) VCO. (a) Phase Detector: Phase detector compares the input frequency and VCO frequency and generates DC voltage i.e., proportional to the phase difference between the two frequencies. (b) Low Pass filter: The function of the LPF is to remove the high frequency components in the output of the phase detector and to remove the high frequency noise. (c) Voltage Controlled Oscillator (VCO): The third section of PLL is the VCO; it generates an output frequency that is directly proportional to its input voltage. The maximum output frequency of NE/SE 566 is 500 Khz. Operation : The phase detector is basically a multiplier and produces the sum (fs + fo) and difference (fs - fo) components at its output. The high frequency component (fs + fo) is removed by the low pass filter and the difference frequency component is amplified then applied as control voltage vc to VCO. The signal vc shifts the VCO frequency in a direction to reduce the frequency difference between fs and fo. Once this action starts, we say that the signal is in the capture range. The VCO continues to change frequency till its output frequency is exactly the same as the input signal frequency. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 12

The circuit is then said to be locked. Once locked, the output frequency fo of VCO is identical to fs except for a finite phase difference φ. This phase difference φ generates a corrective control voltage vc to shift the VCO frequency from f0 to fs and thereby maintain the lock. Once locked,pll tracks the frequency changes of the input signal. Thus, a PLL goes through three stages (i)free running, (ii) capture and (iii) locked or tracking. Capture range: the range of frequencies over which the PLL can acquire lock with an input signal is called the capture range. This parameter is also expressed as percentage of fo. Pull-in time: the total time taken by the PLL to establish lock is called pull-in time. This depends on the initial phase and frequency difference between the two signals as well as on the overall loop gain and loop filter characteristics. Closed loop analysis of PLL AM detector AM INPUT PLL MULTIPLIER( PHASE DETECTOR) LPF DEMODULATED OUTPUT PHASE VCO OUTPUT SHIFT 90º PLL is locked to the carrier frequency of the incoming AM signal. Once locked the output frequency of VCO is same as the carrier frequency but it is in un modulated form. The modulated signal with 90ºphase shift and the un modulated carrier from output of PLL are fed to multiplier. Since VCO output is always 90º out of phase with the incoming AM signal under locked condition both signals applied to multiplier are in same phase. The low pass filter connected to the output of the multiplier rejects high frequency components which gives demodulated output. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 13

7. Explain the operation of four quadrant multiplier.[ AUC Nov 2006] Analysis of four quadrant Gilbert cell It consist of emitter coupled pair of transistors Q1 and Q2 in series with a cross coupled emitter coupled transistor pair Q3 to Q6. A constant source Iee is connected in the emitter circuit of Q1 and Q2 to bias them. Vx and Vy are two differential inputs which are to be multiplied together. Due to symmetry in the cross coupled devices Iee gets equally divided among various branches of the circuit and eliminates any common mode shift in the output voltage Vo. Analysis : Assume all transistors are of same type I1 = I3 + I4 I2= I5 +I6 Iee=I1+I2 Let gm(3,4) and gm(5,6) are variable Trans conductance of transistor pairs Q3,Q4 and Q5 and Q6 respectively. Where transconductance gm is given by Iee / Vt Vt- thermal equivalent voltage EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 14

Current unbalance in the differential pairs of Q3 Q4 and Q5 Q6 are given by I3-I4 = gm(3 4) Vx I5-I6 = gm(5 6) Vx The differential output voltage is given by Vo= ( I3 I4) Rl - ( I5 I6) Rl Vo= Rl[ (I3-I4) (I5 I6)] Substituting values of I3 I4 and I5 - I6 we get Vo=Rl [gm(3 4) Vx - gm(5 6) Vx] But gm(3 4) = I1 / Vt and gm(5 6) = I2/ Vt Vo= Rl[I1 / Vt * Vx - I2/ Vt * Vx] Vo= Rl Vx / Vt[I1 I2] Re is very large I1 Re >> Vt and I2 Re >> Vt I1 I2 = Vy / Re V0 = Rl Vx Vy / Vt Re Let K= Rl / Re Vt where k is a constant Vo= k Vx Vy Output is directly proportional to the product of two inputs Vx and Vy Limitations : Gilbert cell works well when Vx < Vy EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 15

8. With circuit diagram explain the working of a NE 566 VCO. [AUC Nov 2006] A common type of VCO available in IC form is NE/SE566. The pin configuration and basic block diagram of 566 VCO are shown in figures below. The capacitor c1 is linearly charged or discharged by a constant current source/sink. The amount of current can be controlled by changing the voltage vc applied at the modulating input (pin 5) or by changing the timing resistor R1 external to the IC chip. The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the modulating voltage at pin 5 is increased, the voltage at pin 6 also increases, resulting in less voltage across R1 and thereby decreasing the charging current. The voltage across the capacitor C1 is applied to the inverting input terminal of Schmitt trigger via buffer amplifier. The output voltage swing of the Schmitt trigger is designed to Vcc and 0.5 Vcc. If Ra = Rb in the positive feedback loop, the voltage at the non-inverting input terminal of Schmitt trigger swings from 0.5 Vcc to 0.25 Vcc. When the voltage on the capacitor c1 exceeds 0.5 Vcc during charging, the output of the Schmitt trigger goes LOW (0.5 Vcc). The capacitor now discharges and when it is at 0.25 Vcc, the output of Schmitt trigger goes HIGH (Vcc). Since the source and sink currents are equal, capacitor charges and discharges for the same amount of time. This gives a triangular voltage waveform across c1 which is also available at pin 4. The square wave output of the Schmitt trigger is inverted by buffer amplifier at pin 3. The output waveforms are shown near the pins 4 and 3. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 16

The output frequency of the VCO can be given as follows: where V+ is Vcc. The output frequency of the VCO can be changed either by (i) R1, (ii) c1 or (iii) the voltage vc at the modulating input terminal pin 5. The voltage vc can be varied by connecting a R1R2 circuit as shown in the figure below. The components R1and c1 are first selected so that VCO output frequency lies in the centre of the operating frequency range. Now the modulating input voltage is usually varied from 0.75 Vcc to Vcc which can produce a frequency variation of about 10 to 1. 9. Explain the operation of phase locked loop as a frequency synthesizer.[ AUC Nov 2006,2007] Frequency synthesizer Operation : The frequency synthesizer is to produce an output signal of which the frequency can be precisely adjusted to any value in a prescribed range. The output frequencies of a synthesizer should be stable. In order to ensure stability of output frequency, a crystal oscillator of frequency fosc is used. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 17

The output frequency of crystal oscillator is divided by M with the help of the divide by M network. Thus the input frequency to PLL is fosc/m. The PLL will compare this frequency with the frequency at the output of divide by N network and will try to adjust this frequency equal to fosc / M. In order to obtain the same frequency (fosc/m) at the output of divide by N network,the VCO frequency should be adjusted to, fvco = (fosc /M) * N The equation indicates that by adjusting the ratio (N/M) we can obtain a large number of frequencies. 10. Perform the closed loop analysis of PLL using appropriate diagram and explain any one application of the same. [AUC MAY 2011] Phase locked loops can also be analyzed as control systems by applying the Laplace transform. The loop response can be written as: Where The loop characteristics can be controlled by inserting different types of loop filters. The simplest filter is a one-pole RC circuit. The loop transfer function in this case is: EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 18

The loop response becomes: This is the form of a classic harmonic oscillator. The denominator can be related to that of a second order system: Where For the one-pole RC filter, The loop natural frequency is a measure of the response time of the loop, and the damping factor is a measure of the overshoot and ringing. Ideally, the natural frequency should be high and the damping factor should be near 0.707 (critical damping). With a single pole filter, it is not possible to control the loop frequency and damping factor independently. For the case of critical damping, A slightly more effective filter, the lag-lead filter includes one pole and one zero. This can be realized with two resistors and one capacitor. The transfer function for this filter is EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 19

This filter has two time constants τ1 = C(R1 + R2) τ2 = CR2 Substituting above yields the following natural frequency and damping factor The loop filter components can be calculated independently for a given natural frequency and damping factor Real world loop filter design can be much more complex eg using higher order filters to reduce various types or source of phase noise. Applications of PLL: The PLL principle has been used in applications such as FM stereo decoders, motor speed control, tracking filters, FM modulation and demodulation, FSK modulation, Frequency multiplier, Frequency synthesis etc., 11. Explain the application of PLL for AM and FM detection [AUC MAY 2011] AM Detector AM INPUT PLL MULTIPLIER( PHASE DETECTOR) LPF DEMODULATED OUTPUT PHASE VCO OUTPUT SHIFT 90º PLL is locked to the carrier frequency of the incoming AM signal. Once locked the output frequency of VCO is same as the carrier frequency but it is in un modulated form. The modulated signal with 90ºphase shift and the un modulated carrier from output of PLL are fed to multiplier. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 20

Since VCO output is always 90º out of phase with the incoming AM signal under locked condition both signals applied to multiplier are in same phase. The low pass filter connected to the output of the multiplier rejects high frequency components which gives demodulated output. FM Detection : The FM signal which is to be demodulated is applied at the input of the PLL. As PLL is locked to the FM signal, the VCO starts tracking the instantaneous frequency in the FM input signal. The error voltage produced at the output of the amplifier is proportional to the deviation of input frequency from the centre frequency FM. Thus the error amplifier we get demodulated FM output. 12. Explain the operation of gilbert multiplier with neat sketches. [AUC MAY 2011] Analysis of four quadrant Gilbert cell EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 21

It consist of emitter coupled pair of transistors Q1 and Q2 in series with a cross coupled emitter coupled transistor pair Q3 to Q6. A constant source Iee is connected in the emitter circuit of Q1 and Q2 to bias them. Vx and Vy are two differential inputs which are to be multiplied together. Due to symmetry in the cross coupled devices Iee gets equally divided among various branches of the circuit and eliminates any common mode shift in the output voltage Vo. Analysis : Assume all transistors are of same type I1 = I3 + I4 I2= I5 +I6 Iee=I1+I2 Let gm(3,4) and gm(5,6) are variable Trans conductance of transistor pairs Q3,Q4 and Q5 and Q6 respectively. Where transconductance gm is given by Iee / Vt Vt- thermal equivalent voltage Current unbalance in the differential pairs of Q3 Q4 and Q5 Q6 are given by I3-I4 = gm(3 4) Vx I5-I6 = gm(5 6) Vx The differential output voltage is given by Vo= ( I3 I4) Rl - ( I5 I6) Rl Vo= Rl[ (I3-I4) (I5 I6)] Substituting values of I3 I4 and I5 - I6 we get Vo=Rl [gm(3 4) Vx - gm(5 6) Vx] But gm(3 4) = I1 / Vt and gm(5 6) = I2/ Vt EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 22

Vo= Rl[I1 / Vt * Vx - I2/ Vt * Vx] Vo= Rl Vx / Vt[I1 I2] Re is very large I1 Re >> Vt and I2 Re >> Vt I1 I2 = Vy / Re V0 = Rl Vx Vy / Vt Re Let K= Rl / Re Vt where k is a constant Vo= k Vx Vy Output is directly proportional to the product of two inputs Vx and Vy Limitations : Gilbert cell works well when Vx < Vy 13. What is phase locked loop? Explain its operation with diagrams [AUC MAY 2011] Phase locked loop construction and operation: The PLL consists of i) Phase detector ii) LPF iii) VCO. (a) Phase Detector: Phase detector compares the input frequency and VCO frequency and generates DC voltage i.e., proportional to the phase difference between the two frequencies. (b) Low Pass filter: The function of the LPF is to remove the high frequency components in the output of the phase detector and to remove the high frequency noise. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 23

(c) Voltage Controlled Oscillator (VCO): The third section of PLL is the VCO; it generates an output frequency that is directly proportional to its input voltage. The maximum output frequency of NE/SE 566 is 500 Khz. Operation : The phase detector is basically a multiplier and produces the sum (fs + fo) and difference (fs - fo) components at its output. The high frequency component (fs + fo) is removed by the low pass filter and the difference frequency component is amplified then applied as control voltage vc to VCO. The signal vc shifts the VCO frequency in a direction to reduce the frequency difference between fs and fo. Once this action starts, we say that the signal is in the capture range. The VCO continues to change frequency till its output frequency is exactly the same as the input signal frequency. The circuit is then said to be locked. Once locked, the output frequency fo of VCO is identical to fs except for a finite phase difference φ. This phase difference φ generates a corrective control voltage vc to shift the VCO frequency from f0 to fs and thereby maintain the lock. Once locked,pll tracks the frequency changes of the input signal. Thus, a PLL goes through three stages (i)free running, (ii) capture and (iii) locked or tracking. Capture range: the range of frequencies over which the PLL can acquire lock with an input signal is called the capture range. This parameter is also expressed as percentage of fo. Pull-in time: the total time taken by the PLL to establish lock is called pull-in time. This depends on the initial phase and frequency difference between the two signals as well as on the overall loop gain and loop filter characteristics. 14. List and define the various performance parameters of a Multiplier IC. (6) (ii) How the multiplier is used as voltage divider? (5) (iii) How the multiplier is used as frequency doubler? (5) [AUC MAY 2012] Accuracy: This specifies the derivation of the actual output from the ideal output, for any combination of X and Y inputs falling within the permissible operating range of the multiplier. Linearity: This defines the accuracy of the multiplier. The figure shows the response of the output as a function of one input voltage Vx when the other Vy is assumed constant. It represents the maximum percentage derivation from the ideal straight line output. An error surface is formed by plotting the output for different combinations of X and Y inputs. The Linearity Error can be defined as the maximum absolute derivation of the error surface. This linearity error imposes a lower limit on the multiplier accuracy. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 24

Bandwidth: The Bandwidth indicates the operating capability of an analog multiplier at higher frequency values. Small signal 3 db bandwidth defines the frequency f0 at which the output reduces by 3dB from its low frequency value for a constant input voltage. This is identified individually for the X and Y input channels normally. The transconductance bandwidth represents the frequency at which the transconductance of the multiplier drops by 3dB of its low frequency value. This characteristics defines the application frequency ranges when used for phase detection or AM detection. Voltage Divider The circuit in which output is the division of the two input signals is called as a voltage divider. The multiplier is used in the feedback loop. As node A is grounded, node B is also grounded Frequency Doubler EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 25

Consider the two input signals The first term is DC for a phase difference of but at twice the frequency of the inputs. while the second term varies with time 15. Explain, with neat block diagrams, how PLL is used as (i) AM Detector. (5) (ii) FM Detector. (5) (iii) Frequency Synthesizer. (6) [AUC MAY 2012,Nov 2013] AM Detector AM INPUT PLL MULTIPLIER( PHASE DETECTOR) LPF DEMODULATED OUTPUT PHASE VCO OUTPUT SHIFT 90º PLL is locked to the carrier frequency of the incoming AM signal. Once locked the output frequency of VCO is same as the carrier frequency but it is in un modulated form. The modulated signal with 90ºphase shift and the un modulated carrier from output of PLL are fed to multiplier. Since VCO output is always 90º out of phase with the incoming AM signal under locked condition both signals applied to multiplier are in same phase. The low pass filter connected to the output of the multiplier rejects high frequency components which gives demodulated output. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 26

FM Detection : The FM signal which is to be demodulated is applied at the input of the PLL. As PLL is locked to the FM signal, the VCO starts tracking the instantaneous frequency in the FM input signal. The error voltage produced at the output of the amplifier is proportional to the deviation of input frequency from the centre frequency FM. Thus the error amplifier we get demodulated FM output. Frequency synthesizer Operation : The frequency synthesizer is to produce an output signal of which the frequency can be precisely adjusted to any value in a prescribed range. The output frequencies of a synthesizer should be stable. In order to ensure stability of output frequency, a crystal oscillator of frequency fosc is used. The output frequency of crystal oscillator is divided by M with the help of the divide by M network. Thus the input frequency to PLL is fosc/m. The PLL will compare this frequency with the frequency at the output of divide by N network and will try to adjust this frequency equal to fosc / M. In order to obtain the same frequency (fosc/m) at the output of divide by N network,the VCO frequency should be adjusted to, fvco = (fosc /M) * N The equation indicates that by adjusting the ratio (N/M) we can obtain a large number of frequencies. EC2254 LINEAR INTEGRATED CIRCUITS II/IV SEM ECE - L.M.I.LEO JOSEPH ASST.PROF/ECE PAGE 27