Diode Circuits Recent GATE Problems

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Diode Circuits Recent GATE Problems 1. The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across the diode DD 1 is CC 1 DD 2 cos(ωωωω) AC DD 1 CC 1 (a) cos(ωωωω) 1 (b) sin(ωωωω) Soln. Given, Voltage vv(tt) = cccccc ωωωω (c) 1 cos(ωωωω) (d) 1 sin(ωωωω) [GATE 2012: 1 Mark] Find the voltage across the diode D1 (diodes and capacitors are ideal) When the positive cycle of the input is applied diode D1 is forward biased and D2 is reverse biased. Capacitor C1 charges to maximum voltage (here 1 V) When negative cycle of the input comes D1 is reverse biased, so replaced by open. Note that D2 is reverse biased forever and can be replaced by a open switch. 1 cos(ωωωω) AC C VV(tt) = cos(ωωωω) 1 cos(ωωωω) 0 1 (cos ωωωω 1) 0 1 t t 2

In this circuit C1 & D1 form a clamper circuit while D2 and C2 form peak detector. This cascaded circuit acts as peak to peak detector. Option (a) 2. The i v characteristics of the diode in the circuit given below are vv 0.7 ii = AA, 500 0AA, vv 0.7 VV vv 0.7 VV 1 kkω 10 VV v The current in the circuit is (a) 10 ma (b) 9.3 ma Soln. As per the given i v characteristics ii = vv 00.77 555555 AA ffffff vv 00. 77 VV (11) i (c) 6.67 ma (d) 6.2 ma [GATE 2012: 1 Mark] From the given circuit, vv = 1111 1111111111 (22) 1 kkω 10 VV v From equation (1) and (2) eliminate v ii = 1111 1111111111 00. 77 555555 = i 99. 33 555555 2222

oooo, 3333 = 99. 33 555555 33. 11 oooo ii = = 66. 222222 555555 Thus, option (d) 3. In the circuit shown below, the knee current of the ideal Zener diode is 10 ma. To maintain 5 V across R L, the minimum value of R L in Ω and the minimum power rating of the Zener diode in mw, respectively are 100Ω 10V II LLoooooo VV ZZ = 5VV RR LL (a) 125 and 125 (b) 125 and 250 (c) 250 and 125 (d) 250 and 250 [GATE 2013: 2 Marks] Soln. Given, Knee current of Zener (II zzzz ) = 11111111 Knee current of Zener is the minimum current that should flow through the diode for proper Zener action Zener is of 5V i.e. VV zz = 5555 Find, minimum RL and diode power rating. The minimum value of RL means the load current is maximum (Imax) So, VV RRRR = II LLLLLLLL. RR mmmmmm oooo, RR mmmmmm = VV RRRR II LLLLLLLL = 55 II LLLLLLLL (11)

Note, II = II zzzz II LLLLLLLL oooo, II LLLLLLLL = II II zzzz = 5555 1111 = 44444444 RR mmmmmm = 55 55555555 = 4444 1111 33 4444 = 555555 44 = 111111ΩΩ Minimum power rating of Zener diode. It will be decided by the maximum current in Zener. PP zz = VV zz. II zzzzzzzz Option (b) = 55 5555 mmmm = 222222 mmmm 4. A voltage 1000 sin(ωωωω) volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in volts, is W 1 kkω Y Z 1 kkω X (a) sin(ωωωω) (b) (sin ωωωω sin ωωωω )/2 (c) (sin ωωωω sin ωωωω )/2 (d) 0 for all t [GATE 2013: 2 Marks] Soln. Voltage applied across Y Z terminals vv ii = 11111111 ssssss ωωωω Diodes are assumed ideal For positive cycle of the input All four diodes are Reverse biased VV WW VV XX = 00 oooo, VV WWWW = 00 For negative cycle of the input

All diodes are forward biased i.e. short circuited VV WWWW = VV WW VV XX = 00 Thus, VWX is zero for all times Option (d) 5. The figure shows a halfwave rectifier. The diode D is ideal. The average steadystate current (in Amperes) through the diode is approximately D 10 sin ωωtt f = 50 Hz AC R 100Ω C 4 mf Soln. Given, Input signal = 1111 ssssss ωωωω Frequency = 50 Hz Period of the waveform TT = 11 ff = 11 5555 = 2222 mm ssssss Time constant = RRRR = 111111 44 1111 33 ssssss. Note here, RC >> T = 400 m sec. [GATE 2014: 1 Mark] Thus the voltage across the resistor can be approximated to 10V (DC).

D AC 10V II DDDD 100 Ω 10V 100 Ω Current through the diode II DD (DDDD) = 111111 = 00. 11 AA 111111 This circuit is also sometimes called half wave peak detector. In AM receives it is used to detect envelope of AM wave Answer 0.1 A 6. Two silicon diodes, with a forward voltage drop of 0.7 V, are used in the circuit shown in the figure. The range of input voltage V i for which the output voltage V 0 = V i is (a) 0.3 VV < VV ii < 1.3 VV (b) 0.3 VV < VV ii < 2 VV (c) 1.0 VV < VV ii < 2.0 VV (d) 1.7 VV < VV ii < 2.7 VV RR DD 1 DD 2 VV 0 VV 0 1 VV DC DC 2 VV [GATE 2014: 1 Mark] Soln. Given, Forward voltage drop of the given Si diodes is 0.7V Find, the range of Vi for which output voltage VV 00 = VV ii Let us see the D2 branch of the circuit. D2 will be forward biased when VV ii > 00. 77 22 = 22. 7777

D2 will be Reverse biased when VV ii < 22. 7777 See the branch D1 D1 will be forward biased when VV ii < 11 00. 77 = 11. 7777 D1 will be Reverse biased when VV ii > 11. 77 VV When both the diodes will be Reverse biased (both shunt branches will be open) then VV 00 = VV iiii Thus, it will happen when D2 is Reverse biased i.e. VV ii < 22. 7777 D1 is Reverse biased i.e. VV ii > 11. 7777 Thus, 11. 7777 < VV ii < 22. 7777 Option (d) 7. For the circuit with ideal diodes shown in the figure, the shape of the output (VV oooooo ) for the given sine wave input (VV iiii ) will be 0 0.5 TT TT VV iiii VV 0uuuu (aa) 0 TT (bb) 0 0.5 TT 0.5 TT TT (cc) 0 0.5 TT TT (dd) 0 0.5 TT TT [GATE 2015: Mark] Soln. The given circuit can be redrawn as

Vi 0.5T T t a Vin b D1 D2 A R B Vout 0.5T T t For ve half cycle of the input D1 and D2 are ON VV oooooo = VV iiii For ve half cycle of the input D1 and D2 are off VV oooooo = 0000 Option (c) 8. In the circuit shown below, the Zener diode is ideal and Zener voltage is 6 V. The output voltage V 0 (in volts) is. 1 kkω 10 VV 1 kkω VV 0 [GATE 2015: 1 Mark] Soln. Given, Zener voltage = 6 V Zener diode is reverse biased during its operation. Here with the applied voltage, the voltage across the Zener diode is VV 00 = 11 KKΩΩ 111111 KKΩΩ 111111 = 5555 Diode will be reverse biased but not in the Zener region, so open circuited.

Answer Thus, V0 = 5V 9. If the circuit shown has to function as a clamping circuit, then which one of the following conditions should be satisfied for the sinusoidal signal of period T? C VV AC R (a) RC << T (b) RC = 0.35 T Soln. Observe the following circuit C (c) RC = T (d) RC >> T [GATE 2015: 1 Mark] VV DC D This circuit is of a negative clamper. The present circuit has a load resistor connected in shunt. When diode is off the capacitor discharges through resistor R. The output falls exponentially with time constant RC to avoid the discharge of capacitor significantly RC >> T Where T is period of the sinusoidal waveform applied to the given circuit. Option (d) 10. The diode in the circuit given below has VV OOOO = 0.7 VV but ideal otherwise. The current (in ma) in the 4 kω resistor is.

1 ma 22 kkωω D 11 kkωω 33 kkωω 44 kkωω 66 kkωω [GATE 2015: 2 Marks] Soln. The given circuit is a bridge circuit note that the cross arm product is same i.e. 22 66 = 44 33 12 = 12 So, bridge is balanced So no current through 1 kω resistor Now current through 4 kω resistor will be II = 99 99 66 111111 = 99 mmmm = 00. 66 mmmm 1111 Answer 0.6 ma 11. In the circuit shown, assume that diodes D 1 and D 2 are ideal. In the steadystate condition the average voltage V ab (in Volts) across the 0.5 µf capacitor is. 1 μμff 50 sin(ωωωω) AC D 1 D 2 bb 0.5 μμμμ aa VV aaaa [GATE 2015: 1 Mark]

Soln. The given circuit can be redrawn as follows: 111111 50 sin(ωωωω) AC D1 00. 55 μμμμ b a VV aaaa D2 During ve half cycle of the applied sinewave input D1 is forward biased 111111 Applying KVL 5555 VV CCCC = 00 oooo, VV CCCC = 555555 During ve cycle of input Applying KVL 5555 5555 VV aaaa = 00 oooo, VV aaaa = 11111111 50VV AC 50VV AC 50VV VVCCCC VV aaaa Answer 100V 12. In the circuit shown, assume that the diodes D 1 and D 2 are ideal. The average value of voltage V ab (in volts) across terminals a and b is. 6ππ sin(ωωωω) AC aa D 1 D 2 10 kkω bb 10 kkω VV aaaa 20 kkω [GATE 2015: 1 Mark]

Soln. During positive cycle of the input D1 is Forward biased and D2 is Reverse biased The circuit reduces to a 10 KK VV iiii = 6666 ssssss ωωωω VV iiii AC 10 KK b 20 KK VV aaaa = 1111 KK 1111 KK 2222 KK. VV iiii = VV iiii 33 = 6666 ssssss ωωωω 33 = 2222 ssssss ωωωω During negative cycle of the input D1 is Reverse biased b VV aaaa = D2 is Forward biased 111111 111111 111111. VV iiii = VV iiii 22 VV iiii AC VV aaaa a 10 KK 20 KK = 6666 ssssss ωωωω 22 = 3333 ssssss ωωtt 10 KK V0 3333 22ππ 0

VV aaaa = 2222 ππ 3333 ππ = 55 vvvvvvvvvv Answer: 5 volts 13. Assume that the diode in the figure has VV oooo = 0.7 VV, but is otherwise ideal. R1 DC 22 VV 22 kkωω i 2 R2 66 kkωω The magnitude of the current i 2 (in ma) is equal to [GATE 2016: 1 Mark] Soln. The given circuit can be redrawn as 2VV DC 2222ΩΩ 66KKΩΩ Thevenin equivalent This circuit can be further simplified using Thevenins theorem 2222 6666 DC 22 22 66 22 = 44 = 00. 5555 88

Voltage across diode is 0.5V thus the diode is OFF. The circuit reduces to DC 2KK 6KK ii 22 The current through 6 K ii 22 = Answer: 0.25 ma 22 2222 6666 = 22 = 00. 2222 mmmm 8888 14. The diodes D1 and D2 in the figure are ideal and the capacitors are identical. The product RC is very large compared to the time period of the ac voltage. Assuming that the diodes do not breakdown in the reverse bias, the output voltage V 0 (in volt) at the steady state is D1 1111 ssssss(ωωωω) AC C C R V0 D2 [GATE 2016: 1 Mark] Soln. Diodes D1 and D2 are ideal. The above circuit can be redrawn as

1111 ssssss(ωωωω) AC 10V V0 10V During positive cycle of input D1 and D2 are shorted thus VV 00 = 0000 During negative cycle the diodes are reverse biased VV 00 = 0000 Thus VV 00 = 0000 all the times 15. The figure shows a halfwave rectifier with a 475 µf filter capacitor. The load a draws a constant current I 0 = 1 A from the rectifier. The figure also shows the input voltage V i the output voltage V c and the peaktopeak voltage ripple u on V c. The input voltage V i is a trianglewave with an amplitude of 10V and a period of 1 ms. 0 10V 10V Vi t VC u 0 The value of the ripple u (in volts) is. Soln. Given, Half wave rectifier circuit [GATE 2016: 2 Marks] t

Filter capacitor = 475 µf Load draws constant current of 1 Amp. The input voltage is triangular. Output voltage Vc is given One has to determine ripple (peak to peak) Amount of charge lost by the capacitor should be equal to the charge gained during charging i.e II dddd. TT = VV rr(pp pp). CC TTTTTTTT, VV rr (pp pp) = II dddd. TT CC = = 11 444444 111133 = 22. 1111 1111. 11 1111 33 444444 1111 66