INTEGRATED CIRCUITS Supersedes data of 992 May 4 2 Dec 8
FEATURES Fully synchronous operation Multiplexed 3-State I/O ports for bus oriented applicatio Built in cascading carry capability U/D pin to control direction of counting Separate pi for Master reset and Synchronous operation Center power pi to reduce effects of package inductance Count frequency 5 MHz Typ Supply current ma Typ See 74F269 for 24-pin separate I/O port version See 74F779 for 6-pin version DESCRIPTION The is a fully synchronous 8-stage Up/Down Counter with multiplexed 3-State I/O ports for bus-oriented applicatio. It features a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, except for the case of asynchronous reset, are initiated by the rising edge of the clock. TC output is not recommended for use as a clock or asynchronous reset due to the possibility of decoding spikes. PIN CONFIGURATION I/O I/O I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 2 3 4 5 6 7 8 9 2 9 8 7 6 5 4 3 2 ORDERING INFORMATION MR SR CEP CET VCC TC U/D PE CS OE SF85 TYPE TYPICAL f MAX CURRENT TYPICAL SUPPLY (TOTAL) 5MHz ma ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE V CC = 5 V ±%, T amb = to +7 C PKG DWG # INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 2-Pin Plastic DIP NN SOT46-2-Pin Plastic SOL ND SOT63-74F(U.L.) HIGH/LOW LOAD VALUE HIGH / LOW Data Inputs 3.5/. 7 µa /.6 ma I/O n Data Outputs 5/4 3. ma / 24 ma PE Parallel Enable input (active Low)./. 2 µa/.6 ma U/D Up/Down count control input./. 2 µa /.6 ma MR Master Reset input (active Low)./. 2 µa /.6 ma SR Synchronous Reset input (active Low)./. 2 µa /.6 ma CEP Count Enable Parallel input (active Low)./. 2 µa /.6 ma CET Count Enable Trickle input (active Low)./. 2 µa /.6 ma CS Chip Select input (active Low)./. 2 µa /.6 ma OE Output Enable input (active Low)./. 2 µa /.6 ma Clock input (active Rising Edge)./. 2 µa/.6 ma TC Terminal Count Output (active Low) 5/33. ma / 2 ma NOTE: One (.) FAST Unit Load (U.L.) is defined as: 2 µa in the High state and.6 ma in the Low state. 2 Dec 8 2 853-377 25265
LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) 8 7 CEP OE 3 PE 2 2 9 4 CS MR SR U/D CET TC 5 I/O I/O I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 9 2 3 4 7 CTR DIV 256 R & M2[LOAD] & EN3 M4[DOWN] M5[UP] EN6 V CC = Pin 6 GND = Pin 6 2 3 4 5 7 8 9 SF86 8 2 & G7 2,5,7, +/C8 2,4,7 R9 [] [2] [4] [8] [6] [32] [64] [28],2,3,4, 5,6,7,8 2 3 4 5 7 8 9 3,5,6,8 CT=256 3,4,6,8 CT= 5 SF87 FUNCTION TABLE INPUTS MR SR CS PE CEP CET U/D OE OPERATING MODE X X H X X X X X X I/O to I/O7 in high impedance (PE disabled) X X L H X X X H X I/O to I/O7 in high impedance X X L H X X X L X Flip-flop output appears on I/On lines L X X X X X X X X Asynchronous reset for all flip-flops H L X X X X X X Synchronous reset for all flip-flops H H L L X X X X Parallel load all flip-flops H H (not LL) H X X X Hold H H (not LL) X H X X Hold (TC held High) H H (not LL) L L H X Count up H H (not LL) L L L X Count down H = High voltage level L = Low voltage level X = Don t care = Low-to-High clock traition (not LL) = CS and PE should never be Low voltage level at the same time. 2 Dec 8 3
LOGIC DIAGRAM SR 9 PE 3 MR CS 2 2 OE I/O 2 I/O 3 I/O2 4 I/O3 5 I/O4 7 I/O5 8 I/O6 9 I/O7 U/D 4 CEP 8 TOGGLE MR CET 7 DATA TC 5 LOAD D Q Q Q Q VCC=pin 6 GND=pin 6 For pinouts refer to Package Pin Configuratio SF88 2 Dec 8 4
ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage.5 to +7. V V IN Input voltage.5 to +7. V I IN Input current 3 to +5 ma V O Voltage applied to output in High output state.5 to +V CC V I O Current applied to output in Low output state TC 4 ma I/O 48 ma T amb Operating free-air temperature range to +7 C T stg Storage temperature 65 to +5 C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX V CC Supply voltage 5. V V IH High-level input voltage 2. V V IL Low-level input voltage.8 V I IK Input clamp current 8 ma I OH High-level output current TC ma I/O n 3 ma I OL Low-level output current TC 2 ma I/O n 24 ma T amb Operating free-air temperature range 7 C 2 Dec 8 5
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP 2 MAX UNIT V OH High-level output voltage TC I/O n V CC = MIN, V IL = MAX, I OH = ma V IH = MIN (V IL =. V, V IH =45V I OH = 3 ma for MR, inputs) V CC = MIN, V OL Low-level output voltage V IL = MAX, I OL = MAX, V IH = MIN ±%V CC 2.5 V ±5%V CC 2.7 3.4 V ±%V CC 2.4 3.3 V ±5%V CC 2.7 3.3 V ±%V CC.35.5 V ±5%V CC.35.5 V V IK Input clamp voltage V CC = MIN, I I = I IK.73.2 V Input current I/O n V CC = MAX, V I = V ma I I at maximum input voltage others V CC = MAX, V I = 7. V µa I IH High-level input current except V CC = MAX, V I = 2.7 V 2 µa I IL Low-level input current I/O n VCC = MAX, V I =.5 V.6 ma I OZH + I IH I OZL + I IL Off-state output current High-level voltage applied Off-state output current Low-level voltage applied V CC = MAX, V O = 2.7 V 7 µa I/O n V CC = MAX, V O =.5 V 6 µa I OS Short-circuit output current 3 V CC = MAX 6 5 ma I CCH 95 35 ma I CC Supply current (total) I CCL V CC = MAX 5 45 ma I CCZ 5 5 ma NOTES:. For conditio shown as MIN or MAX, use the appropriate value specified under Recommended Operating Conditio for the applicable type. 2. All typical values are at V CC = 5 V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, I OS tests should be performed last. 2 Dec 8 6
AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDI- TIONS LIMITS T amb = +25 C V CC = +5. V C L = 5 pf, R L = 5 Ω T amb = to +7 C V CC = +5. V ± % C L = 5 pf, R L = 5 Ω MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform 5 8 MHz t PZH t PZL t PHZ t PLZ t PZH t PZL t PHZ t PLZ t PZH t PZL t PHZ t PLZ Propagation delay to I/O n Waveform Propagation delay to TC Propagation delay U/D to TC Propagation delay CET to TC Waveform Waveform 4 Waveform 3 5. 5. 3.5 3.5 3.5 Propagation delay MR to I/O n Waveform 2 5. 7. 9. 5.. Propagation delay MR to TC Waveform 4 Output Enable time Waveform 6 CS to I/O n Waveform 7 Output Disable time Waveform 6 CS to I/O n Waveform 7 Output Enable time Waveform 6 PE to I/O n Waveform 7 Output Disable time Waveform 6 PE to I/O n Waveform 7 Output Disable time Waveform 6 OE to I/O n Waveform 7 Output Enable time Waveform 6 OE to I/O n Waveform 7 4. 6. 4. 3. 5. 3. 5. 3. 2.5 2.5. 2. 6.5 6. 6.5 8. 5. 7. 5. 6.5 4. 4. 4. 2.5 4..5.5.. 8. 8. 7. 8. 9..5 8.5.5 9.5 8.. 7. 9. 4. 7. 5. 5. 5. 3.5 3.5 3.5 4. 6. 3.5 5. 3. 3. 3. 2. 2.5 4.. 2..5.5.. 9. 9. 8.5 8.5.5 2.5..5 9.. 9.. 9. 8.5 8.5.5 8. UNIT 2 Dec 8 7
AC SETUP REQUIREMENTS SYMBOL t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t w (H) t w (L) PARAMETER Setup time, High or Low I/O n to Hold time, High or Low I/O n to Setup time, High or Low U/D to Hold time, High or Low U/D to Setup time, High or Low PE, SR or CS to Hold time, High or Low PE, SR or CS to Setup time, High or Low CEP or CET to Hold time, High or Low CEP or CET to TEST CONDITIONS Pulse width, High or Low Waveform LIMITS T amb = +25 C V CC = +5. V C L = 5 pf, R L = 5 Ω T amb = to +7 C V CC = +5. V ± % C L = 5 pf, R L = 5 Ω MIN TYP MAX MIN MAX t w (L) MR Pulse width, Low Waveform 2 3. 3. t rec Recovery time, MR to Waveform 2 4. 3. 3. 8. 8. 9.5 9.5 5. 9. 4. 4. 9. 9....5 UNIT 2 Dec 8 8
AC WAVEFORMS NOTE: For all waveforms =.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. /f MAX MR t W (H) t W (L) t W (L) t rec I/O n VM I/O n TC VM SF89 Waveform. Propagation Delay, Clock Input to Output, Clock Pulse Width and Maximum Clock Frequency SF9 Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time CET MR, U/D TC TC SF9 Waveform 3. Propagation Delay, CET Input to Terminal Count Output SF92 Waveform 4. Propagation Delay, U/D and MR Inputs to Terminal Count Output PE, CS, U/D, SR, I/O n, CEP, CET t s (H) t h (L) t s (L) t h (L) PE, OE, CS t PZH t PHZ V OH -.3V I/O n. Setup and Hold Times SF93 SF94 Waveform 6. 3-State Output Enable Time to High Level and Output Disable Time from High Level PE, OE, CS t PZL t PLZ I/O n V OL +.3V SF95 Waveform 7. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 2 Dec 8 9
TEST CIRCUIT AND WAVEFORMS PULSE GENERATOR V IN V CC D.U.T. V OUT R L 7.V NEGATIVE PULSE 9% % t THL ( t f ) t w t TLH ( t r ) % 9% AMP (V) V R T C L R L Test Circuit for 3-State Outputs SWITCH POSITION TEST SWITCH t PLZ closed t PZL closed All other open POSITIVE PULSE % t TLH ( t r ) t THL ( t f ) 9% 9% t w Input Pulse Definition % AMP (V) V DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F INPUT PULSE REQUIREMENTS amplitude rep. rate t w t TLH t THL 3.V.5V MHz 5 2.5 2.5 SF777 2 Dec 8
DIP2: plastic dual in-line package; 2 leads (3 mil) SOT46-2 Dec 8
SO2: plastic small outline package; 2 leads; body width mm SOT63-2 Dec 8 2
NOTES 2 Dec 8 3
Data sheet status Data sheet status Product status Definition [] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contai the design target or goal specificatio for product development. Specification may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai final specificatio. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [] Please coult the most recently issued datasheet before initiating or completing a design. Definitio Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 34). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditio above those given in the Characteristics sectio of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 8 East Arques Avenue P.O. Box 349 Sunnyvale, California 9488 349 Telephone 8-234-738 Copyright Philips Electronics North America Corporation 2 All rights reserved. Printed in U.S.A. Date of release: - Document order number: 9397 75 7887 2 Dec 8 4