A New Three Phase Multilevel Inverter With Reduced Number Of Switching Power Devices With Common Mode Voltage Elimination Arpan Hota, Sachin Jain Department of Electrical Engineering National Institute of Technology Warangal Warangal, India hota.arpan@gmail.com, jsachin@nitw.ac.in Abstract This paper presents a new topology for a 3-ϕ, three step multilevel inverter (MLI) with Common Mode Voltage (CMV) elimination. The proposed MLI structure is realized with fewer switching power devices compared to the conventional MLI solutions for CMV elimination. A space vector modulation technique, based on Large Medium Zero Vector Modulation (LMZVM), is also proposed to operate the presented MLI. Reduced number of switching power devices results in less number of driver circuits, reduced installation space and low cost. Further, due to the elimination of CMV, the proposed MLI is free from issues like EMI and leakage current. Presented topology is compared with other topologies to prove its superiority. Simulation results are presented to confirm the capability of the proposed MLI. Keywords Common Mode Voltage elimination; 3-ϕ Multilevel Inverter; Reduced switching power device; I. INTRODUCTION The demand for High Voltage (HV) and high power applications is increasing rapidly. At the same time there are increasing constraints with respect to size, volume, cost and weight of the systems. This restricts the use of low frequency heavy weight transformers in HV and high power applications which would have been a viable solution. Also, the usage of low frequency transformer restricts the variation in input and output voltage. Thus, there is a requirement for power conditioners which not only give extended bandwidth for variations in input and output voltage but also have the advantages of low weight, low cost and controllability. For these reasons, the HV power converters are at the focal point of continuing studies for the researchers. Among the various options, Multilevel Inverters (MLI) are a good solution for HV applications, as they are supported by advantages like high power quality (low THD), reduced switching loss and lower dv/dt stress [-5]. However MLIs are often operated at high frequency to reduce the size and improve power quality. This may result in high frequency voltage transitions between the load and source neutral point. This voltage is also known as CMV. The high frequency switching of CMV causes several issues in electrical systems like electromagnetic interference, leakage current etc. These problems also restrict the application of Vivek Agarwal Department of Electrical Engineering Indian Institute of Technology Bombay Mumbai, India agarwal@ee.iitb.ac.in MLI to various sophisticated fields like aerospace, military, medical etc. In case of electric drives applications, the high frequency transitions of CMV may cause leakage current and bearing current, which are hazardous for the motor. It can also result in lubricant insulation failure [6-7]. For PV applications high frequency voltage transition in CMV causes the flow of leakage current in the stray capacitance between the grounded body of the PV cell and the PV cell itself [8]. In literature there are several methods and MLI configurations which have been proposed to eliminate or reduce the CMV. Configurations proposed in [9-] use a dual inverter system for its application to an open-end winding induction motor with CMV reduction. These are good solutions but for specific application. Some other proposed topologies in [3-4] eliminate CMV in induction motor drives. However they suffer the disadvantage of higher switch count. This results in higher cost, size and weight of the MLI. Another good solution given by Lee et.al. where authors have proposed a new PWM technique for reduction of the CMV in 3-ϕ grid connected PV system [5]. It also minimizes leakage current. In short all the above solutions are either application specific or require more number of devices for the elimination of CMV. This paper presents an optimized configuration of a 3-ϕ MLI with minimum number of switches. The proposed system eliminates the CMV and high frequency voltage transition in between the load neutral and source terminal points. Proposed topology requires simple Space Vector Modulation (SVM) strategy with Large Medium Zero Vector Modulation (LMZVM) [5]. LMZVM is modified in a way that it can completely eliminate CMV for the proposed MLI structure. The proposed MLI structure is optimized with respect to the PWM strategy. So, it can eliminate CMV even with a reduced switch count compared to the conventional solutions. This manuscript is divided into five sections. Section II describes about the structure of the proposed 3-ϕ MLI. Section III discuss about the PWM technique used to operate the proposed MLI. Section IV gives the comparison of the proposed topology with the conventional topologies and the recent topologies proposed. The simulation results are shown
and explained in section V and the concluding statements are given in section VI. MLI for CMV elimination. The details of the PWM strategy are given in the next subsection. II. OPERATION OF THE PROPOSED MLI Fig. shows the configuration of the proposed 3-ϕ MLI topology with CMV elimination. The structure comprises 3 switches. As shown in Fig. phase A can be connected to bus, or 3 by using the power switches S A, S A or S 3A respectively. Similarly for phase B the switches are S B, S B or S 3B and for phase C, the switches are S C, S C or S 3C. Out of these switches, S A, S B and S C are four quadrant switches. These switches are realized by anti-series connection of two MOSFETs with anti-parallel diode. All other switches are two quadrant switches which can be realized by single MOSFETs with anti-parallel diode. Thus, to realize these nine switches twelve MOSFETs are required. Further, it may be observed in Fig. that these switches connect the 3-ϕ output to three buses (bus, and 3). So, they are called phase-to-bus switches. Another important point to be noted is that the proposed configuration requires four dc voltage sources each of equal magnitude (V dc ) as can be observed in Fig.. The string of the dc sources consists of five terminal or nodal points at the dc bus (P, P, P, P 3, P 4 ). Now, as suggested by Fig., bus can be connected to nodal point P 3 if switch S is turned ON or can be connected to nodal point P if switch S is turned ON. Switch S and S cannot be turned ON simultaneously as that will cause a shoot through. Similarly, Bus 3 can be connected to nodal point P if switch S 3 is active or nodal point P if switch S 4 is active but to avoid shoot through problem, S 3 and S 4 cannot be turned ON simultaneously. Switches S, S, S 3 and S 4 are called bus-to-point switches. These four switches are also two-quadrant in nature. So, they can be realized using single MOSFETs. Thus, the total number of MOSFETs required to build the complete topology is sixteen. A star connected load is connected at the nodal point P A, P B and P C with load neutral point N. Now, by properly switching phase-to-bus and bus-topoint switches many state vectors can be generated. For example, a certain vector [X,Y,Z] can be generated by connecting phase A to point P X, phase B to point P Y and phase C to nodal point P Z (X,Y,Z ranges from to 4). Proposed topology can generate 3 state vectors for which CMV is zero. These 3 vectors are presented in Table. The active switches for each of the vector are also shown in Table. For example to generate the vector [, 4, ] phase A, B and C should be connected to nodal point P, P 4 and P respectively. Now, nodal point P is only accessible via bus 3 so, phase A and C both connected to bus 3 by turning ON switch S 3A and S 3C then bus 3 is connected to nodal point P by turning ON switch S 3. Similarly nodal point P 4 is accessible directly via bus so, switch S B is turned ON to connect phase B to nodal point P. Similarly, other vectors with zero CMV can be found as described in Table I. These 3 vectors are plotted in Fig. which takes the form of a hexagon with Sectors. And a suitable PWM strategy is devised to operate proposed 3 phase Fig.. Proposed optimized 3-ϕ MLI topology with zero CMV. TABLE I. VOLTAGE VECTORS WITH ZERO CMV AND THE CORRESPONDING ACTIVE SWITCHES State Vector Corresponding active switches (while all location [Fig. ] other switches are turned OFF) [,,] S A, S B, S C, S [4,,] S A, S 3B, S 3C, S 3 [4,,] S A, S B, S 3C, S, S 4 [3,3,] S A, S B, S 3C, S, S 4 [,4,] S A, S B, S 3C, S, S 4 [,4,] S 3A, S B, S 3C, S 3 [,4,] S 3A, S B, S C, S, S 4 [,3,3] S 3A, S B, S C, S, S 4 [,,4] S 3A, S B, S C, S, S 4 [,,4] S 3A, S 3B, S C, S 3 [,,4] S A, S 3B, S C, S, S 4 [3,,3] S A, S 3B, S C, S, S 4 [4,,] S A, S 3B, S C, S, S 4 Fig.. State vectors generated using proposed optimized configuration with zero CMV.
III. PWM STRATEGY The PWM technique required to operate the proposed 3 phase MLI uses LMZVM method [5]. LMZVM is an SVM strategy, which uses state vectors located in the hexagon boundary and its centre as given in Fig.. There are twelve vectors, which are located at the hexagon boundary and the zero vector [,,] which is located at the centre. Out of those vectors 6 are large vectors and the remaining 6 are medium vectors. Large vectors utilize all dc bus voltage which results a vector with magnitude 3.74V dc. Similarly medium voltage vector bypasses one dc source resulting in a vector with magnitude 3V dc. Large voltage vectors are [4,,], [4,,], [,4,], [,,4], [,,4] and [,4,]. Medium voltage vectors are [4,,], [,,4], [,4,], [,3,3], [3,,3] and [3,3,]. The magnitude and angle values for all the vectors are listed in Table II. These 3 vectors divide the hexagon in sectors as illustrated by Fig.. Now, the output vector at any sector will be realized using a large vector, a medium vector and a zero vector. To achieve this following steps are involved: Step : The sector identification is done from the value of the angle of the output vector. Step : The switching times are calculated for the three vectors associated with the identified sector. One example is taken for a given sector as shown in Fig. 3. As Fig. 3 suggests the sector is made up of large, medium and zero vectors. X is the medium vector, X is the large vector and the zero vector is. Now, an output vector X has to be implemented using the three vectors. This is achieved when X vector is turned ON for time T, vector X is turned ON for time T and the zero vector is turned ON for T time. If total switching time is T S then T + T + T = T S () And T X θ T X θ T X θ () X Or, X S cos sin X cos T cos TS X sin (3) X T sin T X cos X cos cos Or, TS X (4) T X sin X sin sin Fig. 3. Generation of output voltage vector using LMZVM. Now, using the values from Table II in () and (4) the values of T, T, T can be calculated. TABLE II. STATE VECTORS WITH THEIR ANGLE AND MAGNITUDE Vector Number State Vector Magnitude of the vector (in voltage) [,,] / 36 [4,,] 3V dc / 36 [4,,] 3.74V dc 3 3 [3,3,] 3V dc 6 4 [,4,] 3.74V dc 9 5 [,4,] 3V dc 6 [,4,] 3.74V dc 5 7 [,3,3] 3V dc 8 8 [,,4] 3.74V dc 9 [,,4] 3V dc 4 [,,4] 3.74V dc 7 [3,,3] 3V dc 3 [4,,] 3.74V dc 33 Angle of the vector (in degrees) Now, it may be observed in Table II that among the nonzero vectors, the minimum magnitude is 3V dc. The circle inscribed inside the hexagon can have a maximum radius of 3V dc as can be observed from Fig.. So, the linear range of modulation exists for the output voltage vector with magnitude up-to 3V dc. The amplitude modulation index is defined as: X m a = (5) 3Vdc When m a is operated between and it is the range for linear modulation. In the range of linear modulation the output voltage will always have same number of levels. Because any arm of the hexagon in Fig. has three vectors and whatever the value of m a the chosen vectors to implement the output vector are always selected from hexagon boundary and its centre. The voltage spikes in CMV that may occur due to the dead band can be suppressed by using a common mode capacitive filter. IV. COMPARISON OF THE PROPOSED CMLI WITH EXISTING TOPOLOGIES The purpose of the introduction of the proposed 3 phase MLI is to eliminate CMV with a reduction in the number of power semiconductor devices. Therefore, the proposed CMLI is compared with existing topologies in terms of number of switching power devices, number of levels produced and CMV. The configuration proposed in [4] requires 4 switches to completely eliminate CMV and it produces three level output. Whereas the proposed topology consists of only 6 switches and it also produces a three level output voltage.
The topology and the PWM technique presented in [5] requires only power switches but it cannot eliminate CMV completely whereas the presented topology completely eliminates CMV. The proposed topology is also compared with the three level NPC, three level Cascaded H-bridge (CHB) and the proposed topology in [4] and [5] in terms of number of switches and CMV. The comparison results are presented in Table III. observation can be made from Fig. 7 is that the current becomes more trapezoidal with the increase of m a. Though slight increase in current THD can be observed with the increase of m a, it is always less than 5% meeting the IEEE 547 standard. TABLE III. COMPARISON OF THE PROPOSED TOPOLOGY WITH EXISTING TOPOLOGIES 3-ϕ Three level MLI Topology Number of power semiconductors V. SIMULATION RESULTS CMV NPC 8 Not eliminated Cascaded H-bridge Not eliminated Configuration given by 4 eliminated Kumar et.al. [4] Configuration given by Reduced Lee et.al. [5] Presented topology in this paper 6 eliminated The performance of the above mentioned 3 phase MLI has been investigated by using a simulation model in MATLAB/SIMULINK environment with PLECS block-set. Switching frequency is kept at khz. Each phase of the 3 phase Y connected load consists of an RL load with R= Ω and L=.5 H while the value of voltage of each voltage source is Volts i.e. V dc = Volts. Fig. 4 (a) shows the 7 level line to line output voltage of the proposed MLI at m a =. The sinusoidal nature of the load current is depicted in Fig. 4 (b). From Fig. 4 (c) it can be seen that the CMV is zero which proves the fact that the proposed MLI eliminates the CMV. From Fig. 5 it can be seen that the voltage difference between load neutral point N and different nodal points from the string of the sources (P, P, P, P 3, P 4 ) are constant. As these voltages do not involve any high frequency voltage transitions it can be inferred that, the proposed MLI eliminates the leakage current flow when used for PV applications. Output voltage and current waveform with current THD at different m a under linear modulation have been recorded in Fig. 6. An important observation can be made from Fig. 6 that for every value of m a output voltage waveform always has 7 levels which proves the fact that the proposed MLI will have same number (7) of levels irrespective of the value of m a. But it can also be seen from Fig. 6 that as m a decreases pulse width also decreases. Fig. 7 shows output voltage and current with THD in over-modulation at different m a values with m a greater than. It is evident from Fig. 7 that as m a increases the switching time of zero vector reduces. And at m a =.3 there is no switching of zero vector i.e. the output vector is completely outside of the hexagon boundary. Another important Fig. 4. (a) Line to line output voltage of the proposed MLI (b)load current (c) CMV between load neutral N and source neutral P. The blocking voltages of the switches (S A, S A, S 3A ) that connects phase A to the three buses are shown in Fig. 8. For the other phases the waveform will be same but degree phase shifted. One important observation can be made from Fig. 8 (b) that the blocking voltage of switch S A varies from -3 volts to volts which supports the requirement of a four quadrant, bi directional switch for the realization of S A. Fig. 8 also indicates that switch S A and S 3A will stay in turn OFF state for a long time (T OFF ). And switching state transition happens between to V which is half of the total dc bus voltage. So, it can be concluded that switches S A S 3A will have low switching loss. Fig. 9 shows the blocking voltage waveform of the bus-to-point switches S, S, S 3, S 4. The blocking voltage of the 4 bus-to-point switches are V which is one fourth of the total dc bus voltage. Fig. 5. V N, V N, V N, V 3N and V 4N are voltage difference between load neutral point N and P, P, P, P 3 and P 4 respectively.
Voltage (V) 4-4 - 4-4 - m a= m a=.7 m a=.5 m a=.3 3. 3.5 4. Time (sec) e- THD=.97% THD=.8% THD=3.67% m a =.3 THD=4.63% 3. 3.5 4. Time (sec) m a= m a=.7 m a=.5 - - - - e- Fig. 6. Output voltage (line to line) and load current at different values of m a under linear modulation with current THD. Voltage (V) 4-4 - 4 - m a=.3 m a=. m a=. 4.6% 3.5%.73% m a=.3 m a=. m a=. 4 - m a=.5 m a=.5 i.34% A -..5 3. 3.5 4...5 3. 3.5 4. Time (s) e- Time (s) e- Fig. 7. Output voltage (V/div.)(line to line) and load current (A/div.) at different values of m a under over modulation with current THD. Fig. 8. Blocking voltage of switches (a) S A (b) S A (c)s 3A. T ON: Continuous ON period of a switch. T OFF: Continuous OFF period of switch. T Sw: Period for high frequency switching transition. Current (A) - - - Current (A) Fig. 9. Blocking voltage of switches S, S, S 3, S 4. The load current THD for proposed MLI is always less than 5% as shown in Fig. 6 and 7. This meets the requirement of IEEE 547 standard. Therefore, the proposed MLI is expected to be a convenient solution for grid integration. The FFT analysis of load current is shown in Fig. for m a =. It can be seen that the maximum magnitude of the other harmonics is less than.6%. Mag(% of Fundamental) Fig.. FFT analysis for the load current shown in Fig. 4 (b). VI. CONCLUSION The topology presented in this paper is optimized with respect to the PWM strategy used to eliminate the CMV. So, the proposed configuration is blessed with the advantage of reduced number of power switches when compared to the existing topologies. Another advantage of the proposed MLI structure is the voltage difference between the load neutral point and the different terminals of dc bus are constant i.e. no high frequency voltage transition. This is expected to solve the major issues related to CMV like EMI and leakage current. Another important point to be noted is that the current THD of the proposed MLI converter meets the IEEE 547 standard. This results in better power quality performance. The abovementioned points indicate that the proposed MLI configuration is expected to be a good solution for drives applications and grid-tied PV applications. References [] Mittal, N.; Singh, B.; Singh, S.P.; Dixit, R.; Kumar, D., "Multilevel inverters: A literature survey on topologies and control strategies," Power, Control and Embedded Systems (ICPCES), nd International Conf. on, vol., no., pp.,, 7-9 Dec.. [] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng, "Multilevel inverters: a survey of topologies, controls, and applications," Industrial Electronics, IEEE Trans. on, vol.49, no.4, pp.74-738, Aug.
[3] Malinowski, M.; Gopakumar, K.; Rodriguez, J.; Pérez, M.A., "A Survey on Cascaded Multilevel Inverters," Industrial Electronics, IEEE Trans. on, vol.57, no.7, pp.97-6, July. [4] Lezana, P.; Pou, J.; Meynard, T.A.; Rodriguez, J.; Ceballos, S.; Richardeau, F., "Survey on Fault Operation on Multilevel Inverters," Industrial Electronics, IEEE Trans. on, vol.57, no.7, pp.7,8, July. [5] M. F. Kangarlu and E. Babaei, A generalized cascaded multilevel inverter using series connection of sub-multilevel inverters, IEEE Trans. Power Electron., vol. 8, no., pp. 65 636, Feb. 3. [6] S. Chen, T. A. Lipo, and D. Fitzgerald, Source of induction motor bearing currents caused by PWM inverters, IEEE Trans. Energy Convers., vol., no., pp. 5 3, Mar. 996. [7] J. Adabi, F. Zare, G. Ledwich, and A. Ghosh, Leakage current and common mode voltage issues in modern AC drive systems, in Proc. Australasian Univ. Power Eng. Conf., pp. 6, Dec. 9, 7, [8] Ozkan, Z. and Hava, A.M., "A survey and extension of high efficiency grid connected transformerless solar inverters with focus on leakage current characteristics," in Energy Conversion Congress and Exposition (ECCE), IEEE, pp.3453-346, 5- Sept. [9] M. R. Baiju, K. K. Mohapatra, R. S. Kanchan, and K. Gopakumar, A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive, IEEE Trans. Power Electron., vol. 9, no. 3, pp. 794 85, May 4. [] R. S. Kanchan, P. N. Tekwani, M. R. Baiju, K. Gopakumar, and A. Pittet, Three-level inverter configuration with common-mode voltage elimination for induction motor drive, IEE Proc. Electr. Power Appl., ol. 5, no., pp. 6 7, Mar. 4, 5. [] P. N. Tekwani, R. S. Kanchan, and K. Gopakumar, Five-level inverter scheme for an induction motor drive with simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance, IEE Proc. Electr. Power Appl., vol. 5, no. 6, pp. 539 555, Nov. 4, 5. [] Sudharshan Kaarthik, R.; Gopakumar, K.; Mathew, J.; Undeland, T., "An open-end winding IM drive with multilevel -sided polygonal vectors with symmetric triangles," in Power Electronics and Applications (EPE'4-ECCE Europe), 4 6th European Conference on, vol., no., pp.-9, 6-8 Aug. 4. [3] Kumar, P.R.; Kaarthik, R.S.; Gopakumar, K.; Leon, J.I.; Franquelo, L.G., "Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges," in Power Electronics, IEEE Trans. on, vol.3, no.7, pp.347-3478, July 5. [4] Roshan Kumar, P.; Rajeevan, P.P.; Mathew, K.; Gopakumar, K.; Leon, J.I.; Franquelo, L.G., "A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge," in Power Electronics, IEEE Trans. on, vol.9, no.3, pp.4-49, March 4. [5] June-Seok Lee; Kyo-Beum Lee, "New Modulation Techniques for a Leakage Current Reduction and a Neutral-Point Voltage Balance in Transformerless Photovoltaic Systems Using a Three-Level Inverter," in Power Electronics, IEEE Trans. on, vol.9, no.4, pp.7-73, April 4.