Southen Illinois Univesity Cabondale OpenSIUC Aticles Depatment of Electical and Compute Engineeing 7-06 Cuent Compensation Techniques fo Lowvoltage High-pefomance Cuent Mio Cicuits Stefan Leitne Haibo Wang zhwang@siu.edu Follow this and additional woks at: http://opensiuc.lib.siu.edu/ece_aticles The final publication is available at Spinge via the link below. Recommended Citation Leitne, Stefan and Wang, Haibo. "Cuent Compensation Techniques fo Low-voltage High-pefomance Cuent Mio Cicuits." Analog Integated Cicuits and Signal Pocessing 88, No. ( Jul 06): 79-88. doi:0.007/s0470-06-0743-z. This Aticle is bought to you fo fee and open access by the Depatment of Electical and Compute Engineeing at OpenSIUC. It has been accepted fo inclusion in Aticles by an authoized administato of OpenSIUC. Fo moe infomation, please contact opensiuc@lib.siu.edu.
Cuent Compensation Techniques fo Low-voltage High-pefomance Cuent Mio Cicuits Stefan Leitne and Haibo Wang Depatment of Electical and Compute Engineeing, Southen Illinois Univesity Cabondale, Cabondale, IL 690 Stefan Leitne email: ls330@siu.edu Abstact This pape pesents two cuent mio cicuits fo low-voltage applications. Unlike most cuent mios that use stacked tansistos in the output banch to boost the output esistance, the poposed designs use cuent compensation techniques to achieve high output esistance. By avoiding stacked tansistos in the output banch, the minimum output voltages of the poposed cicuits ae significantly lowe compaed to those of othe cuent mio cicuits with compaable output esistance. Paticulaly, the fist design emphasizes on educing the minimum output voltage to an extemely low level of aound 0mV. The second design stesses minimizing implementation cost. Compaed to a simple cuent mio cicuit, the second design equies only one additional tansisto but boosts the output esistance by moe than 0 times. Both cicuit analysis and simulations ae pesented to examine the pefomance of the poposed designs. Keywods: Low-voltage, cuent mio, cuent compensation, stability, CMOS cicuit The aticle is published in Analog Integated Cicuits and Signal Pocessing, Vol. 88, No., July, 06, pp. 79-88 http://link.spinge.com/aticle/0.007/s0470-06-0743-z
I. Intoduction Cuent mios (CM) ae essential building blocks of analog cicuits. Two citical paametes of a CM cicuit ae its output esistance out and the minimum output voltage V out,min. The latte is also efeed to as the CM compliance voltage and is to maintain the accuacy of the input and output cuent elation. A lage out enhances the accuacy of the CM cicuit and helps achieve high amplifie gain when the CM cicuit is used as the active load of the amplifie. Meanwhile, a small V out,min impoves signal headoom, which is highly desiable in low-voltage design. In geneal, the effots to impove one often negatively affects the othe, which leads to an inceasingly difficult tade-off with the scaling down of cicuit supply voltage. Taditionally, out of a CM cicuit is impoved by placing an additional tansisto M 3 on top of mio tansisto M as shown in Figue (a). This isolates M fom output voltage vaiations and hence helps stabilize output cuent I out. By using diffeent methods to geneate M 3 gate voltage V C, this stuctue has evolved into seveal well-known CM topologies, including classical cascode, wide-swing cascode, and gate egulated CM cicuits [8, ]. The classical cascode topology biases V C at the level of V t + V dsat, whee V t is tansisto theshold voltage and V dsat is the minimum V DS to keep the tansisto in satuation egion. Hence, it has V out,min = V t + V dsat. The wide-swing cascode topology educes V C level to V t + V dsat and subsequently deceases V out,min to V dsat. The gate egulated topology uses an amplifie to fom a negative feedback loop that stabilizes M dain voltage to enhance out. Its V out,min is also about V dsat due to stacked tansistos M and M 3. In addition to the effots to boost out, othe techniques have been developed to impove the CM input and output cuent matching [9, ] o to educe the equied voltage level at CM input nodes [, 0]. Nevetheless, these techniques still assume the cascode stuctue and hence cannot futhe educe V out,min below V dsat. Fig. Techniques to impove CM output esistance Besides the afoementioned cascode stuctue, thee is an altenative appoach to impove CM out as shown in Figue (b). In the figue, the output banch mio tansisto is modeled by an ideal tansisto M in paallel with tansisto output esistance o. I o, the cuent flowing though o vaies accoding to the CM output voltage. If a compensation cuent I C, which accuately tacks I o, is added to the CM input banch, then the CM output cuent I out will not be affected by the vaiations of the CM output voltage. This method is efeed to as cuent compensation technique in the pape. Since this appoach does not equie stacked tansistos in its output banch, its V out,min can be educed below V dsat, making it moe appealing in low-voltage design. A CM cicuit with cuent compensation technique is shown in Figue (c) [4, 7, ]. It uses an amplifie to keep the dain voltages of M and M at the same level. If M and M ae matching devices and have the same output esistance, the cuents due to the finite output esistance of M and M accuately tack each othe. Hence, the cicuit manifests high out and has V out,min aound V dsat. Once the output voltage is below V dsat, M and M ente linea egion and the cicuit loses its effectiveness to keep the dain potentials of the mio tansistos equal. Note that this cicuit contains a positive feedback loop (amplifie negative input and M ) and a negative feedback loop (amplifie
positive input and M ). To make it stable, the impedance at its input node should be lage than that at its output node. A detailed stability analysis fo this type of CM cicuits is discussed in []. Due to the amplifie feedback, the cicuit copies its output node voltage to its input node. To achieve high out and wide voltage swing, its input node should have high impedance and wide swing as well. Such constaints complicate the design of its input souce and limit its applications. The CM cicuits in [3, 0] implement simila cuent compensation schemes and avoid the above constaints by using cascode stuctue in the CM output banch. Howeve, this inceases CM V out,min to V dsat level, making them unsuitable in ulta-low voltage applications. Table Output esistance and compliance voltage compaison Types of CM cicuits out V out,min Simple CM cicuit o V dsat Classical Cascode CM g m o V t + V dsat Wide-swing Cascode g m o V dsat Gate-egulated Cascode [8] Ag m o V dsat Low-voltage Wilson CM [6] g m o V dsat CM Cicuit in [5] g m o 3 > V dsat Cuent compensation CM cicuit in [4, 7] in * Pop. high-pefom CM cicuit A o < V dsat Pop. ORBCM cicuit o4 o o4 o V dsat * in is the impedance obseved at the input node of the CM cicuit. The cicuit in [4,7] has a negative output esistance. Table summaizes the achievable out and V out,min of vaious CM cicuits. In the table, g m and o denote tansisto tansconductance and output esistance; A is the gain of the amplifie used in the design. Clealy, the V out,min of CM cicuits with the stacked stuctue is about V dsat o above, with the exception of the cicuit in [5], in which one of the stacked tansistos opeates in linea egion. Meanwhile, the cuent compensation based CM cicuits in [4, 7] educe V out,min to V dsat level, but suffe fom seveal limitations as discussed ealie. This pape pesents two low-voltage cuent compensation based CM cicuits whose out and V out,min ae listed in the last two ows of the table. The fist design, efeed to as high-pefomance CM cicuit, emphasizes on pushing V out,min to an extemely low level that is aound 0mV. Unlike the pevious low-voltage CM cicuit [4, 7], the poposed design does not equie the CM input node to have high impedance and wide swing. The second design, efeed to as output esistance boosted simple CM cicuit (ORBCM), stesses minimizing the implementation cost. It equies only one additional tansisto but significantly boosts out compaed to a simple CM cicuit. Both cicuit analysis and simulations ae pesented to discuss thei design consideations and to demonstate thei supeb pefomance. The est of the pape is oganized as follows. Section descibes the poposed high-pefomance CM cicuit. Its output esistance and stability ae also discussed in this section. The ORBCM cicuit and its design consideations ae pesented in Section 3. Cicuit simulation esults ae pesented in Section 4 and the pape is concluded in Section 5. V dsat II. Poposed high-pefomance cuent mio cicuit The poposed high-pefomance CM cicuit is shown in Figue. It uses a feedback loop consisting of amplifie A and tansisto M to ensue NMOS mio tansistos M and M 4 have the same dain voltage. Thus, the CM output I out pecisely tacks I DS4. Meanwhile, anothe feedback loop compised of amplifie A, tansistos M 4, M and M 3 foces PMOS mio tansistos M 3 and M 5 to have the same dain potential, esulting in I DS3 = I DS5. Since I DS3 = I in and 3
I DS4 = I DS5, we have I out = I in. To futhe illustate how the input and output cuent elation is enfoced by the feedback loops in a dynamic manne, we assume V out inceases by ΔV. Then the output of amplifie A inceases and so does V DS4. This momentaily causes I DS4 to incease, mainly due to the finite output esistance of M 4 with the assumption that M 4 gate voltage V G is not affected yet. The incease on I DS4 is then passed to I DS3 and subsequently causes M 3 gate voltage V C to decease. As a esult, amplifie A deceases M and M 4 gate voltage V G to settle the cicuit into a new stable state. Thus, the mechanism to ealize cuent compensation can be summaized as follows. When V out inceases, so does cuent I o, the cuent flowing though M output esistance o. The feedback system educes the gate voltage of M such that the cuent eduction due to deceased V G compensates the incease on I o. Fig. Poposed high-pefomance CM cicuit Fig. 3 Small signal model of the poposed CM cicuit The small signal model of the poposed cicuit is shown in Figue 3. Note that fequency compensation capacitos C ~3 in Figue ae not included in the small signal model. As detailed in Appendix A, the out of the poposed cicuit can be deived as: 4
out = o ( o + g m (A + ) + g mb ) ( o4 g m g m A A ( + g m5 05 ) + g m3 o4 + g m4 o4 A ( + g m5 05 o3 )) + o3 + g m3 + o () whee A and A denote the gain of amplifies A and A. If A is lage, the above equation can be appoximately simplified as: out A o () The poposed cicuit has seveal advantages ove the pevious designs [4, 7]. Fist, mio tansistos M and M 4 ae not diectly contained in the feedback loop that contols thei dain potential. Thus, even if M and M 4 leave satuation egion, the feedback loop can still keep thei dain voltages at the same level, which allows V out,min of the poposed cicuit to be educed below V dsat. Second, the poposed cicuit does not copy the output voltage level to its input node and hence eliminates the equiements of high impedance and wide swing fo its input node. This simplifies the CM input diving cicuit design and impoves cuent matching. Since the poposed cicuit contains seveal feedback loops, stability is an impotant design concen. Fist, compensation capacitos C ~3 ae used to impove the phase magin of the afoementioned negative feedback loops. These capacitos also pefom fequency compensation fo amplifies A and A. Second, thee is a positive feedback loop compised of the positive input of amplifie A, tansisto M, the positive input of amplifie A, and tansisto M. As shown in Appendix B, its open loop gain G OL can be deived as: G OL ( A + A ) ( + g m5 o5 ) g m( o L ) o4 g A m3 + ( + g m5 o5 ) g (3) m4 g A m3 whee L epesents the CM cicuit output load esistance. Since g m = g m4, o = o4, A, and ( + g m5 o5 ) g m4 A g, the above equation can be simplified as: m3 G OL o L o4 < This indicates that the positive feedback loop gain is always smalle than and hence it does not undemine the stability of the poposed cicuit. (4) III. Output esistance boosted simple cuent mio cicuit The poposed ORBCM cicuit stives to impove CM output esistance with minimized hadwae ovehead. Compaed to the simplest CM cicuit in Figue 4 (a), the poposed cicuit depicted in Figue 4 (b) equies only one additional tansisto M 3. It implements compensation cuent I C by taking advantage of the output esistance of the CM diving device M 4. Also, tansisto M 3 functions as a souce followe, thus the dain potential of M 4 tacks the voltage vaiation at the output node. Assuming V out expeiences a change of ΔV, then the cuent flowing though the output esistance of M changes by ΔV o. Meanwhile, ΔV is popagated to the dain teminal of M 4 since V GS3 is constant thanks to the elatively stable I DS3. Thus, the change on the cuent flowing though the output esistance of M 4 is ΔV o4. If o = o4, compensation cuent I C will completely cancel the vaiation on the cuent flowing though the output esistance of M, thus boosting the output esistance of the CM cicuit. The small signal model of the ORBCM cicuit is shown in Figue 4 (c). As descibed in Appendix C, its output esistance can be deived as: 5
out = g m3 g m o3 o [ o3 + o4 + o3 o4 (g m3 + g mb3 )] [ + g m ] + o If g m = g m, g m and g m3 g mb3, the above expession can be simplified as: o o4 o (6) out = o4 o o o4 It shows that out can be significantly impoved if o o4. Since M and M 4 ae diffeent types of tansistos, achieving exact matching between o and o4 may not be ealistic. Howeve, as long as o and o4 ae easonably close, the poposed CM cicuit will have much highe out than the simple CM cicuit and this is achieved with using only one additional tansisto. Although pocess vaiations will affect the matching between o and o4, simulation esults demonstate that the poposed design etains its high out advantage at the pesence of pocess vaiations. Finally, if o > o4, the ORBCM cicuit will manifest a negative output esistance, which can be toleated in vaious applications, e.g. the CM cicuit functioning as the tail cuent souce of diffeential amplifies. Howeve, if a negative esistance is undesiable, o4 can be designed to be lage than o with adequate design magin. (5) Fig. 4 Poposed ORBCM cicuit and its small signal model The ORBCM cicuit also contains a positive feedback loop compised of two stages. The fist stage is a souce degeneated common souce (CS) amplifie with M 3 as the amplification device and diode-connected M as the active load. The second stage is the CS amplifie with amplification device M. Assume L is the load esistance at the ORBCM cicuit output. The loop gain of the positive feedback can be deived as: G OL g m o4 g m ( o L ) o L o4 < Theefoe, the positive feedback will not cause instability in pactical applications. (7) IV. Cicuit simulation esults The two poposed cicuits ae designed using a 0.3µm CMOS technology and opeate with a single.v powe supply. Cicuit simulations show that the poposed high-pefomance CM cicuit can simultaneously achieve high out and exteme low V out,min that is about 0mV. Its stability is also validated by simulation esults. Fo the ORBCM cicuit, simulation esults demonstate that it impoves out by moe than 0 times compaed to a simple CM cicuit. 6
Simulations ae also conducted to study the impact of pocess vaiations and to demonstate the advantages of using the ORBCM cicuit in amplifie design. A. Poposed high-pefomance CM cicuit In the design of the poposed high-pefomance CM cicuit, two-stage topologies ae used fo amplifies A and A to achieve modeate gain and elatively lage output swing. If the mio tansistos have lage size, the amplifie output swing equiement will be elaxed and, subsequently, single-stage diffeential amplifies can be used. The amplifie schematics ae given in Figue 5 and the types of amplifie input devices ae selected based on thei common mode input ange equiements. Tansisto sizes used in the design ae listed in Table and the compensation capacitos ae selected as: C = 0. pf, C = 0. pf, and C 3 = 0. pf. The attained gains fo amplifies A and A ae 3 and 4, espectively. The CM cicuit is designed fo an output cuent of 6 µa. Fig. 5 Amplifie cicuits used in the high-pefomance CM cicuit Table Tansisto sizes of the high-pefomance CM cicuit Device Channel width/ length Device Channel width/ length M, M4 3μm/0nm M 540nm/360nm M.44μm/0nm M3 600nm/0nm M5, M3 600nm/0nm M4, M5 40nm/0nm M6, M7 600nm/0nm M6, M7 3μm /0nm M8, M9 360nm/0nm M8 80nm/0nm M0 30nm/0nm M9.6μm/360nm M 540nm/0nm C/C/C3 0./0./0. pf Fo compaison puposes, the CM cicuits in [4, 5] ae also designed and simulated using the same CMOS technology. The schematic of the cicuit in [4] is shown in Figue (c). It uses the same mio tansisto sizes as that of M and M 4 in the poposed design and amplifie A is used in the feedback loop. The tansisto sizes of the cicuit in [5] ae selected following the techniques in [5] with tageted output cuent of 6 µa. Figue 6 plots the output cuents of the thee CM cicuits. If the compliance voltage is selected as the output level at which the output cuent diffes fom the ideal value by %, the compliance voltages of the poposed cicuit and the designs in [4] and [5] ae 0 mv, 53mV, and 7 mv, espectively. The elative cuent eos of the thee cicuits ae plotted in Figue 7. It shows the thee designs appoximately achieve the same level of accuacy. With a KΩ load esistance, simulations ae also pefomed to compae the noise pefomance of the thee cicuits. The output white noises of the poposed cicuit and the designs in [4] and [5] ae 6.43 pa/ Hz, 6.6 pa/ Hz and 5.3 pa/ Hz, espectively. It shows the poposed technique does not significantly affect the noise pefomance of the CM cicuit. 7
Fig. 6 Output cuents of the poposed high-pefomance CM cicuit and efeence designs in [4, 5] Fig. 7 Relative output cuent eos of the poposed high-pefomance CM cicuit and efeence designs in [4, 5] Fig. 8 Simulated open loop gain of the positive feedback path Figue 8 shows the simulated open loop gain G OL of the afoementioned positive feedback path. In simulation, the loop is cut at amplifie A positive input, to which an AC signal is injected fo AC analysis. The diffeential amplifie depicted in Figue 0 seves as the load of the CM cicuit in simulation. Due to the small load esistance L, G OL is below -0dB. Using an active load with an output esistance simila to that of M, G OL is still below -6dB, which confims the stability analysis in Section II. 8
B. Poposed ORBCM cicuit Both the poposed ORBCM cicuit and the simple CM cicuit in Figue 4 (a) ae designed with I out = 6 μa. The two cicuits have the same tansisto sizes, as shown in Table 3, and only diffe by that the ORBCM cicuit has an exta tansisto M 3. The simulated output cuents of the two cicuits ae compaed in Figue 9. Clealy, the output cuent of the ORBCM cicuit is much moe stable and the two cicuits appoximately have the same V out,min, which is about the level of V dsat. When the output voltage is at 600mV, the out of the ORBCM and simple CM cicuits ae 3.5MΩ and 30kΩ, espectively. This epesents times impovement by the poposed technique. Simulation also eveals that o = 380 KΩ and o4 = 45 KΩ in the afoementioned conditions. Accoding to Equation 6, out of the ORBCM cicuit is about 4.5MΩ, which is easonably close to the value obtained fom simulation. Table 3 Tansisto sizes of the cuent mio cicuit Device Channel width/ length M, M.um/360nm M3 4.8um/0nm M4 9.6um/40nm Fig. 9 Output cuent of the simple CM and ORBCM cicuit; a: simple CM cicuit; b: ORBCM cicuit Since the out of the ORBCM cicuit stongly depends on the matching between o and o4, Monte Calo (MC) simulations ae conducted to study how pocess vaiations and device mismatches affect the poposed technique. The histogam of the ORBCM out fom 000 MC simulations is shown Figue 0. Note that the thee lagest out values, 66MΩ, 68MΩ and 605MΩ ae significantly highe than the est of the values and ae not included in the plot in ode to avoid ovestetching the x-axis of the plot. The out mean and standad deviation values ae 4.3MΩ and.8mω, espectively. This shows that out has a wide distibution. In many scenaios, the equiement fo CM output esistance is to be lage than, athe than tacking, a taget value. Thus, the wide out distibution can be toleated as long as the majoity of the distibution is lage than the taget value. The minimum out obtained fom the 000 MC simulations is 980KΩ, which is still.5 times lage than the output esistance of the simple CM cicuit. Also, 99% of the obtained out values ae lage than.5mω, which is almost fou times of the output esistance of the simple CM cicuit. This demonstates that the poposed technique emains effective at the pesence of pocess vaiations and device mismatches. With a K load esistance, the output white noise of the ORBCM and simple CM cicuits ae 5.4 pa/ Hz and 5.6 pa/ Hz, espectively. Simulations ae also conducted to show the CMRR (common mode ejection atio) of a diffeential amplifie can be impoved by using the ORBCM cicuit as its tail cuent souce. The amplifie schematic and its tansisto sizes ae shown in Figue. Fo compaison puposes, both the ORBCM cicuit and simple CM cicuit ae used in the study. Figue compaes the obtained CMRRs at a common mode input level of 600mV. It shows that about 8dB impovement, fom 53dB with the simple CM cicuit to 7dB with the ORBCM cicuit, is achieved by adding only one exta tansisto in the design. 9
Fig. 0 Histogam of the ORBCM cicuit out Fig. Amplifie design fo CMRR compaison Fig. : Amplifie CMRR using the ORBCM o the simple CM cicuit as its tail cuent souce 0
V. Conclusions This pape pesents two low-voltage CM cicuit designs using cuent compensation techniques to impove CM output esistance. Unlike most existing CM cicuits that ely on stacked tansistos in the output banch to stabilize the dain potential of the output device, the poposed cicuits place only one tansisto in thei output banches, which helps educe output compliance voltage. In the fist poposed cicuit, amplifie based feedback loops ae used to achieve cuent compensation. Additionally, the mio devices ae not contained in the citical path of the feedback, allowing the mio devices to opeate in deep linea egion without significantly affecting the effectiveness of the feedback loops. This enables the poposed design to achieve extemely compliance voltage at the level of 0 mv, which to ou knowledge is the lowest compliance voltage of any implementation epoted in liteatue. In the second design, the cuent compensation is achieved by copying the voltage vaiations at the CM Output node to its input node and matching the output esistance of the output device with the output esistance of its dive cicuit. This design only equies one addition tansisto compaed to a simple CM cicuit but can significantly impove CM output esistance. The effectiveness of the poposed design at the pesence of pocess vaiation and device mismatches is veified via MC simulations. Thanks to thei low compliance voltage and high output esistance, the poposed designs ae suitable fo vaious low-voltage applications. Refeences. J. Ramiez-Angulo, R. G. Cavajal and A. Toalba, "Low supply voltage high-pefomance CMOS cuent mio with low input and output voltage equiements," IEEE Tansactions on Cicuits and Systems II: Expess Biefs, vol.5, no.3, pp.4-9, Mach 004. A. Zeki and H. Kuntman, "Accuate and high output impedance cuent mio suitable fo CMOS cuent output stages," Electonics Lettes, vol.33, no., pp.04-043, 5 Jun 997 3. T. Itakua and Z. Czanul, High output-esistance CMOS cuent mios fo low-voltage applications, IEICE Tans. Fundam., vol. E80-A, no., pp. 30 3, Jan. 997. 4. F. You, S. H. K. Embabi, J. F. Duque-Caillo and E. Sánchez-Sinencio, An impoved cuent souce fo low voltage applications, IEEE J. Solid-State Cicuits, vol. 3, pp. 73 80, Aug. 997. 5. L. F. Tanguay, M. Sawan and Y. Savaia, "A vey-high output impedance cuent mio fo vey-low voltage biomedical analog cicuits," Poc. IEEE Asia Pacific Confeence on Cicuits and Systems, pp.64-645, Nov. 30 008-Dec. 3 008. 6. B. A. Minch, "Low-Voltage Wilson Cuent Mios in CMOS," Poc. IEEE Intenational Symposium on Cicuits and Systems, pp.0-3, 7-30 May 007. 7. F. You, S. H. K. Embabi, J. F. Duque-Caillo and E. Sanchez-Sinencio, "An impoved cuent souce fo low voltage applications," Poc. IEEE Custom Integated Cicuits Confeence, pp.97-00, 5-8 May 996. 8. E. Sackinge and W. Guggeuhi, A high-swing, high impedance MOS cascode cicuit, IEEE J. Solid State Cicuits, vol. 5, no., pp. 89-98, 990. 9. G. Palmisano, O. Palumbo and S. Pennisi, High lineaity CMOS cuent output stage, Electon. Lett. vol. 3, no. 0, pp. 789-790, 995. 0. V. Peluso, P. V. Coeland, M. Steyaet and W. Sansen, 900 mv diffeential class AB OTA fo switched op-amp applications, Electon. Lett. vol. 33, no. 7, pp. 455 456, 997.. E. Seevinck, M. du Plessis, T. Joubet and A. Theon, "Active-bootstapped gain-enhancement technique fo low-voltage cicuits," IEEE Tans. Cicuits Syst. II, vol.45, no.9, pp.50-54, Sep 998. T. Seano and B. Linaes-Baanco, The active-input egulated cascode cuent-mio, IEEE Tans. Cicuits Syst. I, vol. 4, no. 6, pp. 464 467, June 994.
Appendix A This appendix deives the output esistance of the poposed high-pefomance CM cicuit. Fom the small signal model shown in Figue 3 we have: I c = V C V D o I out = V out o + g m V G I c = V D o4 + g m4 V G + g m (V A V D ) g mb V D I c = V C o3 g m3 V C (8) (9) (0) () V A = (V out V D )A () V G = V C ( + g m5 ( 05 in ))A = (V C V R )A (3) Assuming in 05, V G can be appoximated by: Fom the above equations, I out can be solved as: I out = V out o Thus, out = o V G = V C ( + g m5 05 g m g m A A ( + g m5 05 ) V out ( + g m (A + ) + g mb ) ( o4 o + g m3 o4 + g m4 o4 A ( + g m5 05 o3 )) + + g m3 + o3 ( o + g m (A + ) + g mb ) ( o4 ) A g m g m A A ( + g m5 05 ) + g m3 o4 + g m4 o4 A ( + g m5 05 o3 o )) + o3 + g m3 + o (4) (5) (6) Appendix B This appendix deives the open loop gain of the positive feedback path in the poposed high-pefomance CM cicuit. Assuming V GS is appoximately constant, V D can be appoximated by: V D = ( A + A ) V A+ whee V A+ is the non-inveting input of amplifie A. Also, V C as a function of V D and V G can be appoximated by: (7) V C = V D o4 g m3 V G g m4 g m3 (8) whee V G is given in Equation 4. Fom Equations 4, 7, 8, we can solve V G as:
V G = V A+ ( o4 g A ) m3 + A ( + g m5 05 + g m4 ) A g m3 Finally, tansisto M and the CM load with output esistance L fom a common souce amplifie with the gain of g m ( o L ). Thus, the open loop gain defined as G OL = V out is: V A + G OL ( A + A ) ( + g m5 o5 ) g m( o L ) o4 g A m3 + ( + g m5 o5 ) g m4 g A m3 (9) (0) Appendix C This appendix deives the out of the ORBCM cicuit. Fom the small signal model in Figue 4 (c), we have: I out = V out o + g m V I c = V o + g m V I c = V V o3 + g m3 (V out V ) g mb3 V () () (3) I c = V o4 (4) Solving fo I out fom the above equations and subsequently fo out we find the expession: out = g m3 g m o3 o [ o3 + o4 + o3 o4 (g m3 + g mb3 )] [ + g m ] + o (5) 3