Data Logger by Carsten Kristiansen Napier University. November 2004

Data Logger by Carsten Kristiansen Napier University November 2004

Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Data Logger. Education: Electronic and Computer Engineering. Module: Engineering Applications SE32101. Place of education: Napier University Edinburgh 10 Colinton Road Edinburgh EH10 5DT Lecturer: Dr. T.D. Binnie. Assignment period: 2. November 2004-14. January 2005.

1. Abstract This report describes how an data logger are designed and simulated. The data logger must memorise a analogue signal from an electrical model of an ultrasonic transducer, where the values must be presented visually at a display. These values are be stored when the memory has been triggered from a digital sequence. The data logger are designed in blocks, where each block are simulated individually. This reaches a complete circuit and conclusion of the data logging system.

Contents 1. Abstract... 4 2. Introduction... 6 2.1. Analogue source...6 2.2. Digital source... 7 3. Assignment specifications... 8 3.1. Block diagram... 8 4. Amplifier...9 4.1. Calculations...9 4.2. Simulation of the instrumentation amplifier... 11 4.3. Offset correction... 12 4.4. Offset calculations...12 4.5. Simulation of the amplifier... 13 5. Sequence detector... 15 5.1. State diagram:... 15 5.2. State table:... 15 5.3. State assignment:... 16 5.4. Next state logic... 16 5.5. Simulation of the sequence detector... 17 6. Counter...18 6.1. Counter setup:...18 6.2. Simulation of the counter...19 7. A/D converter...20 7.1. Simulation of the A/D converter... 20 8. Memory and display...21 8.1. Memory...21 8.2. Display... 21 8.3. Simulation of the memory and display... 22 9. Schematic of the data logger...23 9.1. Schematic of the data logger using macros...24 10. Conclusion... 25 11. References...26 11.1. Internet...26 11.2. Literature...26 11.3. Software tools...26

Data Logger Carsten Kristiansen Napier No.: 04007712 2. Introduction The assignment of the design and simulation of this data logger, are done by designing each block for itself, simulating these individually which in the final stage will lead to a complete data logging system. With the use of the TINA Pro software, the circuits and simulations can be carried out. The design procedure for this is to build each of the circuits, simulate their behaviour and then save them individually as macros. The electrical models of the Analogue and digital sources that are used for the assignment are analysed below. 2.1. Analogue source The analogue source is a predefined part of the assignment, which is the electronic model of a ultrasonic transducer. The figure 1 below illustrates the schematic symbol of the analogue source. The output is connected to an impedance meter which in the simulation will measure the output impedance of the analogue source. U1 Analogue Source Vs + Z ZM1 Output Vs 10u T Fig. 1: Analogue Source -10u 50u 1.00m 1.50m 2.00m Time (s) Fig. 2: Analogue source simulation result The impedance are in the simulation measured to be 159,69Ω, which should be taken in consideration when the amplifier circuit are designed, because it can have a great effect on the input of the amplifier as a load resistance. A good solution for this can be by using an instrumentation amplifier for the analogue signal. As the simulation result in figure 2 illustrates, the signal from the analogue source has a amplitude of ±100μV. After a period of 400μS, the analogue source will generate a square signal with a time period of 400μS. This will give a frequency of 1 =2,5 khz. 400 6 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 2.2. Digital source The digital source has two independent outputs, one that is a serial digital test source (Signal) which generates the sequence 1011. The other output is a clock source (Clock), which generates a clock signal for the following sequence detector. U1 Digital Source Signal Clock Signal out Clock out Fig. 3: Digital source T H Clock out L H Signal out L 5u 10u 15u 20u Fig. 4: Digital source simulation result Time (s) The clock in the digital source as shown in figure 4 generates a square signal with a period of 10μS, 1 which gives a frequency of 10 =100kHz. The generation of the signal out, illustrates the serial sequence 1011. Napier University Edinburgh 7

Data Logger Carsten Kristiansen Napier No.: 04007712 3. Assignment specifications The first part is to design an analogue amplifier for the transducer signal. The source transducer is non-ideal it has a finite bandwidth and an internal impedance. The signal from the transducer has a peak voltage of ~100µV. The 8-bit analogue-to-digital converter to be used for the system has a maximum input voltage level of 1,02V which will produce the maximum output of 11111111. The transducer signal must be amplified to match the input of the analogue to digital converter. The transducer signal has to be converted and captured and stored in a digital memory when triggered by a digital source. Specifically, when the serial digital data sequence 1011 is received three times from an external source, then the analogue transducer signal will be captured and stored in a memory. The digital bit rate is 100kHz. The circuit will count the number of individual (non-overlapping) sequences up to a value of three. At this value it will trigger the analogue-to-digital converter and the memory storage. Use TINA simulation package to design and simulate a non-ideal mixed signal data logging circuit which records a digital representation of the analogue output from an ultrasonic transducer. 3.1. Block diagram From the specifications a general block diagram can be presented. The block diagram below in figure 5 indicates what the desired options for the assignment are. Analogue Source Amplifier A/D Converter Memory Display Digital Source CLK Sequence Detector CLK Counter Fig. 5: Data Logger block diagram 8 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 4. Amplifier For amplification between the analogue source and the A/D converter, an instrumentation amplifier circuit are used. This type of amplifier can amplify a very low input voltage to a desired output voltage with a low noise level. The figure 6 below, illustrates how the general instrumentation amplifier looks like. Look aside from the component values, which will be calculated. The OP-amp chosen for the circuit is the TL074 from Texas Instruments. This chip consists of 4 single, low noise OP-amps, which can be supplied with a ± voltage. The supply voltage which will be used for the amplifier is ±12V. R4 1k Input V+ + OP1 TL074 + - V- R1 1k R3 1k V- - + + OP3 TL074 V+ Output R5 1k R7 1k - V- R2 1k R6 1k + + OP2 TL074 V+ Fig. 6: General instrumentation amplifier circuit With this circuit, the values of the resistors has to be calculated from some chosen requirements, which is the amplification of the OP-Amp's. In the first part that includes the OP1 and OP2 the amplification are chosen to be high compared to the amplification with OP3. This is desired to use the excellent qualities of the Common Mode Rejection Ratio (CMRR), that the OP-Amp's can provide. But first it is needed to calculate how great the amplification between the input/output must be. 4.1. Calculations Known: U in =±100 V U out max =1,02V Total amplification: A u total = U out max = 1,02 U in 200 =5100 V / V The total amplification are then split up so that the first part which is OP1 and OP2 provides an amplification of 100 V / V, and the second part with OP3 is set to 51 V / V. Napier University Edinburgh 9

Data Logger Carsten Kristiansen Napier No.: 04007712 Chosen: R1=100 k R2=R1 A u1 =100 V / V R3=10 k R6=R3 A u2 =51 V / V R7 is calculated: A u1 =1 2 R2 R7= 2 R2 R7 A u1 1 = 2 100 k 100 1 R7=2,02 k~2 k (E12 value) Due to tolerance variations of the resistors the value of R7 are changed to 1,8kΩ, and a potentiometer (P1) with a value of 470Ω is inserted in series, so if the circuit where to be build practically, it would be possible to adjust the amplification to the precise value that is needed. The potentiometer is inserted in a way, so that if the glider should attempt to stop working, the instrumentation amplifier would still work, but with a difference in the amplification. The adjustable area of the amplification resistance (R7+P1) will be from 1,8kΩ to 2,27kΩ. The minimum to maximum relationship of the amplification with the potentiometer inserted are calculated below. Minimum to maximum amplification of OP1 and OP2: A u1 min =1 2 R2 =1 2 100 k R7 P1 max 1,8 k 470 ~ 88V / V A u1 max =1 2 R2 =1 2 100 k R7 P1 min 1,8 k 0 ~ 111V / V R3 is calculated: A u = R4 R3 R4=A u R3=51 10 k R4=510 k -And R5 = R4 (E24 value) Voltage output calculations: The output voltage of the instrumentation amplifier, can with the values of the resistors and the input voltage from the analogue source now be calculated. The calculated voltages below are the ideal (the resistor R7 and the potentiometer P1 has a total value of 2,02kΩ), the minimum and the maximum output voltages with the P1 potentiometer inserted. U out ideal = U OP1+ U OP2+ 1 2 R2 R4 R7 P1 ideal R3 = 200 0 1 2 100 k 1,8 k 220 510 k 10 k =1,0201V U out min = U OP1+ U OP2+ 1 2 R2 R4 R7 P1 max R3 = 200 0 1 2 100 k 1,8 k 470 510 k 10 k =0,9089V U out max = U OP1+ U OP2+ 1 2 R2 R4 2 100 k = 200 0 1 R7 P1 min R3 1,8 k 0 510 k 10 k =1,1435V 10 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 4.2. Simulation of the instrumentation amplifier The instrumentation amplifier with the calculated values above are simulated with the ideal values where the potentiometer P1 are in its ideal position, which is at 220Ω. The figure 7 below illustrates the simulation circuit of the instrumentation amplifier, with the analogue source connected to the input. U1 Analogue Source Vs Input V+ + OP1 TL074 + - V- R1 100k R3 10k R4 510k V- - + + OP3 TL074 V+ Output R7 1,8k R5 510k P1 470 R6 10k - V- R2 100k + + OP2 TL074 V+ Fig. 7: Instrumentation amplifier simulation circuit T 20u Input -20u 60m Output -60m 50u 1.00m 1.50m 2.00m Time (s) Fig. 8: Instrumentation amplifier simulation result The simulation output of the instrumentation amplifier indicates that the output are phase shifted 180 degrees compared to the input as shown in figure 8 above, because of the inverting amplifier OP3. The output voltage derived from the simulation in TINA has a peak to peak value of -507,42mV to 538,23mV. The absolute voltage on the output are the two voltages added together which gives a value of 1,045V. Napier University Edinburgh 11

Data Logger Carsten Kristiansen Napier No.: 04007712 4.3. Offset correction As illustrated in the figure 8 with the simulation of the instrumentation amplifier the voltage level of the output are not as desired from 0V to 1,02V, which can be adjusted to the right level by inserting another amplifier on the output of the OP3. The amplifier used for this is an inverting amplifier where there is used offset voltage on the positive input. There are more advantages of inserting this amplifier, than the offset correction. The input to output phase shift of the complete amplifier will be 0 degrees, and since it is a TL074 that is being used for the circuit, all of the OP-amps in the package will be used. If the amplifier where to be build in practical, this would be a preferred choice of use, considering temperature and component variations. The general circuit for the offset correction is illustrated below in figure 9. The values of the resistors will be calculated. R9 1k Input R8 1k V+ - V- + + OP4 TL074 Output R10 1k V+ P2 1k R11 1k Fig. 9: Offset correction circuit 4.4. Offset calculations Known: U out min =507,42 mv Chosen: A u =1 V / V R8=R9=10 k R10=1 k Offset voltage are calculated: U offset = U out min A u 1 =507,42 m =253,71 mv 2 12 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger R11+P2 are calculated: R11 P2=R10 V+ 1 =1 k U offset 12 253,71 m 1 =46,298 k R11 are chosen to be 33kΩ, where the potentiometer P2 then can be calculated to be: P2= R11 P2 R11 chosen =46,298 k 33 k=13,298 k ~ 15 k (E12 value) With the potentiometer P2 adjusted to the correct value of 13,298kΩ, the output should be able to deliver an approximate voltage from 0 to 1,02V. 4.5. Simulation of the amplifier The complete circuit of the amplifier are illustrated in the figure 10 below. The amplifier are simulated with the analogue source on the input. The potentiometers P1 and P2 are adjusted to the correct values as calculated previously to get the best performance of the amplifier. U1 Analogue Source Vs Input V+ + OP1 TL074 + - V- P1 470 R3 10k R1 100k R7 1,8k R6 10k R4 510k V- - + + OP3 TL074 V+ R5 510k R8 10k V+ P2 15k R9 10k V- - + + OP4 TL074 V+ Output R11 33k V- - R2 100k R10 1k + + OP2 TL074 V+ Fig. 10: Amplifier simulation circuit Napier University Edinburgh 13

Data Logger Carsten Kristiansen Napier No.: 04007712 Transient analysis of the amplifier: T 10u Input -10u 1.00 Output 50u 1.00m 1.50m 2.00m Fig. 11: Transient simulation result of the amplifier Time (s) From the figure 11 above the transient simulation result of the amplifier indicates that the phase shift between the input to output are 0 degrees, and the output voltage levels are as desired. The levels are measured to be from -30mV to 1,01V. However the following A/D converters analogue input will only display levels from 0V to 1,01V digitally on the output. AC transfer analysis of the amplifier: T Input -2 8 Output 4 10 100 1k 10k 100k Fig. 12: AC transfer simulation result of the amplifier Frequency (Hz) The AC transfer simulation of the amplifier shows the best working condition of the amplifier in frequency vs. Gain. Note that the best results of the gain can be derived at frequencies between 200Hz to 3kHz. 14 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 5. Sequence detector With the digital source at the input, the sequence detector has to detect at the serial digital sequence 1011. By using D-type Flip-Flops a circuit for the detector can be designed. The output of the Flip- Flops must be added together which will give a detect signal at the output. 5.1. State diagram: The state diagram can give a good overview at the functions that is desired in the sequence detector. There are 4 bits in the sequence 1011, which are put into the diagram below in figure 13. The A to D indicates each of the stages of the 4 bits, where E is the output that has to be set to a logical high when the sequence 1011 is received. Fig. 13: Sequence detector state diagram 5.2. State table: From the state diagram the functions of the sequence detector can be derived and written into a state table as shown below. The table shows the present and next state logic, which are used for the D- type Flip-Flops, where the x +, y + and z + are the inputs on the Flip-Flops. Din are the data-input on the Flip-Flops. State table Present Next state x + y + z + Din = 0 Din = 1 A A B B C B C A D D C E E A B Output Napier University Edinburgh 15

Data Logger Carsten Kristiansen Napier No.: 04007712 5.3. State assignment: To minimize faults in the sequence, there will be used gray code for the present state in the state assignment table as shown below. To find the next state logic, the common known state table for the D-type Flip-Flop have been used. State assignment State Present Next state x + y + z + x y z Din = 0 Din = 1 A 000 000 001 B 001 011 001 C 011 000 010 D 010 011 110 E 110 000 001 Detect 5.4. Next state logic By deriving the next state logic from the state assignment table, it can be written into Karnaugh maps. For each of the 3 outputs there are made a map, where the logical gates for the sequence detector can be found. y z Din x 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 X X X 0 1 1 X X X 0 1 0 0 0 0 1 x + Output x + =Din x y z y z Din x 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 X X X 0 1 1 X X X 0 1 0 0 0 1 1 y + Output y + =Din x y z Din x y x y z y z Din x 0 0 0 1 1 1 1 0 0 0 0 1 0 1 0 1 X X X 0 1 1 X X X 1 1 0 1 1 0 0 z + Output z + =x y z Din x y z Din x y Din x y z 16 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger The expressions for each of the outputs have been tried reducing with boolean algebra, but the results could not make the use of gates for the circuit be more optimized than the expressions derived from the Karnaugh map, so the results from the Karnaugh maps are used for the design of the circuit. 5.5. Simulation of the sequence detector X Y Z U14 SN7404 U13 SN7421 U21 SN7421 U20 SN7411 U16 SN7411 U10 SN7421 U4 + U11 4075 + U6 U17 SN7421 U15 4072 U8+ U1 Din CLK D P Q X D P Q Y D P Q Z C Q U12 SN7411 C Q C Q + U5 + U7 + U9 U1 SN7474 U18 SN7411 U2 SN7474 U3 SN7474 Digital Source Signal Clock U19 SN7411 Detect Fig. 14: Sequence detector simulation circuit The sequence detector are simulated with the Digital source on the input to verify the correct output functions. The result of the digital timing analysis are illustrated below. T CLK 5.00 4.00 Detect Din X Y Z 5.00 4.00 4.00 4.00 10u 20u 30u Fig. 15: Digital timing analysis of the sequence detector Time (s) Napier University Edinburgh 17

Data Logger Carsten Kristiansen Napier No.: 04007712 6. Counter To read the detected sequence from the sequence detector every time there has been a correct sequence 3 times from the digital source, a counter is needed to trigger the memory. The counter that is chosen for this job is the SN74190, which is a 4 bit synchronous up/down BCD counter. The schematic symbol of the counter are shown below with a description of the pin connections. Pin connections: CTEN =Count enable control input D/U =Down/Up control line input CLK =Clock input LOAD= Load control line input A to D=4 bit data input lines M / m=maximum/ minimum count output RCO=Ripple clock output QA to QD=4 bit data output U22 SN74190 CTEN D/U CLK LOAD A B C D M/m RCO QA QB QC QD Fig. 16: Counter By examin the datasheet for the SN74190 counter from Texas Instruments, a circuit for the counter can be designed. The counter must count binary up to three from the previous detect signal, on the CLK input. When this is fulfilled, the counter needs to be reset again to zero and keep counting to three. The counter should at the binary number of three be able to give a logical high trigger signal at the output. 6.1. Counter setup: CLK :Connected to the clock detect output from the sequence detector. CTEN : Connected to ground - counter enabled. D/U : Connected to ground - counter direction up. LOAD :Connected to the output on the trigger gate through an inverter - counter resets when trigger output is high. A to D : Connected to ground - with a low level at the LOAD input, the counter are preset to 0000 on the data output lines. QA and QB : Connected to a AND-gate - when the counter reaches the binary number 3, the output on the AND-gate will give a trigger signal. 18 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 6.2. Simulation of the counter The counter is in the simulation connected to a 10kHz clock signal to verify its use. In the final circuit it is connected as described in the counter setup. The circuit used for the simulation of the counter are illustrated below in figure 17. U22 SN74190 U2 CLK CTEN D/U CLK LOAD A B C D M/m RCO QA QB QC QD U23 SN7408 Output U1 SN7404 Fig. 17: Counter simulation circuit T 5.00 CLK 4.00 Output 25u 50u 75u 1.00m Fig. 18: Transient simulation result of the counter Time (s) The counter will when running, deliver a trigger signal on every third of the clock ticks at the CLK input, except the first counting sequence where it will be at the fourth clock tick. This is because the counter is not reset when it starts counting, which means that when the first clock pulse arrives, the counter will count from binary zero to three. Napier University Edinburgh 19

Data Logger Carsten Kristiansen Napier No.: 04007712 7. A/D converter To convert the analogue signal from the amplifier to digital levels that can be used for the memory circuit, an A/D converter is inserted. The component that is chosen is a standard 8 bit A/D converter from TINA. The analogue input must be a voltage level from 0 to 1,02V, which at the outputs would deliver a 8 bit digital output from 0000 to FFFF. The reference voltage input on the converter are connected to ground. To verify the correct operations of the A/D conversion with the signal from the amplifier, a 8 bit digital to analogue converter are used for this purpose. 7.1. Simulation of the A/D converter 0 1 2 3 4 5 6 7 Input U1 U2 + U3 + VG1 A 0 7 0 7 E A R0 Ri Gnd Output Fig. 19: A/D converter simulation circuit The voltage generator are set to deliver a sinusoidal signal of ±510mV with a offset at 510mV, which will give a voltage level of 0V to 1,02V on the input of the A/D converter, that is similar to the output from the amplifier. 0T 1 2 3 4 5 6 7 Input 4.00 4.00 4.00 4.00 4.00 4.00 4.00 4.00 2.00 1.00 Output 20u 40u 60u Fig. 20: Transient simulation result of the A/D converter Time (s) 20 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 8. Memory and display The values from the analogue source that is amplified and converted to the 8 bit digital signal, needs to be stored in a memory device, and then displayed visually on a display device. The values from the memory can be viewed at the display by the use of addressing. 8.1. Memory The memory chosen for the data logger is a 8 bit static CMOS RAM (SRAM), which is a standard RAM component in TINA. This memory can be addressed from the hex values 00 to FF which gives a total memory allocation of 2048 bytes. To address the memory, the 12 bit binary counter 14040 is inserted in the circuit. The counter will be reset with a high level on the MR pin every time the counter has reached a decimal value of 2048. In the simulation of the memory and display, the output from the counter are connected to both the address and data input lines on the RAM. The clock signal used at the input on the counter are similar to the clock output from the digital source. The setup description below for the memory is the one used for the simulation. Memory setup: CS :Chip select=connected to ground - chip enabled. R/W : Read /Write=Connected to the clock - when a high level the memory reads data on the data input, when low the memory writes data on the data output lines. OD:Output Disable=Connected to ground - memory device enabled. 8.2. Display The display chosen for the data logger is an ascii display. This display has an 8 bit input an can display characters from common known ascii table as illustrated in figure 21. The table is only a small part of the complete ascii table, where the entire table can be found at the Internet address in the references. Fig. 21: Part of the ascii table Napier University Edinburgh 21

Data Logger Carsten Kristiansen Napier No.: 04007712 8.3. Simulation of the memory and display Fig. 22: Digital step by step analysis of the memory and display The figure above illustrates a running simulation of the memory and display, where the display receives a 8 bit digital signal of 01000010, which as a decimal number is 64. In the ascii table this number represents the character B, which the ascii display also indicates. CLK T DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 25u 50u 75u 1.00m Fig. 23: Digital timing analysis of the memory and display Time (s) 22 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 9. Schematic of the data logger Napier University Edinburgh 23

Data Logger Carsten Kristiansen Napier No.: 04007712 9.1. Schematic of the data logger using macros 24 Napier University Edinburgh

Carsten Kristiansen Napier No.: 04007712 Data Logger 10. Conclusion The design and simulation assignment of a data logger has been completed with some difficulty in the simulation part of the complete data logging system. It has been learned that the TINA simulation software surprisingly not where able to simulate the final and complete circuit of the data logger, which was a big disappointment, not to be able to see the final simulation results with the entire circuit. Different approaches where tried to figure out if it could be possible in some way to get a successful simulation result with the final schematic, but without any luck. By reading closely at the homepage of the TINA software it was found that the desired simulation was not possible. If the data logger where to be build in practical, the circuits could be reduced even further by the use of a microcontroller. This controller could be a PSoC mixed-signal controller from Cypress, which would be able to replace roughly all the circuits that has been designed for the system. There where some problems when the sequence detector where designed and simulated. It was at first tried setting up the present states in the state assignment table with binary code, which in the simulations didn't work, so instead the Gray code was used and the outcome of the simulations then where as expected. The assignment of designing the data logger has been a very interesting assignment, cause of the experiences it has given by the use of the TINA software, and the combination of both analogue and digital electronic. Carsten Kristiansen Napier University Edinburgh 25

Data Logger Carsten Kristiansen Napier No.: 04007712 11. References 11.1. Internet Instrumentation amplifiers, www.analog.com TL074, www.ti.com Counter SN74190, www.ti.com ascii table, www.asciitable.com 11.2. Literature Introduction to electrical engineering, Mulukutla S. Sarma. Handout notes for Sequential synchronous circuits, Jay Hoy. Digital Teknik, Leif Møller Andersen. 11.3. Software tools TINA Pro for Windows, www.designsoft.com 26 Napier University Edinburgh