Sony IMX145 8 Mp, 1.4 µm Pixel Pitch Back Illuminated (BSI) CMOS Image Sensor from the Apple iphone 4S Smartphone Imager Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR-1111-801 22553JMJM Revision 1.0 Published: January 19, 2012
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream and Package Overview 2.2 IMX145 Back of Die 2.3 IMX145 Front of Die 3 Die Utilization Analysis 3.1 Die Overview 4 Process Analysis 4.1 Overview 4.2 General Device Structure 4.3 Image Sensor Substrate and Wells 4.4 Image Sensor Substrate Isolation 4.5 Peripheral Transistors and Poly 4.6 Front Dielectrics 4.7 Front Metallization 4.8 Front Vias and Contacts 4.9 Wafer Bonding 4.10 Back of Substrate Features (Dielectrics, Metals, Color Filters, and Microlenses) 4.11 Bond Pads and Test Pads 5 Pixel Analysis 5.1 Pixel Overview and Schematic 5.2 Pixel Plan-View Analysis 5.3 Pixel Cross-Sectional Analysis Diagonal Across FD and Transfer Gate 5.4 Pixel Cross-Sectional Analysis Parallel to Column Out Lines 5.5 Pixel Cross-Sectional Analysis Parallel to Row Select Lines 6 SRAM Analysis 6.1 Overview 6.2 SRAM Plan-View Analysis
Imager Process Review 7 Critical Dimensions 7.1 Package Overview 7.2 Die Features 7.3 Image Sensor Substrate and Wells 7.4 Image Sensor Substrate Isolation 7.5 Peripheral Transistors and Poly 7.6 Front Dielectrics 7.7 Front Metallization 7.8 Front Vias and Contacts 7.9 Wafer Bonding and Carrier Wafer 7.10 Back of Substrate Features (Dielectrics, Metals, Color Filters, and Microlenses) 7.11 Pixels 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Apple iphone 4S Front with Secondary Camera 2.1.2 Apple iphone 4S Rear with Primary Camera 2.1.3 Apple iphone 4S Top with Microphone Jack and Power Button 2.1.4 Apple iphone 4S Bottom with Speaker, Docking Connector, and Microphone 2.1.5 Apple iphone 4S Smartphone Teardown (1 of 5) 2.1.6 Apple iphone 4S Smartphone Teardown (2 of 5) 2.1.7 Apple iphone 4S Smartphone Teardown (3 of 5) 2.1.8 Apple iphone 4S Smartphone Teardown (4 of 5) 2.1.9 Apple iphone 4S Smartphone Teardown (5 of 5) 2.1.10 Camera Module Top 2.1.11 Camera Module Bottom 2.1.12 Camera Module Oblique View 2.1.13 Camera Module Side View 2.1.14 Camera Module Top X-Ray 2.1.15 Camera Module Side X-Ray 2.1.16 Camera Module Back with Markings 2.1.17 CMOS Image Sensor Package Side X-Ray 2.1.18 CMOS Image Sensor Package with PWB Removed 2.1.19 CMOS Image Sensor Package Bottom 2.1.20 Package Cross Section of IMX145 Die 2.1.21 PZ493 Co-Packaged Die Photograph 2.1.22 PZ493 Co-Packaged Die Markings 2.1.23 TPSBPS2292 Co-Packaged Die Photograph Top Metal 2.1.24 TPSBPS2292 Co-Packaged Die Photograph Metal 1 2.1.25 TPSBPS2292 Co-Packaged Die Markings Die Label 2.1.26 TPSBPS2292 Co-Packaged Die Markings Trademark 2.2.1 IMX145 Back Die Photograph with Filters and Lenses Removed 2.2.2 Annotated Back Die Photograph 2.2.3 IMX145 Back Die Photograph at Poly 2.2.4 Annotated Back Die Photograph at Poly 2.2.5 Analysis Sites 2.3.1 Annotated Top Metal Die Photograph 2.3.2 IMX145 Overview of Front Die Corner D 2.3.3 Die Markings 2.3.4 Front Die Corner A 2.3.5 Front Die Corner B 2.3.6 Front Die Corner C 2.3.7 Front Die Corner D 2.3.8 Active Pixel Array Front Corner D 2.3.9 Detail of Bond Pad 2.3.10 Pitch of Bond Pads and Test Pads
Overview 1-2 3 Die Utilization Analysis 3.1.1 Annotated Back of Die Photograph at Poly 3.1.2 Minimum Standard Logic Cell Size 4 Process Analysis 4.2.1 General Structure Periphery 4.2.2 General Structure Pixel Array Edge 4.2.3 Die Thickness 4.2.4 Die Edge 4.2.5 Die Seal 4.2.6 Detail of Bump Bonds 4.3.1 SIMS Sample Reference 4.3.2 SIMS Analysis Sites 4.3.3 SCM of Peripheral Region 4.3.4 Substrate SIMS Logic Region Site SIMS 2A 4.3.5 Substrate SIMS Logic Region Site SIMS 2B 4.3.6 Overview of Embedded N-Well Si Delineation Etch 4.3.7 SCM of Embedded Logic N-Well 4.3.8 Plan-View SCM Image of the Bottom of the Pixel Array Isolation Well 4.3.9 SCM of Pixel Array Isolation Ring 4.3.10 SCM of Pixel Array Isolation Well and N-Type Pixel Cathodes 4.3.11 Overview of Pixel Array Si Stain 4.3.12 Substrate SIMS Pixel Array 4.3.13 SCM Overview of Pixel Array 4.3.14 SCM of Photocathodes Junction Depth 4.4.1 DTI Overview 4.4.2 SEM of DTI Top 4.4.3 SEM Detail of DTI Bottom 4.4.4 STI at Transition from Pixels to Periphery 4.4.5 Minimum Width STI 4.4.6 TEM Detail of Pixel STI Near a Poly Gate 4.4.7 Poly Over STI in Gate Wrap Region 4.5.1 Logic MOS Transistors Oxide Etch 4.5.2 Logic MOS Transistors Si Stain 4.5.3 TEM Overview of Logic Transistor Gates 4.5.4 TEM of Logic Transistor Gate 4.5.5 TEM Lattice Image of Gate Dielectric Near SWS 4.5.6 TEM Lattice Image of ONO Gate Dielectric 4.6.1 Overview of Front Dielectrics 4.6.2 Peripheral PMD 4.6.3 TEM of Pixel Array PMD Layers 4.6.4 ILD 1 to ILD 4 4.6.5 TEM of ILD 1 4.6.6 TEM of ILD 2 4.6.7 TEM of ILD 3 4.6.8 TEM of ILD 4
Overview 1-3 4.6.9 TEM of Upper Passivation and Wafer Bond Region 4.7.1 Overview of Front Metallization 4.7.2 Minimum Pitch Metal 1 4.7.3 TEM of Metal 1 Liner 4.7.4 Minimum Pitch Metal 2 4.7.5 TEM of Metal 2 Liner 4.7.6 Minimum Observed Metal 3 Pitch 4.7.7 TEM of Metal 3 Liner 4.7.8 Minimum Pitch Metal 4 4.7.9 TEM of Metal 4 Liner 4.7.10 Metal 5 Bottom Barrier 4.7.11 Metal 5 Top Cap Layer 4.8.1 Overview of Contact and Via Structures 4.8.2 Minimum Pitch Contacts to Substrate 4.8.3 Minimum Pitch Contacts to Poly 4.8.4 TEM of Contact to Silicon Pixel Array 4.8.5 TEM of Contact to Poly Pixel Array 4.8.6 TEM of Stacked Via 1 and Via 2 Features 4.8.7 TEM of Via 3 With Metals and Dielectrics 4.9.1 Upper Passivation and Wafer Bond Region 4.9.2 TEM of Carrier Wafer Bond Region 4.10.1 Back of Substrate Feature Overview Si Stain 4.10.2 Back Metal Substrate Contact Si Stain 4.10.3 Detail of Back Substrate Contact 4.10.4 TEM of Back Metal Light Shield 4.10.5 TEM Overview of AR Layers, Back PMD, and Light Shield 4.10.6 TEM of Back Antireflection Layer 4.10.7 Blue and Green Filters 4.10.8 Red and Green Filters 4.10.9 TEM Overview of Back of Die, with Red and Green Filters 4.10.10 TEM Overview of Back of Die, with Blue and Green Filters 4.10.11 Microlens Cap Layer 4.11.1 Bond Pad Overview 4.11.2 Bond Pad Edge 4.11.3 Detail of Bond Pad Edge 5 Pixel Analysis 5.1.1 Shared Pixel Schematic 5.2.1 Pixels at Metal 5 5.2.2 Pixels at Metal 4 5.2.3 Pixels at Via 3/Metal 3 5.2.4 Pixels at Metal 3 5.2.5 Pixels at Via 2/Metal 2 5.2.6 Pixels at Metal 2 5.2.7 Pixels at Via 1/Metal 1 5.2.8 Pixels at Metal 1
Overview 1-4 5.2.9 Pixels at Poly 5.2.10 Pixels at Diffusion 5.2.11 SCM Plan View of Pixels Front Overview 5.2.12 SCM Plan View of Pixels Near Surface 5.2.13 SCM Plan View of Eight Cathode Group 5.2.14 Planar SCM of Pixel Cathodes Near Back Surface 5.3.1 TEM Overview of Floating Diffusion Region 5.3.2 TEM of Transfer Gate and FD Contact 5.3.3 TEM of Transfer Gate SWS Region 5.3.4 TEM of Pixel Array ONO Gate Dielectric 5.4.1 Edge Microlens Shift (Vertical) 5.4.2 Section Along FD Strap Si Stain 5.4.3 Reset Transistor Gate Width Si Stain 5.4.4 Source Follower Transistor Gate Width Si Stain 5.4.5 Row Select Transistor Gate Width 5.4.6 Pixel Floating Diffusion Region 5.4.7 TEM Detail of Contact to Substrate and Pixel STI 5.5.1 Edge Microlens Shift (Horizontal) 5.5.2 Microlenses Near Array Center 5.5.3 SCM Cross Section of Pixel Array 5.5.4 Source Follower and Row Select Transistor 5.5.5 Detail of Source Follower Transistor 5.5.6 Detail of Row Select Transistor 5.5.7 Reset Transistor Gate Length 5.5.8 Transfer Gates Horizontal Section 6 SRAM Analysis 6.1.1 6T SRAM Pixel Schematic 6.2.1 Overview of SRAM Cells at Poly and Diffusion 6.2.2 6T SRAM at Metal 3 6.2.3 6T SRAM at Metal 2 6.2.4 6T SRAM at Metal 1 6.2.5 6T SRAM at Poly 6.2.6 6T SRAM at Diffusion
Overview 1-5 1.2 List of Tables 1 Overview 1.4.1 Image Sensor and Camera Module Specifications 1.4.2 Sony IMX145, IMX081, and IMX050 Process Technology Comparison 1.4.3 Device Identification 1.5.1 IMX145 Device Summary 1.6.1 IMX145 Process Summary 2 Device Overview 2.1.1 Camera Module and CMOS Image Sensor Package Summary 2.2.1 Die, Bond Pad, and Standard Cell Dimensions 3 Die Utilization Analysis 3.1.1 Die Utilization 4 Process Analysis 4.3.1 Substrate and Well Vertical Dimensions 4.4.1 Substrate Isolation Critical Dimensions 4.5.1 Transistor and Poly Horizontal Dimensions 4.5.2 Transistor and Poly Vertical Dimensions 4.6.1 Measured Dielectric Thicknesses 4.7.1 Front Metallization Thicknesses 4.7.2 Front Metallization Width and Pitch 4.8.1 Front Via and Contact Horizontal Dimensions 4.9.1 Silicon Carrier Wafer Dielectric Vertical Dimensions 4.10.1 Back Dielectrics and Metals Vertical Dimensions 5 Pixel Analysis 5.1.1 Pixel Horizontal Dimensions 5.1.2 Pixel Vertical Dimensions 5.1.3 Pixel Transistor Dimensions 7 Critical Dimensions 7.1.1 Camera Module and CMOS Image Sensor Package Summary 7.2.1 Die, Bond Pad, and Standard Cell Dimensions 7.3.1 Substrate and Well Vertical Dimensions 7.4.1 Substrate Isolation Critical Dimensions 7.5.1 Transistor and Poly Horizontal Dimensions 7.5.2 Transistor and Poly Vertical Dimensions 7.6.1 Measured Dielectric Thicknesses 7.7.1 Front Metallization Thicknesses 7.7.2 Front Metallization Width and Pitch 7.8.1 Front Via and Contact Dimensions 7.9.1 Silicon Carrier Wafer Dielectric Vertical Dimensions 7.10.1 Back Dielectrics and Metals Vertical Dimensions 7.11.1 Pixel Horizontal Dimensions 7.11.2 Pixel Vertical Dimensions 7.11.3 Pixel Transistor Dimensions
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