Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion with and OE features TTL-compatible inputs and outputs Automatic power-down when deselected Available in pb-free 28-pin TSOP I and 28-pin (300-Mil) Molded DIP Logic Block Diagram Functional Description 32K x 8 Static RAM The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable () and active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When and WE inputs are both LOW, data on the eight data input/output pins (I/O 0 through I/O 7 ) is written into the memory location addressed by the address present on the address pins (A 0 through A 14 ). Reading the device is accomplished by selecting the device and enabling the outputs, and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity. Pin Configurations DIP Top View WE OE A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 ROW DECODER A 10 INPUT BUFFER A 11 32K x 8 ARRAY COLUMN DECODER A 12 A 13 A 14 SENSE AMPS POWER DOWN I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 I/O 0 I/O 1 I/O 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 14 15 V CC WE A 4 A 3 A 2 A 1 OE A 0 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 OE 22 21 A 0 A 1 23 20 A 2 24 19 I/O 7 A 3 25 18 I/O 6 A 4 26 17 I/O 5 WE 27 TSOP I 16 I/O 4 V CC 28 Top View 15 I/O 3 A 5 1 (not to scale) 14 GND A 6 2 13 I/O 2 A 7 3 12 I/O 1 A 8 4 11 I/O 0 A 9 5 10 A 14 A 10 6 9 A 13 A 11 7 8 A 12 Selection Guide 12 15 20 Unit Maximum Access Time 12 15 20 ns Maximum Operating Current 160 155 150 ma L 90 Maximum CMOS Standby Current 10 10 10 ma L 0.05 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-05160 Rev. *B Revised August 3, 2006
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature... 65 C to +150 C Ambient Temperature with Power Applied... 55 C to +125 C Supply Voltage to Ground Potential (Pin 28 to Pin 14)... 0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State [1]... 0.5V to V CC + 0.5V Electrical Characteristics Over the Operating Range [3] CY7C199 DC Input Voltage [1]... 0.5V to V CC + 0.5V Output Current into Outputs (LOW)... 20 ma Static Discharge Voltage... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current... > 200 ma Operating Range Range Ambient Temperature [2] V CC Commercial 0 C to +70 C 5V ± 10% -12-15 -20 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma 2.4 2.4 2.4 V V OL Output LOW Voltage V CC = Min., I OL =8.0 ma 0.4 0.4 0.4 V V IH Input HIGH Voltage 2.2 V CC + 0.3V 2.2 V CC + 0.3V 2.2 V CC + 0.3V V IL Input LOW Voltage 0.5 0.8 0.5 0.8 0.5 0.8 V I IX Input Leakage Current GND < V I < V CC 5 +5 5 +5 5 +5 µa I OZ Output Leakage Current GND < V O < V CC, Output Disabled 5 +5 5 +5 5 +5 µa I CC V CC Operating Supply V CC = Max., Com l 160 155 150 ma Current I OUT = 0 ma, f = f MAX = 1/t RC L 90 ma I SB1 Automatic Max. V CC, > V IH, Com l 30 30 30 ma Power-down Current TTL Inputs V IN > V IH or V IN < V IL, f = f MAX L 5 ma I SB2 Automatic Max. V CC, Com l 10 10 10 ma Power-down Current CMOS Inputs > V CC 0.3V V IN > V CC 0.3V or V IN < 0.3V, f = 0 L 0.05 ma Notes: 1. V IL (min.) = 2.0V for pulse durations of less than 20 ns. 2. T A is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testing information. V Document #: 38-05160 Rev. *B Page 2 of 11
Capacitance [4] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 8 pf C OUT Output Capacitance V CC = 5.0V 8 pf AC Test Loads and Waveforms [5] 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE R1 481Ω (a) R2 255 Ω 5V OUTPUT 5pF INCLUDING JIG AND SCOPE R1 481Ω (b) R2 255Ω 3.0V GND 10% t r ALL INPUT PULSES 90% 90% 10% t r Equivalent to: THÉ VENIN EQUIVALENT 167 Ω OUTPUT 1.73V Data Retention Characteristics Over the Operating Range (L-version only) Parameter Description Conditions [6] Min. Max. Unit V DR V CC for Data Retention 2.0 V I CCDR Data Retention Current V CC = V DR = 2.0V, 10 µa t [4] CDR Chip Deselect to Data Retention Time > V CC 0.3V, V IN > V CC 0.3V or V IN < 0.3V 0 ns [5] t R Operation Recovery Time 200 µs Data Retention Waveform V CC 3.0V DATA RETENTION MODE V DR > 2V 3.0V t CDR t R Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. t R < 3 ns for the -12 and the -15 speeds. t R < 5 ns for the -20 and slower speeds. 6. No input may exceed V CC + 0.5V. Document #: 38-05160 Rev. *B Page 3 of 11
Switching Characteristics Over the Operating Range [3,7] Parameter Read Cycle Description -12-15 -20 Min. Max. Min. Max. Min. Max. t RC Read Cycle Time 12 15 20 ns t AA Address to Data Valid 12 15 20 ns t OHA Data Hold from Address Change 3 3 3 ns t A LOW to Data Valid 12 15 20 ns t DOE OE LOW to Data Valid 5 7 9 ns t LZOE OE LOW to Low-Z [8] 0 0 0 ns t HZOE OE HIGH to High-Z [8, 9] 5 7 9 ns t LZ LOW to Low-Z [8] 3 3 3 ns t HZ HIGH to High-Z [8, 9] 5 7 9 ns t PU LOW to Power-up 0 0 0 ns t PD HIGH to Power-down 12 15 20 ns [10, 11] Write Cycle t WC Write Cycle Time 12 15 20 ns t S LOW to Write End 9 10 15 ns t AW Address Set-up to Write End 9 10 15 ns t HA Address Hold from Write End 0 0 0 ns t SA Address Set-up to Write Start 0 0 0 ns t PWE WE Pulse Width 8 9 15 ns t SD Data Set-up to Write End 8 9 10 ns t HD Data Hold from Write End 0 0 0 ns t HZWE WE LOW to High-Z [9] 7 7 10 ns t LZWE WE HIGH to Low-Z [8] 3 3 3 ns Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 8. At any given temperature and voltage condition, t HZ is less than t LZ, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for any given device. 9. t HZOE, t HZ, and t HZWE are specified with C L = 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t HZWE and t SD. Unit Document #: 38-05160 Rev. *B Page 4 of 11
Switching Waveforms Read Cycle No. 1 [12, 13] t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [13, 14] t RC OE t A DATA OUT t DOE t LZOE HIGH IMPEDAN DATA VALID t HZOE t HZ HIGH IMPEDAN t LZ V CC SUPPLY CURRENT t PU 50% t PD 50% ICC ISB Notes: 12. Device is continuously selected. OE, = V IL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with transition LOW. Document #: 38-05160 Rev. *B Page 5 of 11
Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [10, 15, 16] t WC ADDRESS t AW t HA WE t SA t PWE OE t SD t HD DATA I/O DATA IN VALID t HZOE [10, 15, 16] Write Cycle No. 2 ( Controlled) t WC ADDRESS t S t SA t AW tha WE t SD t HD DATA I/O DATA IN VALID Notes: 15. Data I/O is high impedance if OE = V IH. 16. If goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05160 Rev. *B Page 6 of 11
Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled OE LOW) [11, 16] t WC ADDRESS t AW t HA WE t SA t SD t HD DATA I/O DATA IN VALID t HZWE t LZWE Typical DC and AC Characteristics NORMALIZED I CC,I SB NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 I CC 0.8 0.6 V IN =5.0V 0.4 0.2 I SB 0.0 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED I CC,I SB 1.4 1.2 1.0 0.8 0.6 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE I CC 0.4 V CC =5.0V V IN =5.0V 0.2 I SB 0.0 55 25 125 AMBIENT TEMPERATURE ( C) OUTPUT SOUR CURRENT (ma) OUTPUT SOUR CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 V CC =5.0V 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED AA t NORMALIZED ACSS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) NORMALIZED t AA 1.6 1.4 1.2 1.0 0.8 NORMALIZED ACSS TIME vs. AMBIENT TEMPERATURE V CC =5.0V 0.6 55 25 125 AMBIENT TEMPERATURE ( C) OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 V CC =5.0V 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) Document #: 38-05160 Rev. *B Page 7 of 11
Typical DC and AC Characteristics (continued) 3.0 TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 30.0 TYPICAL ACSS TIME CHANGE vs. OUTPUT LOADING NORMALIZED I CC vs. CYCLE TIME 1.25 NORMALIZED I PO 2.5 2.0 1.5 1.0 0.5 DELTA t AA (ns) 25.0 20.0 15.0 10.0 5.0 V CC =4.5V NORMALIZED I CC 1.00 0.75 V CC =5.0V V IN =0.5V 0.0 0.0 1.0 2.0 3.0 4.0 SUPPLY VOLTAGE (V) 5.0 0.0 0 200 400 600 800 CAPACITAN (pf) 1000 0.50 10 20 30 40 CYCLE FREQUENCY (MHz) Truth Table WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power-down Standby (I SB ) L H L Data Out Read Active (I CC ) L L X Data In Write Active (I CC ) L H H High Z Deselect, Output disabled Active (I CC ) Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 12 CY7C199-12ZXC 51-85071 28-pin TSOP I (Pb-free) Commercial 15 CY7C199-15ZXC 51-85071 28-pin TSOP I (Pb-free) Commercial CY7C199L-15ZXC 20 CY7C199-20PXC 51-85014 28-pin (300-Mil) Molded DIP (Pb-free) Commercial Document #: 38-05160 Rev. *B Page 8 of 11
Package Diagrams 28-pin (300-Mil) PDIP (51-85014) SEE LEAD END OPTION 14 1 0.260[6.60] 0.295[7.49] DIMENSIONS IN INCHES [MM] MIN. MAX. REFEREN JEDEC MO-095 PACKAGE WEIGHT: 2.15 gms 15 28 0.030[0.76] 0.080[2.03] SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.140[3.55] 0.190[4.82] 0.120[3.05] 0.140[3.55] 0.115[2.92] 0.160[4.06] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] SEE LEAD END OPTION 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] 3 MIN. LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014-*D Document #: 38-05160 Rev. *B Page 9 of 11
Package Diagrams (continued) 28-pin TSOP Type 1 (8x13.4 mm) (51-85071) 51-85071-*G All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05160 Rev. *B Page 10 of 11 Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Document History Page Document Title: CY7C199 32K x 8 Static RAM Document Number: 38-05160 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109971 10/28/01 SZV Change from Spec number: 38-00239 to 38-05160 *A 121730 01/09/02 DFP Updated Product Offering table *B 492500 See ECN NXR Removed 8 ns, 10 ns, 25 ns, 35 ns, 45 ns speed bins Removed 28-Lead (300-Mil) CerDIP, 28-Pin Rectangular Leadless Chip Carrier, 28-Lead Molded SOIC, 28-Lead Molded SOJ packages from product offering Changed the description of I IX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed I OS parameter from DC Electrical Characteristics Table Updated Ordering Information Table Document #: 38-05160 Rev. *B Page 11 of 11