MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana Singh Assistant Professor ECE Department MIT Moradabad,Moradabad, U.P., aalps_646@rediffmail.com Ritika Tandon Assistant Professor ECE Department MIT, Moradabad, Moradabad U.P., ritikatandon15@gmail.com Pallavi Saxena ME Scholar NITTTR, Chandigarh, pspallavisaxena@gmail.com ABSTRACT In this paper effects of varying oxide thickness have been analyzed on oxide capacitance. The p well MOSFET device has been designed and simulated using 80 nm technologies with TCAD tool. The oxide thickness has been varied from 10 nm to 11nm and its effects on oxide capacitance has been analyzed. This result shows that when tox is 10.13 nm, the C ox increased with 4.5 10-17 F/m while C ox decreased by 12.3 % when tox is 10.42 nm. Since the integrated circuits being scaled down for improvement in performance and lower power consumption, understanding the rate of gate oxide thickness will lead to better models. Key Words: NMOS; Metal Oxide Semiconductor Field-Effect Transistor (MOSFET); Capacitance-Voltage Characteristics; Oxide Thickness. 1. INTRODUCTION The metal oxide semiconductor field-effect transistor or known as MOSFET is the most used semiconductor device today. With high yield, low cost and dense packaging is considerations that have pushed the MOSFET to the status of the most widely used device in information technology hardware[1]. The MOSFET is a device used to amplify or switch electronic signals with fast switching time and most important device for very large scale integrated (VLSI) circuits such as microprocessor. With demand increased for mobile communication and computation, power consumption is a great value to be considered, the MOSFET has become increasingly critical used since it consumes little power[2]. In MOSFET, there are three terminals such as source (S), drain (D) and gate (G). The top layer of the MOS system is the metal, and it is used to form the gate electrode. Central to the functionality is the thin insulating layer, the gate-oxide. Gate oxide layer or known as dielectric is to provide an isolation layer between metal and semiconductor so that there is no current flow between gate and substrate of the semiconductor as shown in Fig.1. Up till now, the silicon dioxide (SiO 2 ) has been used as a gateoxide due to its properties of high- quality electrical insulator and it s used as barrier material during impurity deposition[3]. Besides, SiO 2 is a very good insulator, typically having a resistivity greater than 10 15 (Ω-cm) and large 8-9 ev energy band gap. The MOS (Metal Oxide Semiconductor) transistor is the most promising active component for silicon VLSI circuits at the present time [4]. There are a number of reasons for this choice. Fig. 1: Cross section of NMOS structure First, it is self isolating, so that the devices can placed side by side on a chip without the needs for providing isolation tubs. As a result, it is considerably smaller than its bipolar counterpart, and requires less processing steps. Furthermore, it can be made in bulk silicon, thus avoiding the costly epitaxial growth [5]. Hence, epitaxial structures are increasingly used in high density application, to minimize latch up problems, caused by devices interactions through a common substrate. The MOS transistor contains two types, the p channel MOS- FET (PMOS) and n-channel MOSFET (NMOS).Both of these MOS transistors have their own characteristic that differentiates each other [6]. The p channel transistor (PMOS), based on aluminum gate technology, was the earliest practical MOS device structure.
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 82 In this project, the NMOS transistors are used. The purpose of this research is to analyze the effect of oxide thickness on C-V and I-V characteristics for the NMOS. 2. BACKGROUND One of important consideration of the MOS structure is the capacitance as a function of applied voltage. It is provide an important characterization tool to check on the quality of the structure. In C-V measurements, a dc bias voltage is applied to the gate, and a small signal is applied to obtain the capacitance at the bias applied. There are three important regions such as accumulation, depletion and inversion. In accumulation, the holes accumulate at the surface and creating a positive mobile interface charge. There no depletion regions here. At this point, the MOS is behave like a parallel plate capacitor with SiO 2 as the dielectric with equation C C ox per unit area...(1) where C ox is the oxide capacitance per unit area. As the gate voltage becomes positive and the channel is depleted of holes, the depletion capacitance becomes. As the device gets more depletion, it will be an inversion regions. The capacitance depends on measurements at low frequencies (typically ~1 100 MHz) or high frequency (typically ~1MHz) since in certain time is needed to generate the minority carriers in the inversion layer. At low frequency, capacitance equals the oxide capacitance since charge is added to and removed from inversion layer and the capacitance can be calculated by equation. C Where SiO 2 is oxide permittivity. esio 2 t ox...(2) For high frequency, capacitance obtained from series connection of the oxide capacitance and depletion capacitance with maximum depletion width. From high frequency C-V characteristics in the inversion, the values of parameter bulk or depletion capacitance C B, the depletion width WB and the doping concentration in the substrate of can be calculated as in equation (3), (4) and(5). C B esi W B...(3) 3. TCAD BASED NMOS DESIGN The general processes to design 80nm MOSFET involving simulation of fabrication process, structure and mesh and electrical testing. A recipe of MOSFET is modified and used in this design. The first process was the simulation for 80nm MOSFET fabrication process which was designed using TCAD. For the fabrication process, the development of the NMOS started with the formation of n-well for p-substrate. The p-substrate was layered with a 100A thick oxide layer by oxidation process. This oxide layer will act as a protector when doing ion implantation process. After that, phosphorus was implanted with the positive resistive as a mask during the annealing process. The temperature used is in range 900-1200 Celsius temperature. Fig. 2: Structure of NMOS The process is followed by formation of active area for transistor NMOS. These areas were defined using photolithography. The active edge of NMOS which is p-well is normally covered by lithography. Then, the implantation of boron ion was done to increase the density of n-type surface. It will act as an obstacle of p-channel under the field oxide. W B 2εSi( 2φf ) qn...(4) 4 ff kt q ln N ' A η f...(5) where q is the magnitude of charge (1.602 10 19 Coulomb), Si is the dielectric constant of Si (11.8), k is Boltzman s Constant (1.38 10 23 J/K), N A is the acceptor concentration, and T is temperature. The C inversion also can be calculated by equation (6). C' ox C' B C inversion...(6) C' + C' ox B Fig. 3: Meshing of NMOS
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 83 The next process is the formation of the polysilicon gate where the oxide layer will be growth and also the implantation of boron ion. The pattern of the gate is designated by lithography action for drain (D) and source (S). The formation process of drain (D) and source(s) for MOSFET is carried with resistive electron layer by all over the wafer for S and D pattern. The final process for development of MOSFET is metallization. The aluminum materials are doped on wafer surface. The resistive layer is coated and the related patterns are made by lithography proces. In process simulation, processing steps such as etching, deposition, ion implantation, thermal annealing and oxidation are Si simulated based on physical equations, which govern the respective processing steps. The simulated part of the silicon wafer is discredited (meshed) and represented as a finite-element structure. After the fabrication processes are completed, the electrical testing called device simulation is done onto the fabricated MOSFET. Each node of the device has properties associated with it, such as material type and doping concentration. For each node, the carrier concentration, current densities, electric field, generation and recombination rates, and so on are computed. 4. SIMULATION AND DISCUSSION A. Device Simulator The process and device simulation has been done by TCAD. There are some operation involved to fabricate NMOS structure such as developing a good simulation grid, performing conformal deposition, performing geometric etches, performing oxidation, diffusion, annealing, and ion implantation, metallization, structure manipulation, and loading structure information. The NMOS structure can be plot by the TCAD simulator as shown in Figs. 2,3,4,5. In process simulation, processing steps such as etching, deposition, ion implantation, thermal annealing and oxidation are simulated based on physical equations,which govern the respective processing steps. The simulated part of the silicon wafer is discretized (meshed) and represented as a finite-element structure. After the fabrication processes are completed, the electrical testing called device simulation is done onto the fabricated MOSFET. Fig. 4: Layout of 80 nm NMOS transistor Device simulations can be thought of as a virtual measurement of the electrical behavior of a semiconductor device, such as a transistor or diode. The device is represented as a meshed finiteelement structure. B. C-v Characteristics From Figs. 7 and 8, the graph that being extracted is for the low frequency of 1Hz. When Vg 0V or less, the graph shows that it is in accumulation regions. The C ox value in accumulation for to x 10.13nm is 4.5 10 17 F/m while C ox value for tox 10.42nm is 4.0 10 17 F/m. For Vg range of 0V to 2.5V, the graph is in depletion regions and starts 2.5 V above, the graph is in inversion regions. Fig. 6: Gate oxidation parameters Fig. 5: 2D view of NMOS During the inversion region, the capacitor depends on frequency. The capacitance for 1Hz is equal to C ox per unit area where for Vg 5V, C ox value for tox 10.13 nm is 6.875 10 17 F/m and C ox value in inversion for to x 10.42nm is 6.0 10 17 F/m. With low frequency, the values of C ox can be calculated by equation (2).
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 84 There are two electrical DC analyses done onto the NMOS a transistors to obtain the curve for ID (Drain Current) versus VGS (Gate to Source Voltage) and ID (Drain Current) versus VD (Drain Voltage). Fig. 7: C-V characteristics graph for difference SiO 2 In Table 1, the simulation values of C ox is from Fig. 6 when Vg 0V for both thickness. For the simulation value of C ox, its decreased by 12.3% when tox is 10.42nm while for calculated value, C ox decreased by 2.79 %. Table 1: Values of C ox of 10.13 nm and 10.42 nm Fig. 9: ID (Drain Current) -VGS (Gate to Source Voltage) tox Calculated C ox Simulation C ox 10.13 nm 3.407 10 3 F/m 4.5 10 1 F/m 10.42 nm 3.312 10 3 F/m 4.0 10 1 F/m By equation (3), (4), (5) and (6), the C B 2.132 10 9 F/m, WB 0.049 m, and Φf 0.9307 V. The value of C inversion for 10.13 nm is 1.7613 10 9 F/m while C inversion for 10.42 nm is 1.769 10 9 F/m. Fig. 10: ID (Drain Current)-VD (Drain Voltage) graph for 80 nm NMOS Table 2: Simulation values for 80nm MOSFET Fig. 8: C-V characteristics graph for different oxide thickness C. I-v ChARACTERISTICS Figs 2,4 depict the layout for NMOS transistor. For both transistors, the metal used is aluminum. The metals are used for interconnection and routing. The insulator used in this device is polysilicon. The source and drain areas are shown in green colour and placed in between gate region for both transistors. The electrical DC analysis are done for both transistors and the results are shown using TCAD tools. Type NMOS Vth (v) 0.210889 Idsat (A) 9.575e 04 Ioff (A) 2.623e 05 The threshold voltage (Vth) for transistor MOSFET is also known as the voltage that was generated between the gate and source at MOS device where current drain-source, drop until zero value. From Figs. 9 and 10, Vth is the starting voltage for MOS transistor. If the value of voltage that is being used is less than Vth, the transistor will be in cut-off area. The threshold voltage (Vth) for 80nm p-well MOSFET is 0.210889V for NMOS. Table 2 shows the value of drain saturation current (Idsat) for NMOS transistor is 9.575e 04. The Idsat is increasing proportionally with the increasing of gate length.
MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 85 The opposite situation happens for leakage current. For the operating of ideal MOS transistor, the current only flow when it is in linear operation. When the transistor is off, no current will flow. But due to some geometrical effects, there is leakage current in small amount though the transistor in cut off operation. 5. CONCLUSION In this paper, device simulators are employed to see the effect of oxide thickness on C-V characteristics and analyze the parameters by C-V measurements. As in objectives, here shown that the C ox will be decreased when oxide thickness is being increased. The design of 80nm p-well MOSFET transistor was done using two main processes which are device simulation and process simulation. Three main parameters are obtained and analyzed which are Threshold Voltage (Vth), Drain Saturation Current (Idsat) and Leakage Current (Ioff). The Idsat is increasing proportionally with the increasing of gate length. The opposite situation happens for leakage current.for the operatingof ideal MOS transistor, the current only flow when it is in linear operation. REFERENCES 1. Kenneth J. Wu, Krishna Sesha and Timothy J., The Quality and Reliability of Intel s Quarter Micron Process (Journal style), Intel Technology Journal, pp. 9-11, 1998. 2. Abdul Aziz A. Osman S.S. A Simulation Based Study On C-V Characteristics Of Oxide Thickness for NMOS, International Conference on Electronic Devices, Systems and Applications, Vol. No.978-1-4244-6632-0, 2010. 3. Hong Xiao, Introduc tion to Semiconduc tor Manufa cturing Technology (Book style), New Jersey, Prentice Hall, pp. 2,380-86.53-181,313-360, 447-501, 2001. 4. Clein, Dan, CMOS Layout, Concepts, Methodologies and Tools (Book style), Newnes Article in a conference proceedings, pp. 7-9, 2000. 5. Ng Jin Aun, Ibrahim Ahmad, and Burhanuddin Yeop Majlis, Rekabentuk, Simulasi dan Pencirian Teknologi 0.25μm Peranti MOSFET (Published Conference Proceedings Style), IEEE National Symposium on Microelectronics (NSM 2003), pp. 221-224, 2003. 6. Galup-Montoro, M. C. Schneider, Mosfet Modelling for Circuit analysis and Design, pp.7-10, 2007.