6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-1 Lecture 24 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) The Long Metal-Oxide-Semiconductor Field-Effect Transistor Contents: April 6, 2007 1. Dynamics of the MOS structure (cont.) 2. Three-terminal MOS structure 3. Introduction to MOSFET Reading assignment: del Alamo, Ch. 8, 8.5-8.6; Ch. 9, 9.1
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-2 Key questions What happens to the C-V characteristics of a MOS structure if the bias is switched abruptly? What happens to the electrostatics of the MOS structure if we contact the inversion layer and we apply a bias to it? How does a MOSFET look like and how does it work (roughly)?
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-3 1. Dynamics of the MOS structure (cont.) Deep depletion Consider what happens after the application of a voltage step from depletion towards inversion. On top of step, put HF small signal to measure C V V th A + ++ + - - - - - - - - - equilibrium 0 ++ + 0 t B + ++ - - - - - - - - - - - - - - - - - - - - - - - - C x d >x dmax A - - - - - - ++ + - - - - C C - + - HF C - - - - - - + ++ - - - - - - x dmax C dd B 0 t - deep depletion (t<<τ g ) inversion (t>>τ g ) Immediately after the onset of the step (after an RC delay), inversion layer does not have a chance to grow (electrons must be generated) MOS remains in depletion ( deep depletion ) x d grows beyond x dmax C smaller than C HF
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-4 Even though V > V th, capacitance in deep depletion described by expression derived for depletion regime: C dd C ox 1 + 4 V γ VFB 2 C-V characteristics: C Cox A low frequency C B high frequency deep depletion V
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-5 2. Three-terminal MOS structure Introduce contact to inversion layer: S G inversion layer VSB p depletion region VGB B Can now apply bias to inversion layer with respect to substrate, V SB. Source-body junction: -p junction only reverse bias desired, V SB 0. Interested only in inversion regime: apply V SB 0 keeping V GB constant.
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-6 Energy band diagrams: qvgb Efe=Efh Efe qvsb qvgs Efh qvgb EF EF VSB=0 VSB>0 φ s (V SB ) = φ s (V SB = 0) + V SB Application of V SB > 0, increases φ s, and also Q d.
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-7 V SB > 0 x d Q d φ s (as in reverse bias p-n junction). ρ xdmax (VSB=0) 0 -xox 0 x xdmax (VSB>0) -qna ε εs εox φ φbi+vgb εs 0 -xox 0 x φsth(vsb=0)+vsb φsth 0 -xox 0 x log po, no po NA p n no ni 2 NA -xox 0 x Total potential difference from G to B fixed: φ bi + V GB = φ ox + φ s Hence: φ ox E ox E s
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-8 But: Q s E s = ɛs Hence: Q s In summary: Q s Q d Q i equivalent to V th shifting positive. Key conclusion: application of a body bias turns inversion layer off! Important implications for device and circuit design and operation.
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-9 V th model that accounts for body bias Go to Poisson-Boltzmann formulation and change: φ sth φ sth + V SB Then: V th = V FB + φ sth + V SB + γ φ sth + V SB For MOSFET operation, interested in threshold in V GS : V GB = V GS + V SB Then: GS GB V th (V SB ) = V th V SB = V FB + φ sth + γ φ sth + V SB Can easily rewrite as: GS GS V th (V SB ) = V th (V SB = 0) + γ( φ sth + V SB φ sth ) GS Note: V SB V th
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-10 Back bias effect important in MOSFETs and CMOS. Ideally, the body of every MOSFET should be tied to its source, but that's expensive. What are the trade-offs? local body contact global body contact Focus on M3 (nmosfet) of NAND gate: with local body contact: VSB = 0 always + predictable with global body contact: sometimes VSB > 0 + slower switching, ",jitter" Cite as: leslis del Alamo, course materials for 6.7201 Integrated Microelectronic Devices, Spring 2007. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month W]
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-11 3. MOSFET Introduction Cross section and layout of n-channel MOSFET (NMOS): polysilicon gate body source drain gate p + p n inversion layer channel gate oxide n p + p Inversion layer links source and drain underneath gate.
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-12 Inversion layer current depends on: lateral field across inversion layer (set to first order by drain-tosource voltage) electron concentration in inversion layer (set to first order by gate-to-source voltage) L x j x ox p (N A ) n Key design parameters: gate length, L electrical channel length gate oxide thickness, x ox source and drain junction depth, x j doping level in body, N A
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-13 4. The ideal MOSFET L gate contact polysi gate gate oxide source contact drain contact channel region p intrinsic region extrinsic regions body contact Simplifying assumptions: Carrier flow is one dimensional. Uniform doping levels Electron transport in inversion layer takes place by drift (i.e., neglect diffusion). Electrons drift along the inversion layer in the mobility regime, i.e., the electron velocity is proportional to the lateral electric field along the inversion layer. Neglect body effect (dependence of V T with y) No parasitic resistances
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-14 Ignore junction sidewall effects. No three-dimensional effects (device scales perfectly with its width). Neglect impact of substrate that surrounds the transistor Definitions of spacial coordinates and voltages: 0 L y V DS V GS -x ox 0 x j V BS S I S inversion layer G depletion region D I D p B x
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 24-15 Key conclusions Deep depletion: condition of MOS structure suddently switched from below threshold to above threshold. Application of voltage to inversion layer with respect to substrate shifts threshold voltage: V SB V th.