INTEGRATED CIRCUIT ENGINEERING

INTEGRATED CIRCUIT ENGINEERING Basic Technology By the Stoff of Integraied Circuit Engineering Corporation, Phoenix, Arizona GLEN R. MADLAND ROBERT L. PRITCHARD HOWARD K. DICKEN FRANK H. BOWER ROBERT D. RICHARDSON DAVID B. KRET Fourth Edition Boston Technical Publishers, Inc. Central Square, Bax 111, Cambridge, Massachusetts 02139 U.S.A. 1966 in

CONTENTS Section FOREWORD iii?. THE ECONOMIC IMPACT OF INTEGRATED CIRCUITS 1.1 INTEGRATED CIRCUITS VS DISCRETE COMPONENT CIRCUITS 2 1.2 THE IMPACT OF INTEGRATED CIRCUITS 2 1.2.1 Economic Drives 2 1.2.2 Control of Circuit Design 2 1.2.3 The User-Supplier Interface 4 1.3 THE ELECTRONIC CIRCUIT DESIGNER AND INTEGRATED CIRCUIT PROCESSING 4 1. 4 CHANGING FROM CONVENTIONAL COMPONENTS TO INTEGRATED CIRCUITS 6 1.5 PRESENT STATUS OF INTEGRATED CIRCUITS 6 1.6 THE ECONOMICS OF MICROELECTRONICS 7 1.6.1 The Pricing Policies of the Semiconductor Industry 7 1.6.2 The Cost of Producing Integrated Circuits 7 l.a DEFINITION OF TERMS 10 l.b LIST OF SYMBOLS 12 l.c TABLE OF CONSTANTS 13 2. THE BASIC MATERIALS AND PROCESSES OF MICROCIRCUITS 2.1 SILICON 14 2.1.1 Electrical Properties of Silicon 14 2.1.2 Material Purification 16 2.1.3 Crystal Structure 20 2.1.4 Preparing Single Crystals 20 2.2 WATER PREPARATION 20 2.2.1 Slicing 20 2.2.2 Lapping and Polishing 20 2.3 PN JUNCTIONS 22 2.3.1 Alloy Junctions 22 2.3.2 Diffused Junctions 22 2.3.3 Epitaxially Grown Junctions 22 2.4 TRANSISTORS 22 2.5 OTHER ACTIVE DEVICES 24 2.5.1 Field Effect Transistors (FET) 24 2.5.2 Zener Diodes 24 2.5.3 Four Layer Devices 24 2.5.4 Thin Film Techniques 24 2.6 DIFFUSION 24 2.6.1 Diffusion Theory 26 2.6.2 Distribution Profiles 26 2.6.3 Dopants 26

2.6.4 2.6.5 Multiple Diffusions Diffusion Systems 28 28 2.7 EPITAXY 2.7.1 Epitaxial Growth 32 32 2.7.2 Epitaxial Systems 32 2.8 2.9 SILICON DIOXIDE CONDUCTORS 34 34 2.9.1 Gold 34 2.9.2 2.9.3 Aluminum Kovar 34 36 2.10 THE PACKAGING MATERIALS 36 2. 10.1 Ceramic 36 2.10.2 Glass 2.10.3 Epoxy 36 36 3. PHOTOLITHOGRAPHY 3.1 MASK LAYOUT 38 3.1.1 Mask Design 38 3.1.2 Art Work 38 3.1.3 Layout Example 40 3.2 PHOTO REDUCTION LIMITATIONS 40 3.2.1 Reduction Theory 40 3.2.2 Optimum Aperture 42 3.2.3 Resolution Limits 42 3.2.4 Alignment Limits 42 3.3 FABRICATION OF PHOTO MASKS 44 3.3.1 3.3.2 Reduction Techniques Step-and-Repeat Techniques 44 46 3.3.3 Multi-Lens Techniques 46 3.3.4 Pinhole Techniques 46 3.4 PHOTO MASKS 46 3.4.1 3.4.2 Mask Copies Chrome Masks 46 50 3.4.3 Metal Masks 50 4. SILICON WAFER PROCESSING 4.1 LOCALIZED DIFFUSION CONTROL 51 4.2 MAJOR PROCESS VARIATIONS 54 4.3 ISOLATION METHODS 54 4.3.1 Diffused Collector Isolation (or Triple Diffusion Process) 54 4.3.2 4.3.3 All Diffused Isolation Diffused Isolation in Epitaxial Layer 56 56 4.3.4 Dielectric Isolation 56 4.3.5 4.3.6 Resistive Isolation Beam-Lead Isolation 56 56 4.4 THE NPN SILICON PROCESS 56 4.4.1 Starting Material 56 4.4.2 Oxidation 56 4.4.3 Buried Layer 58 4.4.4 Epitaxial Layer 58 4.4.5 Cleaning 58 4.4.6 Re-Oxidation 58 4.4.7 Isolation Diffusion 58 4.4.8 Base Diffusion 58 4.4.9 Emitter Diffusion 60 4.4.10 Pre-Ohmic Etch 60 4.4.11 Metalization 4.4.12 Backside Preparation 60 64 4.5 4.6 DIELECTRIC ISOLATION SILICON WAFER PROCESSING PROBLEMS 64 64 vi

4.7 CLEANLINESS AND CONTAMINATION CONTROL 66 4.7.1 De-Ionized Water 66 4.8 PROCESS GASES 66 4.9 DEGREASING 66 4.10 DUST AND ENVIRONMENTAL CONTROL 66 5. PROCESS CONTROL 5.1 DIFFUSION PROCESS CONTROL 68 5.1.1 Visual Inspection 68 5.1.2 Probing 68 5.2 JUNCTION CHARACTERISTICS 72 5.2.1 Electrical Characteristics of Junctions 7 2 5.2.2 Measurement of Junction Depth 72 5.2.3 Diode Recovery Time 72 5.2.4 Junction Profiles 7 2 5.3 TEST PATTERN CONTROL 74 5.4 RESISTIVITY PROBING 74 5.5 PERFORMANCE OF DEVICES 74 5.6 PROCESS CONTROL CHARTS 76 5.7 YIELD DATA 76 5.8 ASSEMBLY PROCESS CONTROL 76 5.8.1 Device Probing 76 5.8.2 Circuit Probing 78 5.8.3 Final Test 78 5.9 MECHANICS OF PROBING 78 5.9.1 Probing Joints 78 5.9.2 Probing Techniques 8 2 5.10 SUMMARY 82 6. THIN FILM PROCESSES 6.1 TYPES OF THIN FILM CIRCUITS 8 3 6.1.1 Substrates 83 6.1.2 Thin Films 83 6.1.3 Thick Films 83 6.2 CHARACTERISTICS OF THIN FILM COMPONENTS 84 6.2.1 Inductance 84 6.2.2 Thin Film Contact Parasitics 84 6.2.3 Thin Film Contact Resistance 84 6.2.4 Thin Film Geometries 86 6.3 PATTERNING THIN FILMS 86 6.3.1 Photolithography 8 6 6.3.2 Metal Masks 86 6.3.3 Silk Screen 88 6.4 THIN FILM RESISTORS 88 6.4.1 Sheet Resistance 88 6.4.2 Temperature Coefficient of Resistance 88 6.4.3 Thin Film Versus Diffused Resistor Parasitics 88 6.4.4 Frequency Response 88 6.4.5 Tolerance 90 6.5 FILM RESISTOR MATERIALS 90 6.5.1 Nichrome 9 2 6.5.2 Cermets 92 6.5.3 Tantalum. 92 6.6 THIN FILM CAPACITORS 92 6.6.1 Diffused Capacitors 94 6.6.2 MOS Capacitors 94 6.6.3 Compatible Capacitors 96 6.7 FABRICATION PROCEDURES 96 6.8 COMPLETE THIN FILM CIRCUITS 98 6.9 THIN FILM FABRICATION SYSTEMS 98 vii

6.9.1 Vacuum Deposition 98 6.9.2 Cathode Sputtering 102 6.9.3 Vapor Plating 102 6.10 SUMMARY 102 7. INTEGRATED CIRCUIT ASSEMBLY 7.1 BASIC ASSEMBLY TECHNIQUES 104 7.2 CIRCUIT PROBING 104 7.3 SCRIBING 104 7.4 PACKAGES 104 7.4.1 TO-5 108 7.4.2 Fiat Packages 108 7.4.3 7.4.4 Special Packages Epoxy Packages 108 108 7.5 DIE BONDING 108 7.5.1 7.5.2 Metal Packages Glass Packages 108 112 7. 6 WIRE BONDING 112 7.6.1 7.6.2 Wire Properties Thermal Compression Wedge Bonding 112 112 7.6.3 Ball Bonding 116 7.6.4 Stitch Bonding 116 7.6.5 Ultrasonic Bonding 116 7.7 7.8 ENCAPSULATION TESTING 116 116 7.9 SILICON MONOLITHIC ASSEMBLY 122 7.10 MULTI-CHIP ASSEMBLY 7.10.1 Layout 122 122 7.10.2 Ceramic Preparation 122 7.10.3 Component Testing 124 7.10.4 Assembly and Testing 124 7.11 THIN FILM ASSEMBLY 7.12 ASSEMBLY CONSIDERATIONS 124 124 7.13 NEW TECHNIQUES 128 7.13.1 Beam Leads 128 7.13.2 Ultrasonic Flip Chip 128 7.13.3 Low Cost Packaging 128 7.14 ASSEMBLY FACILITIES 128 7.14.1 General Considerations 128 7.14.2 Laboratory Facilities 129 7.14.3 Major Capitol Equipment for Assembly 129 8. TESTING COMPLETED INTEGRATED CIRCUITS 8.1 THE GOALS OF INTEGRATED CIRCUIT TESTING 130 8.1.1 The Black Box Concept 130 8.1.2 New Testing Concepts 130 8.2 TESTING STANDARDS 8.2.1 Reference Documents 132 132 8.2.2 Test Conditions 132 8.3 TEST SET-UP 1^4 8.4 PERFORMANCE TESTS 8.4.1 Component Parameters 134 134 8.4.2 Input Measurements 134 8.4.3 8.4.4 Loading Speed of Operation 134 138 8.4.5 Noise Immunity 138 8.5 TEMPERATURE EFFECTS ON PERFORMANCE 8.5.1 Component Parameters and Temperature Variations 138 138 8.5.2 Integrated Circuit Characteristics as a Function of Temperature... 138 viii

8.5.3 Selection of Integrated Circuits 142 8.6 PHYSICAL TESTS 142 8.7 TESTING SYSTEMS 142 8.8 TEST SYSTEM ACCESSORIES 146 8.8.1 Integrated Circuit Holders 146 8.8.2 Environmental Test Jigs 146 8.9 COMMON TESTING ERRORS 146 9. BASIC INTEGRATED DESIGN CONSIDERATIONS 9.1 SILICON MONOLITHIC DESIGN CONSIDERATIONS 150 9.2 DIFFUSED RESISTORS 150 9.3 INTEGRATED CAPACITORS 154 9.3.1 Junction Type Capacitors 154 9.3.2 Oxide Type Capacitors 156 9.4 INTEGRATED TRANSISTORS 156 9.4.1 Diffused Transistor Characteristics 156 9.4.2 Lateral PNP Transistors 158 9.5 INTEGRATED DIODES 158 9.6 INTEGRATED INDUCTORS 158 9.7 COMPATIBLE INTEGRATED CIRCUIT CONSTRUCTION 158 9.7.1 Compatible Resistor Techniques ; 160 9.7.2 Compatible Capacitors 160 9.7.3 Compatible Transistors 160 9.8 MULTI-CHIP DESIGN CONSIDERATIONS 160 9.9 THIN FILM CIRCUIT DESIGN 162 9.9.1 Resistors 162 9.9.2 Capacitors 162 9.9.3 Transistors 162 9.10 COST CONSIDERATIONS 162 9.10.1 Area Considerations 166 9.10.2 Tolerance Considerations 166 9.11 AVAILABLE CIRCUIT ELEMENTS 166 9.11.1 Resistors 166 9.11.2 Capacitors 166 9.11.3 Transistors 168 10. THE MATHEMATICS OF INTEGRATED CIRCUIT DESIGN 10.1 THEORY 169 10.1.1 Wave Equations 169 10.1.2 Band Gap 170 10.1.3 Carrier Concentration 170 10.2 MATERIAL PROPERTIES 172 10.2.1 Mobility 172 10.2.2 Lifetime and Diffusion Length 172 10.2.3 Resistivity 172 10.2.4 Dielectrics 174 10.3 PN JUNCTION THEORY 174 10.3.1 Junctions at Equilibrium 174 10.3.2 Depletion Layer 174 10.3.3 Junction Capacitance 176 10.3.4 Diode Equation 17 6 10.3.5 Reverse Current 178 10.3.6 Forward Voltage 178 10.3.7 Breakdown Voltage 178 10.4 TRANSISTOR CHARACTERISTICS 180 10.4.1 Gain and Transconductance 180 10.4.2 Frequency Calculations 184 10.4.3 PNPN Action 188 10.5 MONOLITHIC DIODE DESIGN 188 10.6 RESISTOR DESIGN 188 ix

. 10.7 CAPACITOR DESIGN 190 10.7.1 The PN Junction Capacitor 190 10.7.2 Silicon Dioxide Capacitor Design 190 10.8 SUMMARY 192 11. DIGITAL INTEGRATED CIRCUITS 11.1 BASIC LOGIC DESIGN PRINCIPLES 193 11.1.1 Binary Numbers 19 3 11.1.2 Numerical Codes 196 11. 1.3 Binary Arithmetic 196 11.2 LOGIC ELEMENTS 196 11.2.1 Application of Basic Elements 196 11.2.2 Positive-Negative Logic Systems 196 11.2.3 NAND-NOR Functions 200 11.2.4 Memory Elements (Flip-flops) 11.3 BOOLEAN ALGEBRA 200 200 11.4 SIMPLE LOGIC CIRCUITS 11.5 INTEGRATED LOGIC CIRCUITS 204 204 11.5.1 Direct Coupled Transistor Logic (DCTL) 204 11.5.2 11.5.3 Resistor Transistor Logic (RTL) Resistor Capacitor Transistor Logic (RCTL) 204 206 11.5.4 11.5.5 Diode Transistor Logic (DTL) Transistor Transistor Logic (TTL) 206 206 11.5.6 11.5.7 Current Mode Logic Complementary Transistor Logic (CTL) 208 208 11.5.8 Logic Circuit Variations 212 11.6 FLIP-FLOP CIRCUITS 11.6.1 Binary Element 212 214 11.6.2 JK Flip-Flop 214 11.7 CIRCUIT PERFORMANCE 216 11.7.1 Shift Registers 216 11.7.2 Binary Counters 216 11.7.3 Propagation Delays 220 11.7.4 Noise Immunity 222 11.8 COMPARISON OF CIRCUIT SYSTEMS 226 11.9 NEW LOGIC CIRCUIT DESIGN 228 12. LINEAR INTEGRATED CIRCUITS 12.1 BASIC LINEARY CONSIDERATIONS 230 12.1.1 Systems Considerations 230 12.1.2 Minimize Bias Current 230 12.1.3 Shielding Offered by Package 232 12.2 LINEAR INTEGRATED DESIGN TECHNIQUES 232 12.2.1 Bias Point Stabilization 232 12.2.2 Direct Coupling 232 12.2.3 Differential Input 234 12.2.4 Capacitors and Capacitance Multipliers 234 12.2.5 Frequency Response 236 12.3 CLASSES OF LINEAR CIRCUITS 12.3.1 Differential Amplifiers 236 236 12.3.2 Audio Amplifiers 240 12.3.3 12.3.4 Video Amplifiers Band Pass Amplifier 240 240 12.3.5 Miscellaneous Linear Circuits 240 12.4 SPECIAL CIRCUIT CONFIGURATIONS 12.4.1 Darlington Amplifier 240 240 12.4.2 RF Grounded Collector Circuits 242 12.4.3 Pulsed Power Supplies 242 12.4.4 12.4.5 Totem Pole Circuit Designs Eliminating Transformers 242 242 x

12.5 COMMERCIALLY AVAILABLE INTEGRATED CIRCUITS 246 12.5.1 Video Amplifiers 246 12.5.2 Audio Amplifiers 246 12.5.3 Differential and Operational Amplifiers 246 12.5.4 Servo Amplifiers 250 13. IMPLEMENTING INTEGRATED CIRCUIT SYSTEMS 13.1 WHETHER TO DESIGN WITH INTEGRATED CIRCUITS 252 13. 1. 1 Percent of Integrated Circuits in Systems 252 13.1.2 Timing the Change to Integrated Circuit Design 252 13.2 SYSTEM DESIGN USING INTEGRATED CIRCUITS 256 13.3 SELECTION OF INTEGRATED CIRCUIT PACKAGE 256 13.4 ASSEMBLY OF INTEGRATED CIRCUIT SYSTEMS 260 13.4.1 Printed Circuit Board Layout 260 13.4.2 Printed Circuit Boards 260 13.4.3 Mounting Integrated Circuit Packages 260 13.4.4 Connectors 264 13.5 TOTAL SYSTEM COST 264 13.5.1 Purchase Price of Materials and Assembly 264 13.5.2 Servicing Cost of Completed Equipment 264 13.5.3 Out-of-Service Cost 266 ' 13.5.4 Design and Development Costs 266 13.5.5 Size and Weight 266 13.6 POWER SUPPLIES 266 13.7 THERMAL CONSIDERATIONS FOR INTEGRATED CIRCUITS 268 13.7.1 Thermal Characteristics of Microcircuit Devices 270 13.7.2 Heat Transfer within the Chip 270 13.7.3 Thermal Resistance in the Die Bond 270 13.7.4 Thermal Characteristics of the Case 272 13.7.5 Total Integrated Circuit Thermal Resistance Values 272 13.7.6 System Thermal Considerations 27 2 13.8 MECHANICAL DESIGN 27 2 13.9 NOISE 276 13.10 TESTING AND REPAIRING INTEGRATED CIRCUIT SYSTEMS 276 14. TOLERANCES 14.1 DIFFERENTIAL 279 14.2 PROBABILITY AND NORMAL DISTRIBUTION 280 14.3 MATERIALS 280 14.4 MASKING TOLERANCE 282 14.5 RESISTORS 282 14.6 CAPACITORS 284 14.7 TRANSISTORS 286 14.8 DIODES 287 14.9 TEMPERATURE 287 14. 10 DESIGN TIME AND TOLERANCE 288 14.11 SUMMARY OF TOLERANCE PROBLEMS 288 14.12 COMBINATION OF ERRORS 288 15. PHOTOMASK DESIGN AND LAYOUT 15.1 MONOLITHIC ISOLATION TECHNIQUES 291 15.1.1 Diffused Isolation 291 15.1.2 Dielectric Isolation 291 15.1.3 Other Junctions 291 15.2 COMPONENT GEOMETRIES 294 15.3 RESISTORS 294 15.3.1 Ohms per Square 294 15.3.2 End Effects 294 xi

15.3.3 Thin Film Resistors 298 15.4 CAPACITORS 298 15.5 TRANSISTORS 298 15.6 DESIGN AND LAYOUT STEPS 302 15. 6. 1 Pin Connections 302 15.6.2 Crossovers 302 15.6.3 Isolation Regions 302 15.6.4 Substrate Contacts 302 15.6.5 15.6.6 Layout Required Masks 302 306 15.7 MASTER SLICE CONCEPT 306 15.8 THERMAL CONSIDERATIONS 306 15.8.1 15.8.2 Thermal Matching High Current 306 306 16. SPECIFICATIONS FOR INTEGRATED CIRCUITS 16.1 TESTING 16.1.1 Test Conditions 310 310 16.1.2 Purpose of Testing 310 16.1.3 Testing and Reliability 312 16.1.4 Integrated Circuits vs Discrete Semiconductor Devices 312 16.2 TYPES OF SPECIFICATIONS 312 16.3 MAXIMUM RATINGS 314 16. 3. 1 Power Limitations 314 16.3.2 Voltage Limitations 314 16.3.3 Current Limitations 314 16.4 FUNCTIONAL SPECIFICATIONS 316 16.5 QUALITY ASSURANCE SPECIFICATIONS 316 16.5. 1 Surface and Reliability 316 16.5.2 Reverse and Leakage Current 318 16.5.3 Noise Figure 318 16.6 LIFE TESTS 318 16.6.1 Failure Defined 320 16.6.2 Life Test Monitoring 320 16.7 MECHANICAL AND ENVIRONMENTAL SPECIFICATIONS 322 16.7.1 Dimension 322 16.7.2 Mechanical Tests 322 16.8 HERMETIC SEAL TESTING 322 16.9 STANDARDIZATION 322 17. GENERAL RELIABILITY CONSIDERATION 17.1 17.2 YIELD VS RELIABILITY THE RELIABILITY PROBLEM 325 325 17.2.1 Price vs Yield 325 17.2.2 Proof of Reliability.326 17.2.3 17.2.4 Quality Control in Peripheral Industries Improved Yield, Higher Reliability and Lower Prices 326 326 17.2.5 The Psychology of Reliability 326 17.3 17.4 THE PLANAR PROCESS PROCESS YIELD 328 328 17.5 RAW MATERIAL PREPARATION 328 17.5.1 17.5.2 Material Purification Crystal Structure 328 330 17.5. 3 Preparing Single Crystals 330 17.6 WAFER PREPARATION 330 17.7 EPITAXY 17.7.1 Defects in Epitaxial Layers 332 332 17.7.2 Measurement of Epi Layers 332 17.8 DIFFUSION 17.8.1 Contamination 334 334 xii

17.8.2 17.8.3 Extraneous Doping Sources Diffusion Spikes 334 334 17.9 PHOTO-LITHOGRAPHY 334 17.9.1 Handling 336 17.9.2 17.9.4 Resolution Masks 336 336 17.9.5 17.9.6 Pinholes Polymerization 336 338 17.9.7 Etching 338 17.9.8 Photoresist Adherence 338 17.9.9 Swelling, Stripping or Tearing 338 17.9.10 Clean-up 338 17.10 METALIZATION 338 17.10.1 17.10.2 Tearing Metalization Adherence 338 338 17.10.3 17.10.4 Peeling and Scratching Chemical Reaction 340 340 17.11 DICING 17.11.1 Scribing 340 340 17.11.2 Breaking 340 17.12 MOUNTING 340 17.13 INTERCONNECTION 17.13.1 Thermocompression Bonds 342 342 17.14 17.13.2 BURN-IN Loose Wires 342 342 17.15 SUMMARY 342 78. RELIABILITY SPECIFICATIONS 18.1 THE PROMISE OF INTEGRATED CIRCUIT RELIABILITY 344 18.2 THE LANGUAGE OF RELIABILITY 344 18.3 PERFORMANCE AND FAILURE DEFINITIONS 346 18.4 THE TIME ELEMENT OF RELIABILITY 346 18.4.1 Life 346 18.4.2 Failure Rate 346 18.4.3 Mean-Time-Between-Failures and Mean-Cycles-Between-Failures.. 346 18.5 18.6 MATHEMATICS OF RELIABILITY CONFIDENCE LEVEL 346 350 18.7 RELIABILITY ASSURANCE METHODS 350 18.7.1 18.7.2 Burn-In Life Tests 350 352 18.8 FAILURE ACCELERATION (STEP-STRESS) 352 18.8.1 18.8.2 Temperature Stress Mechanical Stress 354 354 18.8.3 Combinations of Accelerating Factors 354 18.9 PRODUCTION RELIABILITY ASSURANCE AND SPECIFICATIONS 354 18.9.1 Quality Assurance and Reliability 354 18.9.2 Lot Acceptance 354 18.9.3 18.9.4 Product Qualification Line Qualification Concept 356 356 18.10 RELIABILITY RESULTS 356 18.10.1 Compatibility 356 18.10.2 Interconnections 356 18.10.3 Protection of Surfaces and Delicate Parts 358 18.10.4 18.10.5 Handling Problems Low Power 358 358 18.10.6 Component Misapplication 358 18.11 18.12 COMPLEXITY VS RELIABILITY MAINTENANCE AND REPAIR 358 360 18.13 CONCLUSIONS 360 xiii

19. FAILURE ANALYSIS 19.1 PHYSICS OF FAILURE 361 19.2 SEMICONDUCTOR STRUCTURAL FAILURES 361 19.2.1 Structural Defects 361 19.2.2 Local Stress 361 19.2.3 Neutron Radiation Damage 361 19.2.4 Thermal Shock 364 19.3 SEMICONDUCTOR SURFACE FAILURE 364 19.4 CHEMICALLY CAUSED FAILURES 368 19.5 MECHANICAL CAUSES OF FAILURE 368 19.5.1 Pulling Apart 368 19.5.2 Embrittlement 368 19.5.3 Scratched Metalization 372 19.5.4 Thin Metalization 37 2 19.6 ANALYSIS PROCEDURE 372 19.7 NEWLY DEVELOPED TOOLS AND TECHNIQUES 372 19.7.1 Thermal Profile or Infra-Red Scanning 37 2 19.7.2 Electron Beam or Micro-Scan System 374 19.8 OBSERVED RELIABILITY TEST RESULTS 374 19.9 EXAMPLES OF FAILURES 374 20. FUTURE CAPABILITIES 20. 1 THE CHOICE BETWEEN INTEGRATED CIRCUITS AND CONVENTIONAL COMPONENT ASSEMBLIES 381 20.2 DESIGN OF INTEGRATED CIRCUITS 381 20.3 TESTING AND SPECIFYING INTEGRATED CIRCUITS 38 2 20.4 THE 'MAKE OR BUY' DECISION 38 2 20.5 THE ASSEMBLY OF INTEGRATED CIRCUITS 38 2 20.6 TOTAL SYSTEMS RELIABILITY 383 20.7 THE COMPLETED INTEGRATED CIRCUIT EQUIPMENT IN THE ELECTRONIC MARKET PLACE 38 3 20.8 PRESENT-DAY INTEGRATED CIRCUIT PERFORMANCE 383 20.9 FUTURE CAPABILITY OF INTEGRATED CIRCUIT TECHNOLOGY 38 3 20.9. 1 Frequency Response and Speed 383 20.9.2 Frequency Selection 384 20.9.3 High Voltage High Power 384 20.10 PRESENT TECHNOLOGY INDICATORS 386 20.11 CONCLUSIONS 386 xiv