Design and Analysis of a WLAN CMOS Power Amplifier Using. Multiple Gated Transistor Technique

Design and Analysis of a WLAN CMOS Power Amplifier Using Multiple Gated Transistor Technique Liu Hang, Boon Chirn Chye, Do Manh Anh and Yeo Kiat Seng Division of Circuits and Systems, School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798 Abstract This paper focused on 5.2GHz highly integrated Power Amplifier for IEEE 802.11a WLAN application. Multiple gated transistor (MGTR) technique was employed to improve linearity. A new approach for choosing the bias voltage of auxiliary transistor by analyzing the shift of gate bias is used in the design. The simulated results of the proposed two-stage differential power amplifier indicate 25.28 dbm P 1-dB, 32.87% PAE and 26.18 dbm saturated output power with a 5.2 db P 1-dB improvement compared to conventional single transistor amplifier. Keywords: CMOS power amplifer, class-ab, WLAN, high linearity, MGTR. I. INTRODUCTION Linearity plays an important role in Radio Frequency (RF) systems because nonlinearity causes many problems, such as harmonic generation, gain compression, desensitization, blocking, cross modulation and intermodulation, etc. [1]. Among various distortions, even-order distortion caused by even-order nonlinearity can easily be reduced by adopting a differential signal processing architecture [2]. However, it is difficult to reduce odd-order distortion. The third-order intermodulation distortion is the most dominant nonlinearity component among odd-order distortions. The performance measure for this nonlinearity is usually expressed by the 1-dB compression point (P 1-dB ) and input/output third order interception point (IIP 3 /OIP 3 ). The orthogonal frequency division multiplexing (OFDM) based wireless local area network (WLAN) standard uses non-constant envelope modulation. For OFDM, the linearity of the power amplifier (PA) is a key parameter as it is closely related to power consumption and distortion. Thus class-ab PAs are widely used in wireless transceiver designs due to their high linearity and relatively high efficiency. This paper utilized the multiple gated transistor (MGTR) technique in the design of this two-stage differential class-ab PA to improve the linearity, achieving P 1-dB of 25.28 dbm with 32.87% PAE, saturated output power (P SAT ) of 26.18 dbm and OIP 3 of 28.86 dbm at simulation level. Comparisons with existing works are presented in section IV. The relationship between auxiliary transistor gate bias voltage and linearity performance is

carefully studied. This paper is organized as follows: in section II-A, the definitions of P 1-dB and IP 3 are reviewed, and section II-B gives an introduction of the MGTR technique. In section II-C, large signal effect and gate bias shift is discussed. Section III first gives the description of the proposed PA, followed by a discussion on selection of bias voltage of auxiliary transistor with analysis in section III-A and a brief discussion on other design considerations in section III-B. Simulation results and comparisons with other works are presented in section IV. Section V summarizes the paper. II. ILLUSTRATION OF MGTR TECHNIQUE A. Review of P 1dB and IP 3 The nonlinear I DS -V GS relationship of a FET can be modeled by means of Taylor series expansion around a particular V G bias point as follows [3]: (1) where, and are first order, second order and third order trans-conductance gain that can be represented as follows: ;! ;! ; (2) and with being the load impedance, being the amplitude of the input voltage, the output voltage of fundamental frequency, is given by, (3) It can be easily observed that the fundamental frequency gain variation is caused by the third-order term. When 0, the gain will compress. The point where the gain is compressed by 1 db is called the 1-dB compression point (P 1-dB ). When 0, the linearity is not affected by the third order term. When 0, the gain will expand, leading to the gain waveform bending upward, causing nonlinear gain. The output third order interception point (OIP 3 ) and third order intermodulation (IM 3 ), according to [4], can be written as: OIP (4) IM (5)

B. Introduction to MGTR Technique Figure 1. Schematic showing transistors with MGTR technique In Figure 1, an auxiliary transistor (AT) is placed in parallel to the main transistor (MT) with V G bias. MGTR technique utilizes this AT together with MT to improve the overall linearity [5]. By properly selecting the width (W AT ) and the offset voltage ( ) of AT, the overall can be compensated for a small voltage range [6]. When the transistors are biased at the zero region, the linearity is improved, as shown in Figure 2. W MT represents the width of MT, and both transistors have 0.18µm channel length. 2.5 2.0 1.5 W AT = 250um and =300mV W MT = 1000um compensated g m '' (S/V 2 ) 1.0 0.5 0.0-0.5 region of zero g m '' -1.0-1.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 V G (V) Figure 2. compensation The MGTR technique has already been used in low noise amplifier (LNA) and mixer designs [3, 6-8], where there is no obvious large signal effect and the power delivered to load is relatively low. This technique has also been used in a few RF PAs [9-10]. In order for this technique to be suitable delivering large amount of power, the large signal effect has to be considered. With an exemption to Class-A PA, the conduction angle is less than 360. The gate bias voltage is not constant and is easily shifted out of the zero region. The overall becomes negative with the increasing input signal and the gain is compressed. This means that MGTR technique works well

only for a small voltage range, and is generally not suitable for devices with large input signal, like PA. C. Illustration of Gate Bias Voltage Shift The ideal I-V characteristic of a MOSFET consists of two regions, cut-off region with zero drain current and linear region with constant transconductance G. Figure 3 shows an ideal MOSFET with a sinusoidal input signal of amplitude and biased at V G. The threshold voltage is V TH and the peak drain current is I P. Where Figure 3. Operation of transistor [11] (6) ( ) ( ) According to [12], the drain DC current can be expressed as: (9) Thus, the new bias point and the bias shift can be written as: (10) Δ (11)

In Figure 3, is shown for illustration purpose. In actual case, this is not necessarily true. In other words, the equations are still valid when and 0. 0.5 0.4 = 0.9 V = 0.6 V = 0.3 V 0.3 V G (V) 0.2 0.1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 V G (V) Figure 4. Δ vs. for different signal level Figure 4 shows a plot of Δ vs. with 0.4V. It can be seen that larger leads to larger Δ, and with same, higher leads to smaller Δ. When, the transistor is always off and Δ is invalid. When, the transistor is always on and there is no bias shift. The amplifier enters Class-A mode of operation. III. POWER AMPLIFIER DESIGN The proposed Class-AB PA was designed using Globalfoundries 0.18µm IC technology with 1.8V supply voltage. The proposed schematic of the PA is shown in Figure 5. The input and output matching were achieved by C 1, C 2, L 1. L 2. C 7, C 8 and L 7 were for output matching. L 3-6 were RF chokes to feed DC current and bias the transistor. All transistors use resistive gate bias. All transistors have 0.18µm channel length and the widths are: gain stage transistors M 1,2 =600µm, MTs M M1,M2 with W MT =1000µm and ATs M A1,A2 with W AT =800µm. Bias voltages are selected as V Bias = 550mV, V G = 800mV and = 380mV. DC consumption is 214mA. The output stage is carefully designed with a study on the effect of various on linearity. All simulations are performed at 5.2GHz of frequency.

V DD L 3 L 5 L 6 L 4 R 3 R 4 RF IN + C 1 C 5 M 1 M M1 M A1 M M2 C 7 C 8 M A2 C 6 M 2 C 2 RF - IN L 1 R 1 C 3 R 5 L 7 C 4 R 6 R 2 L 2 RF OUT + RF OUT - Figure 5. The schematic of proposed PA A. Auxiliary Transistor Offset Voltage Selection The choice of of AT is as follows: with W MT fixed at 1000µm and V G fixed at 0.8V (Class-AB mode), is varied and the overall gain is analyzed. W AT can be altered to reduce or increase the value of to achieve flat gain. 2.5 g m '' (S/V 2 ) 2.0 1.5 1.0 0.5 0.0-0.5-1.0 Main Peak Secondary Peaks with = 800mV 1000um 800um 600um 400um 200um with W AT = 800um =200mV =380mV =600mV =800mV -1.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 V G (V) Figure 6. The relationship between W AT, and Figure 6 is a plot of the overall with various W AT and. It can be seen that the main peak is almost unchanged as W MT is fixed. The position of the secondary peak is determined by, and the height of the secondary peak is determined by W AT. When is small, the amplifier is always on and the bias voltage is not changed. As increases, the bias voltage is shifted as illustrated in Figure 4. As a result, is changed.

8 6 = 200 mv = 380 mv = 600 mv = 800 mv Peak gain for = 380 mv Gain (db) 4 2 0-2 -30-20 -10 0 10 20 30 Output Power (dbm) Figure 7. Gain vs. output power for different Figure 7 shows the gain vs. output power from simulation. The V TH is approximately 0.45V. It can be seen that for a low = 200mV, the gain and the P 1-dB are both improved. However, as is small, the bias of AT V G is high and the significant increase in DC consumption is undesirable. For larger where, the AT is off for small and there is no extra DC current. Comparing the remaining three curves, the = 380mV curve is chosen as the offset voltage used in this design, as it provides higher P 1-dB with acceptable gain ripple. For = 600mV, the gain expansion is significant. For = 800mV, the gain compress first, and then expand and compress again. The gain flatness is poor. 2.5 2.0 1.5 1.0 Secondary peak shifts to the left as increases =1.3V =1.0V =0.7V =0.4V =0.2V =0V g m '' value g m '' (S/V 2 ) 0.5 0.0-0.5-1.0-1.5-2.0 0.7 0.8 0.9 V G (V) Figure 8. Shift of V G, effective and variation at =380mV

Figure 8 illustrates how the gain plot for = 380mV in Figure 7 is generated. It shows the bias shift of both MT and AT, and the change in overall. Bias shift in MT is observed as an increase of the operating point V G, from 0.8V at 0 to about 0.9V at 1.3V. The bias shift in AT is observed as an increase in V G. From Figure 4 it can be seen that as AT is biased lower than MT, the bias shift is more significant, which means Δ and the effective is decreasing. As seen in Figure 8, the secondary peak is shifting towards left as increases, indicating a decreasing effective. The is shown with respect to, and is redrawn with respect to in Figure 9. 1.5 Peak g m '' = 1.208 g m '' IM 3 1.2 1.0 0.8 0.5 0.4 g m '' (S/V 2 ) 0.0 Peak IM 3 = 0.01625 0.0 IM 3 (A) -0.5-0.4-1.0-0.8-1.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 (V) -1.2 Figure 9. and IM 3 vs. Figure 9 shows a plot of and IM 3 vs.. It can be seen that with increasing, the overall varies from positive to negative, causing the overall gain to expand and then compress. It can be seen that the maximum occurs at = 200mV which can also be observed in Figure 8. The maximum gain variation occurs at = 400mV corresponding to P out = 18.09 dbm, which is shown in Figure 7 and Figure 12. If the same analysis is performed on = 600mV, the peak IM 3 will be larger than in Figure 9, and the gain expansion is more significant as seen in Figure 7. If this analysis is performed on = 800mV, a negative-positive-negative can be observed, and the gain compresses, expands and compresses again as shown in Figure 7. By analyzing the dynamics of and the gain plot, a new design approach is established for AT s bias voltage selection. Optimization can be achieved by analyzing the effect of and W AT on under various. The conclusion drawn from this analysis is that while the initial value of with no input is important for LNA and mixer designs, the value when large signal is applied is far more useful in

PA design. Large signal effect or gate bias shift must be taken into account for PA design when MGTR technique is applied. B. Other Design Considerations The output matching network is designed for maximum power transfer. Load-pull measurement is performed to find the optimum load impedance and the output matching network transforms the optimum load impedance to a 100 Ω differential port. The first gain stage is designed to provide some the voltage gain. Inter-stage matching is achieved by ac coupling, and input matching is achieved by conjugate matching the input impedance to 100 Ω differential source port. IV. SIMULATION RESULTS The PA is designed using Globalfoundries 0.18 µm IC technology. The simulation is achieved using Cadence and based on the device models provided by the foundry. Capacitors are metal-insulator-metal (MIM) type and inductors are symmetric, center-tapped with 6 layer metal. This PA operates at 5.2GHz under 1.8V voltage supply. Figure 10 shows the results of small signal S-parameter analysis. Good return loss can be achieved for WLAN first band (5.15-5.25 GHz). 20 15 S11 S21 S22 10 S-Parameter (db) 5 0-5 -10-15 -20-25 2.0 4.0 6.0 8.0 Frequency (GHz) Figure 10. S-parameter of proposed PA Figure 11 shows the output power and PAE vs. the input power. An output P 1-dB of 25.28 dbm is observed at an input power of 10.5 dbm, with 32.87% PAE.

30 Output Power PAE 40 Output P 1dB =25.2796 dbm 20 30 Output Power (dbm) 10 0-10 PAE=32.87% 20 10 PAE (%) -20 0-30 -40-30 -20-10 0 10 20 Input Power (dbm) Figure 11. Output power and PAE vs. Input power The gain and DC current vs. output power is shown in Figure 12. In this figure, the gain is compared with an amplifier utilizing the MT alone with identical size and bias. It can be seen that both the P 1-dB and P SAT are improved, with 18% more DC current at 20 dbm output power. When the device is delivering relatively small amount of power, it consumes no additional DC current. This explains why the OIP 3 performance is not improved: as the method for determining OIP 3 is based on extrapolation of first and third order terms of small input signal, where the auxiliary transistor is off, OIP 3 remains the same as single transistor amplifier. Gain (db) 17 16 15 14 13 12 11 10 16.14dB 15.8dB MGTR gain MT alone gain P out =20.07dBm, Gain=15.14dB P out =25.29dBm, Gain=14.8dB 18% more DC current at 20 dbm output power with MGTR -30-20 -10 0 10 20 30 Output Power (dbm) MGTR current MT alone current Peak gain 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 DC current (A) Figure 12. Gain vs. output power

The performance of the proposed PA is summarized in Table I and comparisons with recent published works are shown in Table II. All designs are based on 0.18µm IC technology. It can be seen that for this work, the P 1-dB is closest to P SAT, which means the circuit is more linear and thus the PAE at P 1-dB is much higher. TABLE I. SIMULATED RESULTS Parameter Value Center Frequency (GHz) 5.2 Supply Voltage (V) 1.8 P SAT (dbm) 26.18 P 1-dB (dbm) 25.28 PAE @ P 1-dB (%) 32.87 OIP 3 (dbm) 28.86 Power Gain (db) 15.8 DC consumption (mw) 385 DC consumption at P 1-dB (mw) 994 TABLE II. PERFORMANCE COMPARISONS WITH RECENT PUBLISHED PAS Frequency (GHz) P SAT (dbm) P 1-dB (dbm) OIP 3 (dbm) PAE (%) Design Features Supply Voltage (V) Refs. 5.25 20.9 18.8 28.6 20.1 2-stage cascoded differential 2.4 [13] 5.25 19.5 16 27 32 * 2-stage push-pull differential 3.3 [14] 5 24.1 21.8 N/A 13.1 3-stage differential 1.8 [15] 5 26.5 20.8 N/A 26.7 * 2-stage differential 3.3 [16] 5.2 26.18 ** 25.28 ** 28.86 ** 32.87 ** 2-stage differential 1.8 This work * indicates maximum PAE instead of PAE at P 1-dB ** indicates simulation results instead of measured results V. CONCLUSIONS The design and analysis of a low-voltage fully-integrated CMOS Power Amplifier has been presented. The simulation results show that it is suitable for 5.2GHz WLAN application. The proposed design offers a power gain of 15.8 db and P 1-dB of 25.28 dbm with 32.87% PAE under 1.8V supply. It is capable of delivering high linear output power with high efficiency. By studying the gate bias shift and change in, a new design approach is established for selecting the auxiliary transistor bias voltage, and thus enhancing the linearity performance.

ACKNOWLEDGEMENT We wish to acknowledge the funding support for this project from Nanyang Technological University under the Undergraduate Research Experience on CAmpus (URECA) programme. REFERENCES [1] B. Razavi, RF microelectronics. NJ: Prentice-Hall, 1998. [2] N. Ilku, K. Bonkee, and L. Kwyro, "Single-ended differential amplifier and mixer circuits utilizing complementary RF characteristics of both NMOS and PMOS," in IEEE MTT-S International, Microwave Symposium Digest, 2003, pp. A117-A120. [3] M. Rajashekharaiah, P. Upadhyaya, and H. Deukhyoun, "Enhanced gm3 cancellation for linearity improvement in CMOS LNAs," in IEEE International Symposium on Circuits and Systems, 2006, pp. -4243. [4] K. Kundert. (2002, Accurate and rapid measurement of IP2 and IP3. The Designer's Guide Community. Available: www.designers-guide.org [5] K. Bonkee, K. Jin-Su, and L. Kwyro, "A new linearization technique for MOSFET RF amplifier using multiple gated transistors," Microwave and Guided Wave Letters, IEEE, vol. 10, pp. 371-373, 2000. [6] P. Upadhyaya, M. Rajashekharaiah, Z. Yang, H. Deukhyoun, and C. Yi-Jan Emery, "A 5 GHz novel 0.18 um inductor-less CMOS sub-harmonic mixer," in In 2005 IEEE Workshop on Microelectronics and Electron Devices, 2005, pp. 71-74. [7] K. Tae Wook, "A common gate mixer with transconductance nonlinearity cancellation," in IEEE 8th International Conference on ASIC, 2009, pp. 458-460. [8] C. Weyers, P. Mayr, J. W. Kunze, and U. Langmann, "A 22.3dB voltage gain 6.1dB NF 60GHz LNA in 65nm CMOS with differential output," in IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2008, pp. 192-606. [9] L. Chao, A. V. H. Pham, M. Shaw, and C. Saint, "Linearization of CMOS broadband power amplifiers through combined multigated transistors and capacitance compensation," IEEE Transactions on Microwave Theory and Techniques, vol. 55, pp. 2320-2328, 2007. [10] H. Yu-Chun and L. Zhi-Ming, "High power CMOS power amplifier for WCDMA," in IEEE Asia Pacific Conference on Circuits and Systems, 2006, pp. 199-202. [11] L. Besser and R. Gilmore, Practical RF circuit design for modern wireless systems, vol. II. BSN: Artech House, 2004. [12] P. B. Kenington, High-linearity RF amplifier design. BSN: Artech House, 2000. [13] S. H. L. Tu and C. Sky Chang-Hung, "A 5.25-GHz CMOS cascode class-ab power amplifier for 802.11a WLAN," in Internatonal Conference on Microelectronics, 2007, pp. 11-14. [14] W. Wei and Y. P. Zhang, "0.18 um CMOS push-pull power amplifier with antenna in IC package," IEEE Microwave and Wireless Components Letters, vol. 14, pp. 13-15, 2004.

[15] E. YunSeong and L. KwangDu, "A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications," IEEE Microwave and Wireless Components Letters, vol. 14, pp. 504-506, 2004. [16] H. Solar, R. Berenguer, I. Adin, U. Alvarado, and I. Cendoya, "A fully integrated 26.5 dbm CMOS power amplifier for IEEE 802.11a WLAN standard with on-chip "power inductors"," in IEEE MTT-S International, Microwave Symposium Digest, 2006, pp. 1875-1878. Hang Liu was born in Baoding, Hebei, China, in 1988. He is a final year undergraduate student of Nanyang Technological University and will be receiving his bachelor s degree in 2011. His bachelor s degree major is electrical and electronic engineering. His research focuses on low power and high linearity RF front-end design. Chirn Chye Boon received the B.E. (Hons.) (Elect.) in 2000 and Ph.D. (Elect. Eng.) in 2004 from Nanyang Technological University (NTU), Singapore. In 2005, he joined NTU as a Research Fellow and became an Assistant Professor in the same year. Before that, he was with Advanced RFIC, where he worked as a Senior Engineer. He specializes in the areas of radio frequency (RF) circuits and systems design for Biomedical and Communications applications. He is the Programme Director for RF and MM-wave research in the SG$50 millions research centre of excellence, VIRTUS (NTU) since Mar. 2010. He has published more than 40 technical papers and one book in the areas of RF and MM-wave. Manh Anh Do received the B.Sc. degree in physics from the University of Saigon, Ho Chi Minh, Vietnam, in 1969 and the B.E.(Hons.) degree and the Ph.D. degree in electrical engineering from the University of Canterbury, Canterbury, New Zealand, in 1973 and 1977, respectively. Between 1977 and 1989, he held various positions, including as a Design Engineer, Production Manager, and Research Scientist in New Zealand and a Senior Lecturer with the National University of Singapore, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, as a Senior Lecturer in 1989 and obtained the Associate Professorship in 1996 and Professorship in 2001. Between 1995 and 2005, he was Head of Division of Circuits and Systems, NTU. He was the Director of Center for Integrated Circuits and Systems, NTU from 2007 to 2010. He has been a consultant for many projects in the electronics industry and was a key consultant for the implementation of the 200-million-dollar Electronic Road Pricing project in Singapore from 1990 to 2001. He has authored and coauthored 105 papers in leading journals and 140 papers in international conference proceedings. His current research interests include mobile

communications, RFIC design, mixed-signal circuits, and intelligent transport systems. Prof. Do is a Chartered Engineer. He is a Fellow of the Institution of Engineering Technology (IET). He was a Council Member of IET, U.K., from 2001 to 2004 and an Associate Editor for the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES in 2005 and 2006. Kiat Seng Yeo received the B.E.(Hons.) degree in electronics and the Ph.D. degree in electrical engineering from Nanyang Technological University (NTU), Singapore, in 1993 and 1996, respectively. He is currently the Head of the Division of Circuits and Systems and a Professor of electrical and electronic engineering with NTU. He is a recognized expert in CMOS technology and low-power CMOS IC design. He gives consulting to multinational corporations. He is the holder of 15 patents. He has published four books (International editions) and more than 250 papers in his areas of expertise. His research interests include device modeling, low-power circuit design, and RFIC design. Dr. Yeo serves in the organizing and program committee of several international conferences as the General Chair, a Co-chair, the Technical Chair, etc.