Ultra Low-Power 12-bit SAR ADC for RFID Applications

Ultra Low-Power 12-bit SAR ADC for RFID Applications Daniela De Venuto DEE Politecnico di Bari, Italy ddevenuto@polibait Eduard Stikvoort NXP Semiconductors Eindhoven, The Netherlands eduardstikvoort@nxpcom David Tio Castro, Youri Ponomarev NXP Semiconductors Leuven, Belgium youriponomarev@nxpcom Abstract The design and first measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented The comparator and the DAC are optmised for the lowest power consumption The proposed design has a power consumption of 052µW at a bitclock of 50-kHz and of 085µW at 100-kHz with a 12-V supply As far as we know, the Figure-of-Merit of 66 fj/convertion-step is the best reported so far The ADC was realised in the NXP CMOS 014µm technology with an area of 035 mm 2 Only four metal layers were used in order to allow 3D integration of the sensors [4] Products such as this one suggest the possibility that although the price of RFID tags may not decrease sufficiently for all potential tracking applications, sensorenhanced tags may be able to provide increased functionality for the same price as conventional RFID tags To date there are several approaches for incorporating sensing capabilities into RFID Active tags use battery to power their communication circuitry, sensors, and microcontroller Active tags benefit from relatively long wireless range (approximately 30m) and can achieve high data and sensor activity rates Nevertheless high care has to be given to the power management in order to keep the volume of the battery small and increase the lifetime A block diagram of an RFID sensing platform is shown in figure 1 1 Introduction In recent years rapid development of Radio Frequency Idenification (RFID) technology has resulted in a wide variety of applications and devices used for identification and tracking purposes RFID systems typically consist of small low-cost, battery free devices called tags which use the radio signal from a specialized RFID reader for power and communication When queried, each tag responds with a unique identification number by reflecting energy back to the reader through a technique called backscatter modulation Tags are often application specific, fixed function devices that have a range of 10-50cm for inductively coupled devices and 3-10m for UHF tags Traditionally, RFID tags have been used as a replacement for barcodes in applications such as supply chain monitoring, asset management, and building security [1] A number of investigators however, have proposed more ambitious applications that use conventional RFID as a sensor, inferring high order information from object proximity [2, 3] More conventional RFID applications can also benefit from sensor enhanced RFID tags Specific applications for sensor enhanced RFID tags are in [4] and include infrastructure and object monitoring, automatic product tamper detection, identification of harmful agents, and biomedical devices for non-invasive monitoring A commercially available RFID tag for detecting dangerous temperatures in food products during transit is described in Figure 1 RFID TAG The crucial component in the architecture is the AD converter It has to receive the different sensor signals, and to provide high resolution with low power consumption The successive approximation (SA) algorithm is a suitable low-power solution, especially when used for slow input signals (up to about 1 MHz) with 10 to 12 bit resolution [5-6] This paper focuses on the design of a 12-bit SAR ADC The power budget is derived from the specifications of the overall architecture The power consumption should be below 1µW for a bitclock of 100kHz The implementation had to be done in the CMOS 014µm technology of NXP Starting from the specification a promising solution was found that is based on a recently published architecture 978-3-9810801-6-2/DATE10 2010 EDAA

[11, 12] The design and the implementation will be discussed in the next chapters 2 Ultra Low Power SAR ADC Architecture in Cber V stab/2 Clad Figure 2 Implemented 12 bit SAR ADC architecture In figure 2 the architecture here proposed is shown [12] The novelties consist in the comparator and the charge redistribution A/D The cold side of the capacitors of the A/D are connected to ground or to the regulated supply of V stab The hot side of the capacitors is connected to the comparator input The other comparator input is Vref = Vstab/2 At the start of a conversion the input signal is sampled on the hot side of the capacitors while the MSB is 1 and the other bits are 0 When bit k is set, the voltage in the input of the A/D changes with ΔV in with 3 > 8 thermometer coder Compa AD_out bit 0(msb) bit 1 bit 2 bit 3 bit 11(lsb) SAR register Clad2 Clad changes after comparator did the decision Figure 3 shows the timing diagram For each bit, the bit is set, the comparison is made, the register cell is reset and the next register cell is set All clock and timing signals are generated on chip The timing is driven by a single external clock Cladnot bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 comparator gives 1 Figure 3 ADC Timing diagram Figure 4 shows a simulation of two comparisons From top to bottom the analogue input, the start conversion pulse (, Fig3), the A/D output, the comparator output and input are plotted The bit-wise increments in the input of the comparator are clearly visible The comparator input goes to the reference voltage ΔVin=V S C K /(C AD +C ber ) (1) where C K is the bit capacitance of bit k and C AD is the sum of the bit capacitances C AD =C MSB +C bit1 + +C bit11 (2) C ber is a capacitor that determines the input voltage range of the A/D The peak-to-peak input range is given by V in,max V in,min = V S C AD /(C AD +C ber ) (3) In the case of C ber =0 the input range is rail-to-rail In the presented circuit Cber=3 pf and V Stab is 12 V The input range is 0250 0950V The capacitor of the LSB is 1 ff The digital logic of the SAR register and control is realized with a bit-slice architecture For each bit there is a shift register cell and a flip-flop The shift register enables the bit As written above, at the start, the MSB is set, all other bits are zero The output of the comparator is the output of the A/D A delayed clock is used for a latch in the output of the comparator so that the output bit Figure 4 Simulation of the conversion process 3 The latched comparator The comparator is a key component in a SAR A/D Here we use a modified version of the comparator published in [12] Already in [11] a comparator architecture without bias current and with externally applied clock signal has been presented It has a high speed clock and a low input-

referred noise given its power consumption The comparator consists of two stages and capacitors were added to the output nodes of the first stage The circuit presented in [11] is modified into the circuit of Fig5, in which a flip flop of two NOR gates is driven by the input stage That simplifies the circuit wrt the circuit of [11] and somewhat reduces the maximum clock frequency As speed is not an issue for the application in TAGs, we did the simplification The comparator showed a perfect behaviour at 1 MHz current consumption slightly increases with frequency The current consumption is about 11 na/khz bb Clad a b in ref + Δ V - Δt aa Figure 5 Proposed latched comparator Just one clock is used to drive the comparator The comparison starts with the rising edge of the incoming clock When the clock is low, all nodes of the input differential pair are high and the two NOR gates have low ouptuts Caused by the rising input clock the NMOST is switched on and the two PMOSTs are switched off Nodes a and b go low so that the two NOR gates can operate as a flipflop Which one of node a or b goes low first, determines the final state Which of the nodes a and b goes down first is controlled by the input voltage of ΔV Explicit capacitors to nodes a and b proved to be superfluous The output of the two-nor-gate flipflop is given to a couple of latches so that the comparator output does not go down during the low phase of the input clock In the implemented circuit one of the two ouptuts is given to the SAR register and the other one is the output of the A/D The dynamic power consumption with a 12V supply is about 140nW at 100kHz and the static power consumption is about 30nW To validate these results, the comparator was placed on a IC test chip in the NXP CMOS 014 µm technology The area of the comparator is 35µm x 70µm Measurements (see Fig 6) demonstrate the agreement with simulations In the measurements, the resolution of the comparator is shown by adding an offset to the input signal The simulated sensitivity is better than 5µV This is well below the required 250µV needed for the 12 bit AD Measurements of the power consumption as function of the clock frequency are given in figure 7 It shows that the Figure 6 Measured input and output of the comparator Idd(uA) 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 Idd Lineare (Idd) NI OFF 2nd y = 0,0095x + 0,0235 R 2 = 0,9262 0 10 20 30 40 50 60 70 80 CLK (khz) Figure 7 Measured current consumption of the comparator as a function of the bit clock

4 Experimental results of the Low Power ADC Figure 8 shows the layout and pinning of the test IC The the standard digital I/O modules were used Some logic gates and an I/O pin were added for testing the digital circuitry Figure 8 Overview of the A/D test IC The total circuit area is less then 035mm 2 in the NXP 014 um CMOS IC process Four metal layers were used in the design of the A/D An oscilloscope picture of the output bits of the A/D and the start conversion pulse is shown in Fig9 Table 1 shows the current consumption of the digital (I ddd ) and the analog (I dda ) part of the circuit The analogue part icludes the comparator and its latches as well as the circuit for the reference voltage The digital part consists of the timing module and the SAR The measurements show a current of 08 µa at a bit clock of 100 khz The measurements revealed an input range of 250mV - 950mV Table 1 Bias Current versus bit-clock frequency Bit clock [khz] Idda [na] Iddd [na] 125 180 110 25 190 150 375 210 200 50 220 215 625 230 300 75 240 340 875 250 390 100 270 440 1125 280 490 125 290 530 250 410 1000 Figure 10 shows the reconstructed sine-wave and its FFT The second and third harmonic were at 68 dbc and -675 dbc respectively The 0dB line refers to the maximum DC input level of the A/D Figure 11 shows the reconstructed sine-wave and the spectrum when the input signal is 50mVpp In this case the third harmonic is at -70dBc The nonlinear distortion may relate to the relatively large input range of the A/D and the protection diodes in the analogue input The histogram test (see Fig12) is based on a clipped sinewave It shows a DNL of +14/-10 LSB, which is almost the value for 11 bits The measurements set-up allows a maximum number of samples of 2046, for this reason the evaluations have been done over 32 averages Figure 9 Measured AD output (red) and the sampling clock (blue) Figure 10 Reconstructed sine wave (top) and the FFT (below) Input frequency is 500 Hz

power supply of 12V The bit clock was designed to be 100 khz and the sample rate 625 khz The charge redistribution architecture enabled efficient power management, so that the power consumption scales linearly with the sampling rate The low power consumption relates to the supply voltage of 12 V and low operating frequency The latched comparator and the charge redistribution A/D efficiently use the current As a result we demonstrated an up-to-date Figure-of-Merit of 66 fj per conversion step The measurements refer to the first silicon and improvement by redesign is to be expected Figure 11 Evaluation of the harmonic distortion for a sine wave input of 50mVpp Figure 12 Measured histogram and DNL A widely used figure of merit (FOM) normalizes the power consumption of the A/D to the input bandwidth [ 9] and the dynamic range: FOM= P/(2 f in 2 ENOB ) (4) When using this FOM for the presented convertor it gives 665 fj/convertion-step 5 Conclusions A low power A/D for application in sensors and TAGs was presented The circuit is implemented in the standard CMOS 014 um IC process of NXP and operates with a 6 Acknowledgements This work has been carried out under the framework of a NXP Semiconductors project The authors want to acknowledge Mat Simons of ICLab, NXP, Eindhoven for his valuable help with the digital blocks synthesis, and Ibrahim Candan and his colleages of AMOS, NXP, Eindhoven for support during the measurements 7 References [1] R Weinstein: RFID: a technical overview and its application to the enterprise IT Professional 73 (2005) [2] R Want, KO Finskin, A Gujtar, BL Harrison: Briging physical and virtual worlds with electronics tags in proc of ACM SIGCHI, May 1999 [3] M Philipose et al: Interferring activities from interactions with objects Pervasive Computing, IEEE 34 2004 [4] R Want: Enabling ubiquitous sensing with RFID Computer 374, 2004 [5] G Van der Plas, S Decoutere, S Donnay: A 016pJ/Conversion-Step 25mW 125GS/s 4b ADC in a 90nm Digital CMOS Process in Proc Of IEEE Int Solid State Circuits Conference 2006 [6] P Nuzzo, F De Bernardinis, G Van der Plas: Efficient Calibration through Statistical Behavioral Modeling of a High- Speed Low Power ADC 2006 [7] B Ginsburg, AP Chandrakasan: An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC in IEEE Journal of Solid-State Circuits, vol42 No6, June 2007 [8] J Crsninckx, G Van der Plas: A 65fJ/conversion-step 0 to 50MS/s 0 to 07mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS in Proc Of IEEE Int Solid State Circuits Conference Dig Tech Papers, Feb 2007 [9] N Verma, AP Chandrakasan: An Ultra Low-Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes in IEEE Journal of Solid-State Circuits, vol42 No6, June 2007 [10] F Maloberti Data Converter Springer, The Netherlands 2008 [11] M van Elzakker, E van Tuijl, P Geraedts, et al: A 19uW 44fJ/Conversio-step 10b 1MS/s Charge-Redistribution ADC in Proc Of IEEE Int Solid State Circuits Conference 2008 [12] D De Venuto, T Castro, Y Ponomarev, E Stikvoort: Low Power 12-bit SAR ADC for Autonomous Wireless Sensors Network Interface Proc of 3 rd IEEE IWASI 09, Trani, Bari, Italy, 25-26 June 2009