Efficient logic architectures for CMOL nanoelectronic circuits

Efficient logic architectures for CMOL nanoelectronic circuits C. Dong, W. Wang and S. Haruehanroengra Abstract: CMOS molecular (CMOL) circuits promise great opportunities for future hybrid nanoscale IC implementation. Two new CMOL building blocks using transmission gates have been introduced to obtain efficient combinational and sequential logic for CMOL designs. Compared with the existing CMOL circuits, the proposed CMOL designs based on these blocks can achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capabilities. This work significantly advances the applications of CMOL to actual electronic circuits and systems. 1 Introduction Recently, a novel hybrid nanowire/molecular/semiconductor circuit, namely CMOL, was introduced [1 6], consisting of nanowires on top of a CMOS stack. CMOL tries to utilise the advantages of both traditional CMOS and novel devices of nanowire/nanotube. Even though there are many issues that still need to be addressed, it is one of many competing ideas [7 17] that are very promising for future hybrid IC implementation. Among several hybrid structures, CMOL is one promising proposal showing advantages in terms of device density, power consumption and fault tolerance capabilities [1 6]. CMOL structures can be used as logic and memory, by using CMOS inverters and nanowire crossbars (wires and molecular switches) as one basic cell. It may also be reconfigured around defective nanodevices to provide a high defect tolerance because of the high density of nanowire crossbars that may be used for both logic and routing functions. Present CMOL analyses have mainly considered NOR-gate combinatorial logic designs [1, 2] and simple latches [3]. In this Letter, two new CMOL basic cells using transmission gates are introduced. By using these new cells along with the basic inverter cell, efficient CMOL combinational and sequential logic designs can be achieved. This work can significantly advance the design and implementation of CMOL circuits and systems. 2 Existing I-Cell [2] The basic CMOL inverter cell (I-Cell) consists of a CMOS inverter, two CMOS pass transistors, two nanowires and two pins, as shown in Fig. 1a [2]. Three I-Cells (shaded) and two programmable molecular switches (green dots) are used as a two-input NOR gate (Figs. 1b and c). The two molecular switches work as two diodes and will # The Institution of Engineering and Technology 2006 Micro & Nano Letters online no. 20065005 doi:10.1049/mnl:20065005 Paper first received 18th April and in revised form 17th July 2006 The authors are with the Department of Electrical and Computer Engineering, Indiana University Purdue University Indianapolis, 723 West Michigan Street, IN 46202, USA E-mail: ww3@iupui.edu 74 establish an OR function of the two inputs A and B. The inverter output F will be F ¼ A þ B, thus implementing a NOR function. It is noted that the two input cells can be shared with other functions in a circuit. The NOR function will then only require one I-Cell. Using this NOR gate as a building block, different combinational logic functions can be obtained. Several CMOL circuits have demonstrated high device density and speed performances with acceptable power consumption [1 3, 6]. Also, the ON/OFF state of the molecular switches can be used as latches. Using CMOS address lines to access these molecular switches, an array of CMOL cells can then establish a memory block. Furthermore, these programmable switches can be used to reroute around defective parts to provide defect tolerance. During the configuration process, the inverter in an I-Cell is turned off. The pass transistors along with the pins and nanowires may be used to setup a path to program the state of molecular switches or diodes as ON or OFF. Generally, each cell can be connected through a nanowire-molecular switch-nanowire link to other M ¼ 2r 2 2 2r 2 1 cells within a square-shaped connectivity domain around the pin (shaded light-grey in Fig. 1d ). This allows the ability to reconfigure around defective components to ensure very high defect tolerance. For example, the reconfiguration of a 32-bit Kogge-Stone adder may provide the ability to achieve a 99% circuit yield, with as many as 22% of the devices defective [6]. It is noted that due to the uniformity of the nanowire/molecular switch levels of CMOL, nanowires/switches do not need to be precisely aligned with each other and the underlying CMOS stack, thus allowing the use of the existing patterning and formation techniques. 3 Proposed T-Cell and D-Cell Using I-Cells, the existing CMOL circuits can only support NOR gate-based combinational logics. Functions such as transmission gates and tri-state gates cannot be implemented using NOR gates. Some Boolean logics are not as efficient using only NOR gates. In addition, the twoterminal molecular switches can only be implemented as basic latches for a memory array and cannot be linked to a clock signal. Thus, it is not clear how to implement a clock-controlled flip-flop and obtain the design of a sequential logic in CMOL. In this study, we propose two new

Fig. 1 Existing CMOL circuit a CMOL I-Cell b CMOL NOR gate c Schematic diagram of a NOR gate d Connectivity of CMOL cells [2] Reprint with permission CMOL cells, namely transmission gate-based cell (T-Cell) and D flip-flop-based cell (D-Cell), to provide efficient combinational and sequential logic designs. The proposed T-Cell consists of one transmission gate and is generally connected with one basic I-Cell as shown in Fig. 2. The main reason of using one I-Cell and one T-Cell together is to obtain a transmission gate F ¼ Z; S ¼ 0 X; S ¼ 1 where S is the selection signal, X is the input signal and Z is high impedance. The nanowire, pin and molecular switch arrangement of the T-Cell are the same as the I-Cell, so that I- and T-Cells are naturally integrated together, maintaining the high performance and high fault tolerance capabilities of the original CMOL. This configuration can provide more efficient logic designs for multiplexer (MUX), XOR gate, tri-state buffer and full adder than the I-Cell only designs. The equations, schematic diagrams and implementations using I- and T-Cells for these designs are shown in Fig. 3. InFig. 3a, the transistor schematic of the MUX consists of one inverter and two transmission gates, corresponding to three cells. Owing to the limitation of the connectivity, one extra I-Cell is required for the design. Thus, Fig. 3a requires four cells. In Fig. 3b, the extra I-Cell is connected with a T-Cell that is not needed but cannot be used by other circuits. Therefore the XOR gate in Fig. 3b requires six cells instead of four cells required by the transistor schematic. Similar to Figs. 3a and b, the total number of cells required by other designs such as tri-state buffer and full adder is obtained and summarised in Table 1. For the purpose of comparison, the number of cells used by the corresponding original CMOL design is also obtained. For example, the MUX can be implemented using three two-input NOR gates and four inverters Fig. 2 Proposed CMOL transmission gate: one I-Cell and one T-Cell F ¼ Z; S ¼ 0 X; S ¼ 1 ðf ¼ SX 2 þ SX 1 ¼ S þ X 2 þ S þ X 1 Þ which requires seven I-Cells; the XOR gate can be implemented using three two-input NOR gates and three 75

Fig. 3 Efficient designs using I- and T-Cells a 2-input MUX b 2-input XOR gate c Tri-state buffer d Full adder inverters ðf ¼ X 1 X 2 þ X 1 X 2 ¼ X 1 þ X 2 þ X 1 þ X 2 Þ which requires six I-Cells. On the basis of these comparison results in Table 1, we can see that compared with the original CMOL designs, the proposed circuits significantly reduce the number of cells in a range of 18 43%. As shown in Fig. 4, the proposed D-Cell consists of one transmission gate and one inverter. The nanowire, pin and 76 molecular switch arrangement of the D-Cell is the same as that of I- and T-Cells. Generally, two D-Cells and two I-Cells are connected together to implement a D flip-flop function. As shown in Table 1, using I- and T-Cells, a total of 20 cells are needed for one D flip-flop. By using I- and D-Cells, only four cells are required, achieving a reduction of 80% in terms of the number of cells. Since all sequential logic circuits will need D flip-flops in the design, this efficient D flip-flop design is crucial for the application of CMOL in practical circuit designs.

Table 1: Comparison of logic designs using basic CMOL and improved CMOL methods Basic CMOL with I-Cell Number Area of cells required Delay Power dissipation (same speed) Improved CMOL with I-Cell, T-Cell and D-Cell Number Area Delay of cells required Power dissipation (same speed) MUX 7 cells 7 A 0 4 t 0 7 P 0 4 cells 4 A 0 2 t 0 4 P 0 XOR 6 cells 6 A 0 3 t 0 6 P 0 6 cells 6 A 0 2 t 0 6 P 0 Tri-state buffer N/A 4 cells 4 A 0 3 t 0 4 P 0 Transmission gate N/A 2 cells 2 A 0 2 t 0 2 P 0 Full adder 22 cells 22 A 0 6 t 0 22 P 0 18 cells 18 A 0 4 t 0 18 P 0 D flip-flop 20 cells 20 A 0 6 t 0 20 P 0 2 I-Cells and 2 D-Cells 4 A 0 4 t 0 4 P 0 4 Performance analysis We now present a performance analysis for I-, T- and D-Cells. I- and T-Cells each consists of four CMOS transistors. We can estimate the area of these cells as that of two inverters. The cell area is approximately A Cell ¼ (2bF CMOS ) 2 ¼ 64(F CMOS ) 2, where F CMOS is the half-pitch of the CMOS system and the scaler factor b is selected as 4 [3]. For example, when 45 nm CMOS technology is used, the area of one cell, A 0, is approximately 129 600 nm 2 [3]. It is noted that the P-type transistor in an inverter is much larger than the N-type. The area of an inverter is about four times of that an N-type transistor. Although the P-type transistor in one transmission gate is small, the area of such a gate is about two times of an N-type transistor. So is the area of two N-type pass logic transistors [18]. Thus, even though D-Cell consists of six transistors (one inverter, one transmission gate and two pass transistors), we can still consider the area of D-Cell as that of two inverters, which is A 0 for the 45 nm case. Using this value for each cell, area data of different designs are obtained in Table 1. The delay calculation of the I-Cell is derived on the basis of the equivalent circuit from the work of Strukov and Likharev [3] (Fig. 5a). The circuit parameters R on, R wire, R pass, C wire and C in represent: ON resistance of the molecular switch, resistance of the nanowire, resistance of the pulldown pass transistor, capacitance of the nanowire and the load capacitance of next CMOS stage, respectively. The values of these parameters are obtained from the work of Strukov and Likharev [2, 3] and C wire is derived on the basis of the minimum interconnect length. The RC delay of the cell is then determined by the total parallel capacitance C in //C wire and the total parallel resistance of (R on /D þ R wire )//R pass, where // represents parallelism and D is the number of other molecular switches related to the two nanowires. Since C in C wire, the total capacitance depends on C wire. Since (R on /D þ R wire ) R pass [3], the total resistance is approximately R pass. Thus, the simplified RC delay of the I-Cell [2] is given as t 0 logð2iþr pass C wire where I is the gate fan-in. T- and D-Cells are similar to I-Cell, except for the different CMOS logic components. As shown in Figs. 5b and c, the total parallel resistance of the D- and T-Cells are also (R on /D þ R wire )//R pass. The total parallel capacitance of the T-Cell is C in //C wire, where C in of the T-Cell is now the source capacitance for the transistors in transmission gate instead of the gate capacitance. The total parallel capacitance of D-Cell is C in //C in 0//C wire, where C in is the source capacitance of transmission gate and C in 0 is the gate capacitance of the cascaded inverter. Since C in // C in 0 C wire, the total capacitance still depends on C wire. Therefore the delay calculation of I-Cell (1) can be used for D- and T-Cells. The delay of a given circuit will then be determined by the total number of cells required in the critical path. As shown in Table 1, the modified CMOL designs not only require less cells, but also improve the speed or delay in a range of 33 50%. The power consumption of I-, T- and D-Cells are estimated as the sum of static power P on, leakage power P leak and dynamic power P d [3] P ON V 2 DD 2R ser ; P leak ¼ MV 2 DD 2R OFF =D ; P ¼ C wirev 2 DD 4t total where R ser is the serial resistance of R on /D and R wire, D is the total number of molecular switches in one nanowire crosspoint, M is the number of closed crosspoint switches and t total is the single cell RC delay. Using (2), the power density of CMOL design [3] is predicted as P AREA ¼ 200 W/cm 2. Then, the average single cell power consumption can be estimated as ð1þ ð2þ P 0 ¼ P AREA area of cell ¼ 0:2592 mw ð3þ Fig. 4 D flip-flop using two I-Cells and two D-Cells Using (3), the power consumption data of different logic gates based on I-, T- and D-Cells are obtained as shown in Table 1. Since the area of one I-Cell is similar to that of T- and D-Cell, the power consumption data for one cell can be considered as a constant. Therefore compared with the existing designs, the proposed designs with the reduced number of cells can achieve power saving up to 80%. 77

as many as 22% of the devices defective. This shows the defect tolerance capability of the proposed method is similar to that of the basic CMOL method. 6 Conclusion Hybrid CMOL integrated circuits show promise in nanoelectronic research and development. One major challenge towards implementing practical CMOL circuits is the improvement of architectures for digital and mixed-signal CMOL circuits. In this work, by introducing two building blocks based on transmission gates for the first time, efficient CMOL combinational and sequential circuits and new system architectures are obtained. Compared with the existing CMOL circuits, the proposed designs achieve more than 30% improvement in speed and up to 80% improvement in density and power consumption while providing similar fault tolerance capability. This work sets up the groundwork for many future studies utilising CMOS, transmission gate families and other logic families in CMOL designs. 7 References Fig. 5 Equivalent circuits of I-, T- and D-Cells a I-Cell b T-Cell c D-Cell 5 Complete architecture and fault tolerance The performance improvement of the proposed I-, T-, D-Cell structure over the I-Cell only structure is significant for a certain design. Thus, it is useful to integrate both structures together to obtain a new CMOL system architecture. One possible architecture can consist of two banks. The first bank is based on I-Cells only, which is efficient for memory or NOR-gated based logic. The second bank is based on tiles of I-, T- and D-Cells. For example, each tile can consist of 36 cells, four of which in the centre provide a D flip-flop. The surronding 32 I- and T-Cells will efficiently provide combinational designs such as MUX, XOR gate, full adder, as well as tri-state buffer and transmission gates. This proposed CMOL system architecture can provide the high fault tolerant capability as the original CMOL system. Since I-, T- and D-Cells are of the same size and maintain the same nanowire crossbar routing structure, the original CMOL defect tolerance scheme [3] can be used. It is achieved by reconfiguring cell connections around the defect cells in two steps: (1) mapping the desired circuit on the defect-free CMOL structure; (2) rerouting the circuit around defective components. The circuit mapping stage is based on optimisation of NOR gate and transmission gate designs. The rerouting stage needs to consider I-, T- and D-Cells. This design flow is similar to the one in the work of Strukov and Likharev [3], with emphasis on I-, T- and D-Cells. Using this design flow, the reconfiguration of a 32-bit carry-ripple adder has been verified, providing the ability to achieve a 99% circuit yield, with 1 Likharev, K.K., and Strukov, D.: CMOL: devices, circuits, and architectures, in G. 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