DC-DC Converter Design Phase Acceleration with Virtuoso UltraSim Simulator Mohamed Bouhamame, Didier Depreeuw NXP Semiconductors Caen France
Outline Motivations DC-DC converter topology Implementation Ultrasim DC-DC converter setting Simulation & measurement results Conclusions 2
Motivations A Controllable high voltage DC-DC Converter High level of integration Low power consumption Tunable RF filter with High linearity and High selectivity 3
DC-DC converter topology V in Ck Ckn C s D 1 C C s D 2 D 3 C s C s C D n-1 D n C C C out C V = V V + N * * V -V - out in d C + C ck d (C I out + C R L V out Where: s s - N is the number of commutating stages (N=20) - f is the operating frequency of the charge pump (f=16mhz) - C s is the stray capacitance at each node (1fF) - I out is the DC current required to drive the load for a given output voltage How to decrease the output voltage rapidly? ) * f 4
Why Tunable RF Filter? Tracking filter used in traditional TV tuner f max f min = C vmax C vmin ( C p >> C v Antenna ) L 1 L 2 C v C p R V tune =0.8V..28V Provider by the DC-DC Tunable Filters are needed because of : High dynamic range of the received signals Wide input bandwidth (F=[50MHz 870MHz]) 5
Implementation DC-DC UP V out D 1 D 2 D 3 DC-DC DOWN Ckup n Ckup p C 1 C 2 C 3 M diodes N diodes D 3 D 2 D 1 C Fringe capacitor Ckdw n Ckdw p C 3 C 2 C 1 Dickson Charge pump is implemented in 2.8V Bi-CMOS 0.25µm Technology (Break down voltage for collector substrate is B vcs0 =80V ) Stray capacitance C s has been reduced by the shielding done by the poly layer V out < (N+M)*V d (V d is the forward bias voltage of the diode) 6
Implementation R C V out =V tune 15M 1M V ck V ck Ckn Ck Resistors used have a breakdown voltage more than 200V and have a sheet resistance of 2000 /square + - V ref DAC Prog V ref enables to tune the center frequency of the tracking filter(vref =Vout/16) Spectre simulation time is really long! (40000 switching periods are required to capture the power-up (the output voltage starts from 0 volt to reach the steady state of 24 volts) How to decrease the time simulation? 7
What Is Ultrasim? UltraSim is a fast-spice hierarchical circuit simulator (Transistor level) which combines a variety of simulation technologies to allow high-capacity simulation of memories, digital, analog, RF and mixed-signal ICs with spicelike accuracy 8
Ultrasim : Fast SPICE Technology Cadence s Slide 9
Transistor Level Circuit Simulation Overview SPICE: Fast-SPICE: Hier-SPICE: Technologies: Compact models Sparse Matrix Solver Time step, Newton-raphson Technologies: Simplified Models: PWL, Table Matrix Partitioning Event-driven Multi-rate RC reduction Technologies: Fast-SPICE technologies Hierarchy Isomorphism Applications: Block design Analog/MS Pre Layout Tran, AC, Noise, RF 50K device capacity Applications: Large Block Design MS/Digital/Memory Pre-/Post Layout Tran 1M device capacity Applications: Full-chip simulation Analog/MS/D/Memory Pre-/Post Layout Tran 1B+ device capacity 10
UltraSim 3rd Generation Transistor Level Simulator Cadence s Slide 11
UltraSim Simulation Modes 12
UltraSim Multirate simulation Different time steps for partitions High frequency partition : small time step Small frequency partition : bigger time step 13
UltraSim Speed Options Cadence s slide 14
UltraSim Simulation Models Overview The same study of the Id_Vd & Id_Vg differences Is under investigation Simkit MN11 and MOS9 are supported in Ultrasim for the following models: DF DA A Spice 15
DC-DC converter setting the server define below is used : OS: Linux 2.4.21-15.ELhugemem i686 Memory: available 4.1157 GB physical 8.3916 GB Swap: available 3.2410 GB physical 4.1784 GB CPU: CPU0 AMD Opteron(tm) Processor 250 2388.905MHz CPU1 AMD Opteron(tm) Processor 250 2388.905MHz cadence_ic 5.10.41.500.2.26 cadence_ius 5.5.s001 cadence_mmsim 6.0.1.174 We need to set vdd=1.8 to get accurate table model creation!.usim_opt progress_p=1 vdd=1.8 Circuit inventory: Nodes 307 Equations 796 bjt504 76 capacitor 57 diode 101 isource 2 juncap 696 mos1100e 278 phy_res 78 resistor 15 vcvs 2 vsource 6 16
Simulation & measurement results Vout (V) Vout (V) 25 25 20 Ultrasim versus Spectre Less than 0.003% diff 20 15 10 spectre ultrasim 15 10 spectre ultrasim 5 5 measurement 0 0 0,5 1 1,5 2 t (ms) 0 0 0,4 0,8 1,2 1,6 2 t (ms) Using Ultrasim, the circuit simulation time is six times faster with the same accuracy compare to Spectre Simulation time result using local setting 17
Measurement results Vout(V) 31 29 27 25 23 21 19 T=Tnom T=85C T=-20C 1,4 1,75 2,1 2,45 2,8 Voltage output range Output current max Supply current max 0V 30 V 8 µa 1mA Vref (V) When I out =8µA, f=16mhz, N=20, V d =0.6V, C=700fF and C s =1fF, V out =32V The temperature dependency of the output voltage is negligible 18
Die photograph Voltage regulation, Clock generation DC/DC UP DC/DC DOWN Technology : 0.25µm Bi-CMOS ft=40ghz Area : 620µm*262µm 19
Ultrasim Pros & Cons Pros Time saving with the same accuracy Factor 6 with DC DC Converter Would have been a great help on time saving during the design phase Cons Spectre is the reference tool, take care of ultrasim simulation results of a global system for which spectre simulation is not possible Sometimes prohibitive simulation time due to not optimized local settings : use the activity report Transient analog signal, no RF capabilities Bipolar transistors not taken into account in the table model simplification Ultrasim-Verilog : not possible to save / load an intermediate step 20
Conclusions A Controllable High Voltage DC-DC converter has been presented A novel solution has been used to decrease the output voltage rapidly The new discharge system solves the problem of the high tuning voltage requirement for MEMS and SMD variable capacitors The forward bias voltage V d is the main limitation of the output voltage Ultrasim have been a great help on time saving during the design phase Ultrasim allows the exploration of more design configurations, the accuracy is excellent for such Bi-CMOS circuit Ultrasim simulator is a very efficient to make possible bottom-up verification for all IC builder 21
Acknowledgements Jean Robert Tourret, NXP Semiconductors Luca Lococo, NXP Semiconductors Serge Toutain, IREENA André Baguenier, Cadence 22
Thanks for your attention! Any Question?