C695 Digital Output emperature ensor Description he C695 is a JEDEC JC42.4 compliant emperature ensor designed for general purpose temperature measurements requiring a digital output. he C695 measures temperature at least 1 times every second. emperature readings can be retrieved by the host via the serial interface, and are compared to high, low and critical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open drain EVEN pin. he C695 is packaged in space saving DFN package with exposed backside die attach pads (DP). he exposed DP reduces overall thermal resistance, thus providing faster response to thermal changes when compared to OIC, OP or O packages. Features JEDEC JC42.4 Compliant emperature ensor emperature Range: 4 C to +125 C upply Range: 3.3 V ± 1% I 2 C / MBus Interface chmitt riggers and Noise uppression Filters on CL and D Inputs Low Power CMO echnology 2 x 3 x.75 mm DFN Package hese Devices are Pb Free and are RoH Compliant CL 2, 1, V CC C695 EVEN 1 2 V PIN CONFIGURION 1 DFN 8 VP2 UFFIX CE 511K (op View) V CC EVEN CL D For the location of Pin 1, please consult the corresponding package drawing. MRKING DIGRM HMC LL YM HMC = pecific Device Code = ssembly Location Code LL = ssembly Lot Number (Last wo Digits) Y = Production Year (Last Digit) M = Production Month (1 9, O, N, D) = Pb Free Package D V Figure 1. Functional ymbol Pin Name, 1, 2 D CL EVEN V CC V DP PIN FUNCION Function Device ddress Input erial Data Input/Output erial Clock Input Open drain Event Output Power upply Ground Backside Exposed DP at V ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. emiconductor Components Industries, LLC, 211 May, 211 Rev. 5 1 Publication Order Number: C695/D
C695 able 1. BOLUE MXIMUM RING Parameter Rating Units Operating emperature 45 to +13 C torage emperature 65 to +15 C Voltage on any pin with respect to Ground (Note 1).5 to +6.5 V tresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. he DC input voltage on any pin should not be lower than.5 V or higher than V CC +.5 V. he pin can be raised to a HV level compatible with the use of a DDR3 PD device sharing the bus with the. CL and D inputs can be raised to the maximum limit, irrespective of V CC. able 2. EMPERURE CHRCERIIC (V CC = 3.3 V ± 1%, = 4 C to +125 C, unless otherwise specified) Parameter est Conditions/Comments Max Unit emperature Reading Error +75 C +95 C, active range ±1. C Class B, JC42.4 compliant +4 C +125 C, monitor range ±2. C 2 C +125 C, sensing range ±3. C DC Resolution 12 Bits emperature Resolution.625 C emperature Conversion ime 1 ms hermal Resistance (Note 2) J Junction to mbient (till ir) 92 C/W 2. Power Dissipation is defined as P J = ( J )/ J, where J is the junction temperature and is the ambient temperature. he thermal resistance value refers to the case of a package being used on a standard 2 layer PCB. able 3. D.C. OPERING CHRCERIIC (V CC = 3.3 V ± 1%, = 4 C to +125 C, unless otherwise specified) ymbol Parameter est Conditions/Comments Min Max Unit I CC upply Current active 2 I HDN shut down; no bus activity 1 I L I/O Pin Leakage Current Pin at GND or V CC 2 V IL Input Low Voltage.5.3 x V CC V V IH Input High Voltage.7 x V CC V CC +.5 V V OL Output Low Voltage I OL = 3 m, V CC > 2.5 V.4 V 2
C695 able 4..C. CHRCERIIC (V CC = 3.3 V ± 1%, = 4 C to +125 C) (Note 3) ymbol Parameter Min Max Units F CL (Note 4) Clock Frequency 1 4 khz t HIGH High Period of CL Clock 6 ns t LOW Low Period of CL Clock 13 ns t IMEOU (Note 4) MBus CL Clock Low imeout 25 35 ms t R (Note 5) D and CL Rise ime 3 ns t F (Note 5) D and CL Fall ime 3 ns t U:D (Note 6) Data etup ime 1 ns t HD:D (Note 5) Data Hold ime (for Input Data) ns Data Hold ime (for Output Data) 3 9 ns t U: R Condition etup ime 6 ns t HD: R Condition Hold ime 6 ns t U:O OP Condition etup ime 6 ns t BUF Bus Free ime Between OP and R 13 ns i Noise Pulse Filtered at CL and D Inputs 1 ns t PU (Note 7) Power up Delay to Valid emperature Recording 1 ms 3. iming reference points are set at 3%, respectively 7% of V CC, as illustrated in Figure 11. Bus loading must be such as to allow meeting the V IL, V OL as well as the various timing limits. 4. he interface will reset itself and will release the D line if the CL line stays low beyond the t IMEOU limit. he time out count is started (and then re started) on every negative transition of CL in the time interval between R and OP. 5. In a Wired OR system (such as I 2 C or MBus), D rise time is determined by bus loading. ince each bus pull down device must be able to sink the (external) bus pull up current (in order to meet the V IL and/or V OL limits), it follows that D fall time is inherently faster than D rise time. D rise time can exceed the standard recommended t R limit, as long as it does not exceed t LOW t HD:D t U:D, where t LOW and t HD:D are actual values (rather than spec limits). shorter t HD:D leaves more room for a longer D t R, allowing for a more capacitive bus or a larger bus pull up resistor. t the minimum t LOW spec limit of 13 ns, the maximum t HD:D of 9 ns demands a maximum D t R of 3 ns. he C695 s maximum t HD:D is <7 ns, thus allowing for an D t R of up to 5 ns at minimum t LOW. 6. he minimum t U:D of 1 ns is a limit recommended by standards. he will accept a t U:D of ns. 7. he first valid temperature recording can be expected after t PU at nominal supply voltage. able 5. PIN CPCINCE ( = 25 C, V CC = 3.3 V, f = 1 MHz) ymbol Parameter est Conditions/Comments Min Max Unit C IN D, EVEN Pin Capacitance V IN = 8 pf Input Capacitance (other pins) V IN = 6 pf 3
C695 YPICL PERFORMNCE CHRCERIIC (V CC = 3.3 V, = 25 C to +125 C, unless otherwise specified.) 3 5 25 4 2 3 I CC ( ) 15 1 I HDN ( ) 2 1 5 25 25 5 75 1 125 1 25 25 5 75 1 125 MB ( C) MB ( C) Figure 2. ctive Current (I 2 C bus Idle) Figure 3. tandby Current (I 2 C bus Idle, hut down) 4 8 ( C) 3 2 1 1 2 3 Part # 2 Part # 1 CONV (ms) 7 6 5 4 3 4 25 25 5 75 1 125 2 25 25 5 75 1 125 MB ( C) MB ( C) Figure 4. emperature Read Out Error Figure 5. /D Conversion ime 3. 4 2.6 35 V H (V) 2.2 1.8 t IMEOU (ms) 3 1.4 25 1. 25 25 5 75 1 125 2 25 25 5 75 1 125 MB ( C) MB ( C) Figure 6. POR hreshold Voltage Figure 7. MBus CL Clock Low imeout 4
C695 Pin Description CL: he erial Clock input pin accepts the erial Clock generated by the Master (Host). D: he erial Data I/O pin receives input data and transmits data stored in the internal registers. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of CL., 1 and 2: he ddress pins set the device address. hese pins have on chip pull down resistors. EVEN: he open drain EVEN pin can be programmed to signal over/under temperature limit conditions. Power On Reset he C695 incorporates Power On Reset (POR) circuitry which monitors the supply voltage, and then resets (initializes) the internal state machine below a POR trigger level of approximately 2. V, i.e. well below the minimum recommended V CC value. he temperature sensor () powers-up into conversion mode. he internal state machine will operate properly above the POR trigger level, but valid temperature readings can be expected only after the first conversion cycle started and completed at nominal supply voltage. Device Interface he C695 supports I 2 C and MBus data transmission protocols. hese protocols describe serial communication between transmitters and receivers sharing a 2 wire data bus. Data flow is controlled by a Master device, which generates the serial clock and the R and OP conditions. he C695 acts as a lave device. Master and lave alternate as transmitter and receiver. Up to 8 C695 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs, 1, and 2. I 2 C/MBus Protocol he I 2 C/MBus uses two wires, one for clock (CL) and one for data (D). he two wires are connected to the V CC supply via pull up resistors. Master and lave devices connect to the bus via their respective CL and D pins. he transmitting device pulls down the D line to transmit a and releases it to transmit a 1. Data transfer may be initiated only when the bus is not busy (see.c. Characteristics). During data transfer, the D line must remain stable while the CL line is HIGH. n D transition while CL is HIGH will be interpreted as a R or OP condition (Figure 8). R he R condition precedes all commands. It consists of a HIGH to LOW transition on D while CL is HIGH. he R acts as a wake up call to all laves. bsent a R, a lave will not respond to commands. OP he OP condition completes all commands. It consists of a LOW to HIGH transition on D while CL is HIGH. he OP tells the lave that no more data will be written to or read from the lave. Device ddressing he Master initiates data transfer by creating a R condition on the bus. he Master then broadcasts an 8 bit serial lave address. he first 4 bits of the lave address (the preamble) select the emperature ensor ( preamble = 11) as shown in Figure 9. he next 3 bits, 2, 1 and, select one of 8 possible lave devices. he last bit, R/W, specifies whether a Read (1) or Write () operation is being performed. cknowledge matching lave address is acknowledged (CK) by the lave by pulling down the D line during the 9 th clock cycle (Figure 1). fter that, the lave will acknowledge all data bytes sent to the bus by the Master. When the lave is the transmitter, the Master will in turn acknowledge data bytes in the 9 th clock cycle. he lave will stop transmitting after the Master does not respond with acknowledge (NoCK) and then issues a OP. Bus timing is illustrated in Figure 11. 5
C695 D CL R BI Figure 8. tart/top iming OP BI EMPERURE ENOR 1 1 PREMBLE 2 1 R/W DEVICE DDRE Figure 9. lave ddress Bits CL FROM MER 1 8 9 D OUPU FROM RNMIER D OUPU FROM RECEIVER R Figure 1. cknowledge iming CKNOWLEDGE t F t LOW t HIGH t R CL 7% 7% 7% 3% 3% 7% D t U: t HD: t HD:D t U:D 7% 3% t U:O 7% 3% 3% 7% 7% t BUF Figure 11. Bus iming 6
C695 Write Operations emperature ensor Register Write o write data to a register the Master creates a R condition on the bus, and then sends out the appropriate lave address (with the R/W bit set to ), followed by an address byte and two data bytes. he matching lave will acknowledge the lave address, register address and the register data (Figure 12). he Master then ends the session by creating a OP condition on the bus. he OP completes the register update. Note that all registers in the are volatile meaning any data contained in them is lost when power is removed from the chip. Read Operations Immediate Read Upon power-up, the emperature ensor () address counter is initialized to h. he address counter will thus point to the Capability Register. his address counter may be updated by subsequent operations. C695 presented with a lave address containing a 1 in the R/W position will acknowledge the lave address and will then start transmitting data being pointed at by the current register address counter. he Master stops this transmission by responding with NoCK, followed by a OP (Figure 13). elective Read he Read operation can be started at an address different from the one stored in the address counter, by preceding the Immediate Read sequence with a data less Write operation. he Master sends out a R, lave address and address byte, but rather than following up with data (as in a Write operation), the Master then issues another R and continuous with an Immediate Read sequence (Figure 14). BU CIVIY: MER R LVE DDRE REGIER DDRE D (MB) D (LB) O P D LINE P LVE C K C K C K CK CK Figure 12. emperature ensor Register Write BU CIVIY: MER R LVE DDRE C K N O C O K P D LINE P LVE C K D (MB) D (LB) Figure 13. Immediate Read BU CIVIY: MER R LVE DDRE REGIER DDRE R LVE DDRE CK N O C O K P D LINE P LVE C K C K CK D (MB) D (LB) Figure 14. elective Read 7
C695 emperature ensor Operation he C695 temperature sensor () combines a Proportional to bsolute emperature (P) sensor with a modulator, yielding a 12 bit plus sign digital temperature representation. he runs on an internal clock, and starts a new conversion cycle at least every 1 ms. he result of the most recent conversion is stored in the emperature Data Register (DR), and remains there following a hut Down. Reading from the DR does not interfere with the conversion cycle. he value stored in the DR is compared against limits stored in the High Limit Register (HLR), the Low Limit Register (LLR) and/or Critical emperature Register (CR). If the measured value is outside the alarm limits or above the critical limit, then the EVEN pin may be asserted. he EVEN output function is programmable, via the Configuration Register for interrupt mode, comparator mode and polarity. he temperature limit registers can be Read or Written by the host, via the serial interface. t power on, all the (writable) internal registers default to x, and should therefore be initialized by the host to the desired values. he EVEN output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialized. While the is enabled (not shut down), event conditions are normally generated by a change in measured temperature as recorded in the DR, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. asynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and PCB, it is recommended that the exposed backside die attach pad (DP) be soldered to the PCB ground plane. Registers he C695 contains eight 16 bit wide registers allocated to functions, as shown in able 6. Upon power up, the internal address counter points to the capability register. Capability Register (User Read Only) his register lists the capabilities of the, as detailed in the corresponding bit map. Configuration Register (Read/Write) his register controls the various operating modes of the, as detailed in the corresponding bit map. emperature rip Point Registers (Read/Write) he C695 features 3 temperature limit registers, the HLR, LLR and CLR mentioned earlier. he temperature value recorded in the DR is compared to the various limit values, and the result is used to activate the EVEN pin. o avoid undesirable EVEN pin activity, this pin is automatically disabled at power up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two s complement with the LB representing.25 C, as detailed in the corresponding bit maps. emperature Data Register (User Read Only) his register stores the measured temperature, as well as trip status information. B15, B14 and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVEN status or by Configuration register settings. Measured temperature is represented by bits B12 to B. Data format is two s complement, where B12 represents the sign, B11 represents 128 C, etc. and B represents.625 C. Manufacturer ID Register (Read Only) he manufacturer ID assigned by the PCI IG trade organization to the C695 device is x1b9. Device ID and Revision Register (Read Only) his register contains manufacturer specific device ID and device revision information. 8
C695 able 6. EMPERURE ENOR REGIER Register ddress Register Name Power On Default Read/Write x Capability Register x7f Read x1 Configuration Register x Read/Write x2 High Limit Register x Read/Write x3 Low Limit Register x Read/Write x4 Critical Limit Register x Read/Write x5 emperature Data Register Undefined Read x6 Manufacturer ID Register x1b9 Read x7 Device ID/Revision Register x813 Read x8 Reserved able 7. CPBILIY REGIER B15 B14 B13 B12 B11 B1 B9 B8 RFU RFU RFU RFU RFU RFU RFU RFU B7 B6 B5 B4 B3 B2 B1 B EVD MOU RFU RE [1:] RNGE CC EVEN Bit Description B15:B8 Reserved for future use; can not be written; should be ignored; will typically read as B7 (Note 8) : Configuration register bit 4 is frozen upon setting Configuration register bit 8 (i.e. a shut down freezes the EVEN output) 1: Configuration register bit 4 is cleared upon setting Configuration register bit 8 (i.e. a shut down de asserts the EVEN output) B6 : he implements MBus time out within the range 1 to 6 ms 1: he implements MBus time out within the range 25 to 35 ms B5 : Pin V HV compliance required for RWP/PD compatibility not explicitly stated 1: Pin V HV compliance required for RWP/PD compatibility explicitly stated B4:B3 : LB =.5 C (9 bit resolution) 1: LB =.25 C (1 bit) 1: LB =.125 C (11 bit) 11: LB =.625 C (12 bit) B2 : Positive emperature Only 1: Positive and Negative emperature B1 : ±2 C over the active range and ±3 C over the operating range (Class C) 1: ±1 C over the active range and ±2 C over the monitor range (Class B) B : Critical emperature only 1: larm and Critical emperature 8. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a 1 to Configuration Register bit 5 (i.e. the EVEN output can be de-asserted during shut-down periods) 9
C695 able 8. CONFIGURION REGIER B15 B14 B13 B12 B11 B1 B9 B8 RFU RFU RFU RFU RFU HY [1:] HDN B7 B6 B5 B4 B3 B2 B1 B CRI_LOCK EVEN_LOCK CLER EVEN_ EVEN_CRL CRI_ONLY EVEN_POL EVEN_MODE Bit Description B15:B11 Reserved for future use; can not be written; should be ignored; will typically read as B1:B9 (Note 9) : Disable hysteresis 1: et hysteresis at 1.5 C 1: et hysteresis at 3 C 11: et hysteresis at 6 C B8 (Note 13) : hermal ensor is enabled; temperature readings are updated at sampling rate 1: hermal ensor is shut down; temperature reading is frozen to value recorded before HDN B7 (Note 12) : Critical trip register can be updated 1: Critical trip register cannot be modified; this bit can be cleared only at POR B6 (Note 12) : larm trip registers can be updated 1: larm trip registers cannot be modified; this bit can be cleared only at POR B5 (Note 11) : lways reads as (self clearing) 1: Writing a 1 to this position clears an event recording in interrupt mode only B4 (Note 1) : EVEN output pin is not being asserted 1: EVEN output pin is being asserted B3 (Note 9) : EVEN output disabled; polarity dependent: open drain for bit B1 = and grounded for B1 = 1 1: EVEN output enabled B2 (Note 15) : event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only B1 (Notes 9, 14) : EVEN output active low 1: EVEN output active high B (Note 9) : Comparator mode 1: Interrupt mode 9. Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set. 1.his bit is a polarity independent software copy of the EVEN pin, i.e. it is under the control of B3. 11. Writing a 1 to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 12). 12.Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition. 13.he powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the is shut down the DC is disabled and the temperature reading is frozen to the most recently recorded value. he can not be shut down (B8 can not be set) as long as either one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. 14.he EVEN output is open-drain and requires an external pull-up resistor for either polarity. he natural polarity is active low, as it allows wired-or operation on the EVEN bus. 15.Can not be set as long as lock bit B6 is set. 1
C695 able 9. HIGH LIMI REGIER B15 B14 B13 B12 B11 B1 B9 B8 ign 128 C 64 C 32 C 16 C B7 B6 B5 B4 B3 B2 B1 B 8 C 4 C 2 C 1 C.5 C.25 C able 1. LOW LIMI REGIER B15 B14 B13 B12 B11 B1 B9 B8 ign 128 C 64 C 32 C 16 C B7 B6 B5 B4 B3 B2 B1 B 8 C 4 C 2 C 1 C.5 C.25 C able 11. CRI LIMI REGIER B15 B14 B13 B12 B11 B1 B9 B8 ign 128 C 64 C 32 C 16 C B7 B6 B5 B4 B3 B2 B1 B 8 C 4 C 2 C 1 C.5 C.25 C able 12. EMPERURE D REGIER B15 B14 B13 B12 B11 B1 B9 B8 CRI HIGH LOW ign 128 C 64 C 32 C 16 C B7 B6 B5 B4 B3 B2 B1 B 8 C 4 C 2 C 1 C.5 C.25 C (Note 16) 16.When applicable (as defined by Capability bit RE), unsupported bits will read as.125 C (Note 16).625 C (Note 16) Bit B15 B14 B13 Description : emperature is below the CRI limit 1: emperature is equal to or above the CRI limit : emperature is equal to or below the High limit 1: emperature is above the High limit : emperature is equal to or above the Low limit 1: emperature is below the Low limit 11
C695 Register Data Format he values used in the temperature data register and the 3 temperature trip point registers are expressed in two s complement format. he measured temperature value is expressed with 12 bit resolution, while the 3 trip temperature limits are set with 1 bit resolution. he total temperature range is arbitrarily defined as 256 C, thus yielding an LB of.625 C for the measured temperature and.25 C for the 3 limit values. Bit B12 in all temperature registers represents the sign, with a indicating a positive, and a 1 a negative value. In two s complement format, negative values are obtained by complementing their positive counterpart and adding a 1, so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. Note that trailing bits, are irrespective of polarity. herefore the don t care bits (B1 and B) in the 1 bit resolution temperature limit registers, are always. able 13. 12 BI EMPERURE D FORM Binary (B12 to B) Hex emperature 1 11 11 1C9 55 C 1 11 111 1CE 5 C 1 111 111 1E7 25 C 1 1111 1111 1111 1FFF.625 C C 1 1 +.625 C 1 11 19 +25 C 11 1 32 +5 C 111 111 7D +125 C Event Pin Functionality he EVEN output reacts to temperature changes as illustrated in Figure 15, and according to the operating mode defined by the Configuration register. In Interrupt Mode, the enabled EVEN output will be asserted every time the temperature crosses one of the alarm window limits, and can be de asserted by writing a 1 to the clear event bit (B5) in the configuration register. When the temperature exceeds the critical limit, the event remains asserted as long as the temperature stays above the critical limit and can not be cleared. In Comparator Mode, the EVEN output is asserted outside the alarm window limits, while in Critical emperature Mode, EVEN is asserted only above the critical limit. he exact trip limits are determined by the 3 temperature limit settings and the hysteresis offsets, as illustrated in Figure 16. Following a shut down request, the converter is stopped and the most recently recorded temperature value present in the DR is frozen; the EVEN output will continue to reflect the state immediately preceding the shut down command. herefore, if the state of the EVEN output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the. his may require clearing the event, disabling the EVEN output or perhaps changing the EVEN output polarity. In normal use, events are triggered by a change in recorded temperature, but the C695 will also respond to limit register changes. Whereas recorded temperature values are updated at sampling rate frequency, limits can be modified at any time. he enabled EVEN output will react to limit changes as soon as the respective registers are updated. his feature may be useful during testing. 12
C695 EMPERURE CRIICL UPPER LRM WINDOW LOWER HYEREI FFEC HEE RIP POIN OFWRE CLER EVEN IME EVEN IN INERRUP EVEN IN COMPROR MODE EVEN IN CRIICL EMP ONLY MODE *EVEN cannot be cleared once the DU temperature is greater than the critical temperature Figure 15. Event Detail H H HY L L HY BELOW WINDOW BI BOVE WINDOW BI Figure 16. Hysteresis Detail 13
C695 PCKGE DIMENION DFN8, 2x3 CE 511K 1 IUE D e b E E2 PIN#1 IDENIFICION PIN#1 INDEX RE 1 D2 L OP VIEW IDE VIEW BOOM VIEW YMBOL MIN NOM MX.7.75.8 1..2.5 2.45.55.65 2 3.2 REF b.2.25.3 3 D 1.9 2. 2.1 D2 1.3 1.4 1.5 FRON VIEW E 2.9 3. 3.1 E2 1.2 1.3 1.4 e.5 YP L.2.3.4 Notes: (1) ll dimensions are in millimeters. (2) Complies with JEDEC MO-229. 14
C695 Example of Ordering Information Prefix Device # uffix C 695 VP2 G 4 Company ID Product Number 695 Package VP2: DFN Lead Finish G: NiPdu ape & Reel (Note 21) : ape & Reel 4: 4,/Reel 17.ll packages are RoH compliant (Lead free, Halogen free) 18.he standard lead finish is NiPdu. 19.his device used in the above example is a C695, in DFN, NiPdu Lead Frame, ape & Reel, 4,/Reel. 2.For additional package and temperature options, please contact your nearest ON emiconductor ales office. 21.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD811/D. ON emiconductor is licensed by Philips Corporation to carry the I 2 C Bus Protocol. ON emiconductor and are registered trademarks of emiconductor Components Industries, LLC (CILLC). CILLC reserves the right to make changes without further notice to any products herein. CILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does CILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in CILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. CILLC does not convey any license under its patent rights nor the rights of others. CILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the CILLC product could create a situation where personal injury or death may occur. hould Buyer purchase or use CILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold CILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that CILLC was negligent regarding the design or manufacture of the part. CILLC is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution Center for ON emiconductor P.O. Box 5163, Denver, Colorado 8217 U Phone: 33 675 2175 or 8 344 386 oll Free U/Canada Fax: 33 675 2176 or 8 344 3867 oll Free U/Canada Email: orderlit@onsemi.com N. merican echnical upport: 8 282 9855 oll Free U/Canada Europe, Middle East and frica echnical upport: Phone: 421 33 79 291 Japan Customer Focus Center Phone: 81 3 5773 385 15 ON emiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local ales Representative C695/D