The Spreadtrum SR528 is a single-chip radio transceiver for quad-band GSM/GPRS cellular applications. The SR528 has been implemented in bulk CMOS and the design has been optimized to meet the challenges of integrated handset design. The receiver part of SR528 supports both Zero-IF (ZIF), and Near Zero-IF (NZIF) system implementations. The performance of the transmit chain requires no additional RF filters to meet the specification for out-of-band emissions. The SR528 exceeds all ETSI radio design requirements and its enhanced transmit architecture permits the rapid design of stable, high performance handsets only requiring a single radio shield. T/R Switch Matrix SR528 Functional Block Diagram E-GSM USGSM DCS PCS Quad- Band PAM LNA LNA LNA LNA Reference Oscillator Block LO Divider /2 or /4 DCXO REF OUT REF2 OUT Delta-sigma Frac N Synthesizer RX Filter Strip Digital Control RX Mode Select ADC + Delta Sigma Mod Zero IF Mode De-rotation 100KHz Near-Zero IF Mode SR528 Programming Interface and Registers Analog Multiplexer Features Industry leading receive current 55mA Available in 5mm x 4mm x 0.9mm 28L 0.5mm pitch QFN Package Enhanced transmit architecture supports: Single radio shield Very low phase error Faster design cycles Integrated transceiver radio fully supporting GSM/GPRS receive and transmit for voice and data applications True Quad-band operation (USGSM850, EGSM900, DCS1800 and PCS1900) ZIF and NZIF receive architectures supported Direct down-conversion receiver eliminates image reject and IF filters Receiver gain digitally selectable in 1dB steps LO Modulation for GMSK No extra off-chip RF filters required for transmit Extensive on-chip automatic selfcalibration Single integrated and programmable fastsettling multi-band LO synthesizer engine Temperature sensor built-in GPRS class 12 compliant 3-wire serial control interface 2.7V to 3.3V single supply voltage Lead-free/RoHS compliant Applications Highly integrated 2.5G quad-band cellular handsets Entry level and feature level mobile phones Wireless PDA and cardbus adapters Spreadtrum Communications Page 1 of 29 Datasheet
SR528 Product Feature Summary Transceiver Functions Integrated radio transceiver fully supporting GSM, GPRS and receive EGPRS GPRS class 12 supported True quad-band GSM operation (USGSM850, EGSM900, DCS1800, PCS1900) Direct LO modulator in GMSK mode General Features Mixed signal interface to a cellular base band Digital tuning of reference crystal 2.7V to 3.3V single supply range -40 C to +85 C operation Table 1: Absolute Maximum Ratings Parameter Min Max Unit Supply voltage (VDD pins) 3.6 V Ambient operating temperature -40 85 C Storage temperature -50 125 C Total power dissipation 475 mw Input voltage range, any pin GND VDD V ESD, MM 100 V ESD, CDM 500 V ESD, HBM (Digital interface pins) 2 kv ESD, HBM (All other pins) 1 kv Note: Stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to maximum rating conditions for extended periods may reduce device reliability. Spreadtrum believes the furnished information is correct and accurate at the time of this printing. However, Spreadtrum Communications reserves the right to make changes to its products without notice. Spreadtrum Communications does not assume responsibility for the use of the described product(s). Spreadtrum Communications Page 2 of 29 Datasheet
Table 2: Operating Conditions Parameter Min Typ Max Unit Condition Operating Range Supply voltage (all VDD pins) 2.7 2.8 3.3 V Operating ambient temperature -40 25 85 C Storage temperature -50 125 C Table 3: Supply Current All VDD pins = 2.8V, T ambient = 25 C, unless otherwise noted Parameter Min Typ Max Unit Condition Total Supply Current Total receive Reg 0x00[11:0]=0x7CF USGSM850, EGSM900 55 66 ma DCS1800, PCS1900 55 66 ma Total transmit Reg 0x00[11:0]=0x0FF LB GMSK mode 114 136 ma HB GMSK mode 114 136 ma Low power modes VDD DIG/IO=2.8V, REF2 EN=0 Idle mode 3.5 5.5 ma DCXO is on Doze mode 14 30 μa DCXO is off Isolated Supply Currents Receive mode Reg 0x00[11:0]=0x7CF VDD1 28 34 ma RF IC circuitry positive supply VDD2 22 26 ma Synthesizer and BB circuitry positive supply VDD DIG IO 5 6 ma DCXO, Digital, and RCB positive supply Transmit mode Reg 0x00[11:0]=0x0FF VDD1 81 96 ma RF IC circuitry positive supply VDD2 24 29 ma Synthesizer and BB circuitry positive supply VDD DIG IO 9 11 ma DCXO, Digital, and RCB positive supply Interface only VDD DIG IO 3.5 5.5 ma DCXO, Digital, and RCB positive supply Spreadtrum Communications Page 3 of 29 Datasheet
Table 4: DC Parameters All VDD pins = 2.8V, T ambient = 25 C, unless otherwise noted These parameters are not tested in mass production Parameter Min Typ Max Unit Condition Baseband Analog Ports RX Output Pins 15-18 Output common mode DC level 8/25 x VDD 12/25 x VDD 16/25 x VDD V DC resolution 1/25 x VDD 1/25 x VDD mv / LSB Source resistance 500 1000 Ω (se) Differential load impedance Resistive 3 20 kω (dif) Reactive 1 15 pf (dif) 'Off' resistance Differential 20 24 kω (dif) Common mode 100 120 kω Baseband Analog Ports TX Input Pins 15-18 Input common mode 1 Input voltage range GND + 350mV VDD 2 VDD - 350mV Input impedance Resistive 10 12 kω (dif) Reactive 1 2 pf (dif) 'Off' resistance Differential 20 24 kω (dif) Common mode 100 120 kω Digital DC Parameters RCB Port Pins 21-23 and Ref Enables Pins 1 and 20 Logic levels Input logic low 0 0.1 0.5 V Input logic high 1.45 1.8 VDD + 0.2 V Input current 0.001 0.5 μa "TEMP OUT" Output Pin 4 Absolute accuracy Voltage output (VTEMP) T DIE = -40 C 57 83 109 mv T DIE = +25 C 947 973 999 mv T DIE = +85 C 1772 1798 1824 mv Source resistance 900 1200 Ω Current consumption 0.8 1 ma Drawn from "VDD2" Temperature equation Temp=0.0695*m- 45.326 m=temp sensor reading in mv Spreadtrum Communications Page 4 of 29 Datasheet
Table 5: AC Parameters: RF Input Ports All VDD pins = 2.8V, T ambient = -40 C to +85 C, unless otherwise noted Measured in a 50Ω impedance system, including external balun (~1dB IL) and required matching components unless otherwise noted Parameter Min Typ Max Unit Condition RF Input Ports USGSM850 869 894 MHz EGSM900 925 960 MHz DCS1800 1805 1880 MHz PCS1900 1930 1990 MHz Characteristic input impedance USGSM850 200 1 250 1.5 Ω pf EGSM900 200 1 250 1.5 Ω pf DCS1800 200 1 250 1.5 Ω pf PCS1900 200 1 250 1.5 Ω pf Spreadtrum Communications Page 5 of 29 Datasheet
Table 6: GSM Receiver RF Specifications Parameter Min Typ Max Unit Condition Cascaded noise figure @ 25 C Reg 0x00[11:0]=0x7CF USGSM850 2.5 3 db EGSM900 2.5 3 db Excludes SAW/PCB losses (~1.5dB) DCS1800 2.5 3 db PCS1900 2.5 3 db ZIF and NZIF mode Maximum cascaded voltage gain Reg 0x00[11:0]=0x7CF USGSM850 92 95 98 db EGSM900 92 95 98 db DCS1800 92 95 98 db PCS1900 92 95 98 db Minimum cascaded voltage gain Reg 0x00[11:0]=0x141 USGSM850 11 14 17 db EGSM900 11 14 17 db DCS1800 7 10 13 db PCS1900 7 10 13 db Baseband step Minimum step size ±0.75 ±1 ±1.25 db Cascaded gain control linearity Integrated -0.5 0 0.5 db Differential Over any 20dB step -0.5 0 0.5 db Differential Over any 2dB step -0.5 0 0.5 db Spreadtrum Communications Page 6 of 29 Datasheet
Table 7: RF Front End Parameter Min Typ Max Unit Condition RF front end voltage gain (high gain) Reg 0x00[10]=1 USGSM850 3.5 4 4.5 db EGSM900 4 db DCS1800 3.5 4 4.5 db PCS1900 4 db RF front end voltage gain (low gain) Reg 0x00[10]=0 USGSM850-23.5-23 -22.5 db EGSM900-23 db DCS1800-26.5-26 -25.5 db PCS1900-26 db Input P1dB high gain Reg 0x00[11:0]=0x770 USGSM850-18 dbm EGSM900-18 dbm DCS1800-18 dbm PCS1900-18 dbm Input P1dB low gain Reg 0x00[11:0]=0x141 USGSM850-8 dbm EGSM900-8 dbm DCS1800-8 dbm PCS1900-8 dbm Input IP3 Reg 0x00[11:0]=0x770 USGSM850-12 dbm EGSM900-12 dbm DCS1800-12 dbm PCS1900-12 dbm Input IP2 Reg 0x00[11:0]=0x770 USGSM850 40 44 dbm ZIF and NZIF EGSM900 40 44 dbm DCS1800 40 44 dbm PCS1900 40 44 dbm Image rejection Reg 0x00[11:0]=0x7CF USGSM850 40 48 db ZIF and NZIF EGSM900 40 48 db DCS1800 40 48 db PCS1900 40 48 db Quadrature gain mismatch -0.5 0 0.5 db Spreadtrum Communications Page 7 of 29 Datasheet
Table 8: TX Specification Parameter Min Typ Max Unit Condition TX Baseband Input Ports Input signal level voltage swing 0.5 1 2 Vpp (dif) Differential input offset voltage 16 32 63 mv Table 9: GSM Transmitter RF Modulation Specification Parameter Min Typ Max Unit Condition TX RF Output Ports RF output frequency Reg 0x00[11:0]=0x0FF USGSM850 824 849 MHz EGSM900 880 915 MHz DCS1800 1710 1785 MHz PCS1900 1850 1910 MHz GMSK programmable output power Reg 0x00[11:0]=0x0FF USGSM/EGSM port -2 0 6 dbm DCS/PCS port -2 0 6 dbm GMSK saturated output power Reg 0x00[11:0]=0x0FF USGSM/EGSM port 6 7 dbm DCS/PCS port 6 7 dbm Output power variation Reg 0x00[11:0]=0x0FF USGSM/EGSM port -2 0 2 db DCS/PCS port -2 0 2 db Spreadtrum Communications Page 8 of 29 Datasheet
Table 10: GSM Transmitter RF Modulation Specification (Part 2) Parameter Min Typ Max Unit Condition TX Modulated RMS phase error Reg 0x00[11:0]=0x0FF USGSM850 1 1.5 EGSM900 1 1.5 DCS1800 1.5 2 PCS1900 1.5 2 Peak phase error Reg 0x00[11:0]=0x0FF USGSM850 4 6 EGSM900 4 6 DCS1800 5 8 PCS1900 5 8 RF modulation spectrum Reg 0x00[11:0]=0x0FF USGSM850 band fc ± 400kHz -67-63 dbc EGSM900 band fc ± 400kHz -67-63 dbc DCS1900 band fc ± 400kHz -65-63 dbc PCS1900 band fc ± 400kHz -65-63 dbc Output harmonics level Reg 0x00[11:0]=0x0FF USGSM/EGSM 2 x fc -26-20 dbc USGSM/EGSM 3 x fc -16-10 dbc DCS/PCS 2 x fc -26-20 dbc DCS/PCS 3 x fc -26-20 dbc Output load Impedance 50 Ω Spreadtrum Communications Page 9 of 29 Datasheet
Table 11: LO Synthesizer Specification Parameter Min Typ Max Unit Condition LO Synthesizer Lock time Receive mode 100 150 μs Settling to within 0.1ppm of target frequency referenced Transmit mode 100 150 μs Synthesizer frequency 3292 3600 3984 MHz range VCO frequency Spurious levels -74-71 dbc Foffset > 400kHz Spreadtrum Communications Page 10 of 29 Datasheet
Table 12: DCXO Specification Parameter Min Typ Max Unit Condition DCXO Reference Configuration (Crystal Reference, "REF IN-" & "REF IN+" Ports) Pins 25 & 26 Capacitive step size (coarse) Reg 0x3A[3:0] = 0000 3 pf Reg 0x3A[3:0] = 0001 2.8 pf : : pf Reg 0x3A[3:0] = 1111 0 pf Capacitive tuning range (fine tuning) Reg0x39[13:0] = 0x3FFF 3.9 4 4.4 pf Reg0x39[13:0] = 0x0000 7.35 7.65 8.05 pf Capacitive step size (fine) 0.21 0.22 0.24 ff/lsb Oscillation startup Input resistance -1000-450 -150 Ω Transconductance 9.5 ms Nominal voltage swing "REF IN+" terminal 1.35 1.8 Vpp "REF IN-" terminal 1.36 1.6 Vpp Reference Crystal Requirements Frequency tolerance -10 0 10 ppm Temperature stability -10 0 10 ppm 20 C < T ambient < +85 C Aging -1 0 1 ppm/year Drive level 100 200 μw Pulling sensitivity 14 25 ppm/pf Load capacitance (CL) 6.5 8 9 pf No external capacitor required. Use coarse setting to adjust for crystal CL value Motional series resistance (RS) 20 60 Ω TCXO Reference Configuration (External Reference, "REF IN+" Port) Pin 26 Input coupling requirement AC Input impedance Resistive 12 15 kω Reactive 8 10 pf Input voltage swing 650 1000 mvpp Input duty cycle 40 50 60 % Phase noise 1kHz offset -132-129 dbc/hz Table 13: Reference Output Specification Parameter Min Typ Max Unit Condition Reference Clock Output Pins 27 & 28 Reference frequency 26 MHz Frequency compensation range ±27 ±40 ppm Frequency compensation resolution 0.005 0.02 ppm/lsb Output duty cycle 40 50 60 % Amplitude (Ref Out) Reg0x38[13:12] = 11 1200 mvpp Reg0x38[13:12] = 10 950 mvpp Reg0x38[13:12] = 01 750 mvpp Reg0x38[13:12] = 00 600 mvpp Clock jitter 10 20 ps rms Drive capacity 10 pf Power-up settling time 2 3 ms Note: For Ref2 Out control, the register location is x38[9:8] Spreadtrum Communications Page 11 of 29 Datasheet
Functional Description: LNA SR528 E-GSM RX Filter Strip RX Mode Select USGSM LNA Zero IF Mode De-rotation T/R Switch Matrix DCS PCS LNA LNA LO Divider /2 or /4 Delta-sigma Frac N Synthesizer 100KHz Near-Zero IF Mode Analog Multiplexer Quad- Band PAM ADC + Delta Sigma Mod Reference Oscillator Block DCXO Digital Control Programming Interface and Registers REF OUT REF2 OUT The SR528 represents the most integrated solution for multi-band GSM/GPRS applications. It integrates a complete quad-band wireless receiver, transmitter, and a fractional-n frequency synthesizer including the voltage controlled oscillator (VCO) and loop filter. The RF portion of the receiver consists of a four band integrated Low Noise Amplifier (LNA) and a quadrature down-converter that performs either direct (ZIF) or near-direct down-conversion (NZIF). The receive chain is fully differential resulting in improved noise immunity during operation. The receive channel filter is implemented in an RX filter strip. It comprises a blocker-reject low-pass channel filter (LPF) and two digitally controlled variable gain amplifiers (VGA). The transmit path consists of a Delta Sigma PLL modulator for GSM. During normal reception and transmission the frequency synthesizer runs at four times the channel frequency for USGSM and EGSM and at two times the channel frequency for PCS1900 and DCS1800. The SR528 also includes a digitally controlled crystal oscillator (DCXO) that can be used to generate the system reference clock at 26MHz. This reduces overall system complexity, cost and form factor. The SR528 is programmed and controlled using a 3-wire radio configuration bus (RCB). The RCB utilizes a packet data pin (DATA), a reference clock pin (CLK) and a latch enable (LE) pin for communication and a 24-bit word pattern is used to format the data packets. Spreadtrum Communications Page 12 of 29 Datasheet
Receive Chain Figure 1: SR528 Receive Chain Quadrature Down-converter RX Filter Strip LNA Zero IF Mode De-rotation I_Port NZIF Q_Port Frequency Synthesizer and LO Generation LO: 4X EGSM/USGSM LO: 2X PCS/DCS PMA LPF STAGE PGA STAGE CHANNEL FILTER STAGE OUTPUT PGA STAGE NOTCH RESPONSE/ DEROTATOR ANALOG MUX (not shown) The receiver in the SR528 can be set to Zero-IF or to a Near Zero-IF mode (NZIF). The receiver mode is programmed over the RCB. The RF portion of the receiver for each frequency of operation includes an LNA with adjustable gain settings to maximize the dynamic range of the receiver. The down-converter portion of the receiver is split into two sections, a high band down-converter for PCS and DCS, and a low-band down-converter for EGSM and USGSM. The receive ports are balanced and matched for 200Ω to support standard RF SAW filters. The RX filter strip in the receiver paths comprises a PMA low pass filter (3rd order Chebyshev) PGA stage, Channel Filter (3rd order Legendre). This is the same for ZIF mode and NZIF mode. This ensures operation over a broad range of gain settings. The channel filter ensures rejection of strong in-band and out-of-band blockers. In order to minimize the set-up of the SR528, extensive on-chip automatic calibration has been implemented. Random DC offsets generated in the SR528 are calibrated out. Automatic DC calibration ensures that externally generated DC offsets do not overload the receive chain. An on-chip state machine generates the timing control signals for this DC calibration and the calibration routine is initiated via the RCB. In normal operation the state machine is started, the RX filter strip is powered up and any inherent DC offsets are removed. These correction signals are then held constant as the RF front end is powered up for the receive chain to process the incoming signal. None of these calibrations require any interaction with the baseband sub-system. Spreadtrum Communications Page 13 of 29 Datasheet
Transmit Chain Figure 2: SR528 Transmit Chain TX I + TX I - TX Q + TX Q Digital Delta- Sigma Modulator 3 Frac - N PLL LO Divider (2/4) Balun Balun RF Attenuator RF Attenuator EGSM/USGSM RF DCS/PCS RF The transmit chain of the SR528 consists of a direct LO modulation transmit path for GSM (GMSK). The LO is modulated directly by the baseband signal by a digital delta-sigma modulator. The modulated output of the modulator is mixed with a DC voltage and the resultant output is then converted to a single ended waveform via an on chip balun. The RF output power level is adjusted to an appropriate level via the on chip RF attenuator. The RF ports of the transmitter are single-ended and matched to 50Ω. No off-chip RF baluns or filters are required. Spreadtrum Communications Page 14 of 29 Datasheet
Frequency Sources There are two frequency sources on the SR528. The first is the RF frequency synthesizer, which serves as the LO for both receive and transmit chains. The VCO for the synthesizer is fully integrated and no calibration is required as this is all performed automatically on the SR528. During reception or transmission in normal operation, the frequency synthesizer is operated at twice the desired channel of operation in PCS and DCS modes and at four times the desired channel of operation in EGSM and USGSM modes. On-chip dividers ( 2 for PCS/DCS and 4 EGSM/USGSM) reduce the frequency of the signal. The outputs of these dividers are buffered before being applied to the up or down converters. The loop filter of the frequency synthesizer is fully integrated. This reduced component count and form factor minimizes the number of sensitive components in the design. Table 14: SR528 LO Frequencies of Operation FREQUENCY BAND Transmitter Frequency Receiver Frequency Transmitter Synthesizer Frequency Receiver Synthesizer Frequency USGSM 824-849 869-894 3296-3396 3476-3576 EGSM 880-915 925-960 3520-3660 3700-3840 DCS1800 1710-1785 1805-1880 3420-3570 3610-3760 PCS1900 1850-1910 1930-1990 3700-3820 3860-3980 The second frequency source is the Digitally Controlled Crystal Oscillator (DCXO). The DCXO is designed to accept a crystal with fundamental frequency of 26MHz. After power-on of the chip, the DCXO starts oscillating. It continues oscillating until power-off or programming of doze mode. The reference oscillator can be used with a 26MHz crystal. In this configuration, the reference frequency is controlled by on-chip capacitor banks that can be switched in via the RCB. This allows for precise tuning of the crystal when implemented with a conventional Automatic Frequency Control (AFC) loop. The SR528 can also be supplied with an external reference such as a 26MHz VCTCXO or other frequency source. The reference clock signal generated in the chip is buffered before being sent to the Phase Locked Loop in the frequency synthesizer block. Either a square wave or a clipped sine wave can be selected. The buffer is capable of driving a reference clock line with a load capacitance of 10pF. There are two 26MHz reference clock output ports on the SR528, REF OUT and REF2 OUT. Each output is independently controlled by its enable ports, REF EN and REF2 EN. Figure 3: Reference Oscillator Configuration.. REF IN+ REF IN- REF EN REF OUT REF2 OUT REF2 EN Spreadtrum Communications Page 15 of 29 Datasheet
Radio Configuration Bus (RCB) A radio configuration bus is used to control the various modes of operation within the SR528. This bus is implemented as a 3-wire serial interface. The signals are Data, Clock and Latch Enable (DATA, CLK, and LE). Power must be applied to the SR528 to program the registers but none of the radio circuitry needs to be active. This minimizes current consumption and also allows pre-programming during normal operation to minimize clock interference. Figure 4: RCB Format Word Structure First Address Bit (MSB) Final Data Bit (LSB) A7 23 A6 22 A5 21 A4 20 A3 19 A2 18 A1 17 A0 16 D15 15 D14 14 D13 13 D12 12 D11 11 D10 10 D9 9 D8 8 D7 7 D6 6 D5 5 D4 4 D3 3 D2 2 D1 1 D0 0 Write Operation DATA A7 A6 A5 A4 A3 A0 D15 D14 D0 CLK 23 22 21 20 19 16 15 14 0 LE Notes: Data are shifted into the registers on the rising edge of the clock. Data are shifted in MSB first. Data are taking effect on the last rising edge of CLK when D0 is shifted in. CLK and DATA are not taken into account when LE is high. They can be high or low or toggling without any effect on the chip. Figure 5: SR528 Radio Configuration Bus Timing (T amb = 25 o C, All VDD = 2.8V, unless otherwise noted) Spreadtrum Communications Page 16 of 29 Datasheet
Parameter Description Min Typ Max Unit F CLK CLK Frequency 5 26 80 MHz t CPH CLK pulse high 5 ns t CPL CLK pulse low 5 ns t CLH CLK low period before rising edge 5 ns t LC LE to CLK setup 5 ns t LCS LE rising edge past CLK rising edge 10 ns t LPH Latch pulse high 5 ns Figure 6: RCB Clock Rising & Falling Edges (T amb = 25 C, All VDD = 2.8V, unless otherwise noted) Parameter Description Min Typ Max Unit t RISE CLK rise time 100 ns t FALL CLK fall time 100 ns Spreadtrum Communications Page 17 of 29 Datasheet
Package Options: There are four types of the packages, all are compatible with another. Only difference among the pin 1 marking. Please note each package type and its pin 1 marking. Figure 7: SR528 28-pin QFN package (Option 1) Spreadtrum Communications Page 18 of 29 Datasheet
Figure 8 SR528 28-pin QFN package (Option 2) Spreadtrum Communications Page 19 of 29 Datasheet
Figure 9 SR528 28-pin QFN package (Option 3) Spreadtrum Communications Page 20 of 29 Datasheet
Figure 10 SR528 28-pin QFN package (Option 4) Spreadtrum Communications Page 21 of 29 Datasheet
Table 15: Landing & Solder Mask Dimensions Description L(mm) W(mm) Remark PERIPHERAL PAD LANDING 0.625 0.28 ROUNDED LANDING PADS PERIPHERAL PAD SOLDER MASK 0.725 0.38 0.100mm OVERPAD LANDING (SMD) PERIPHERAL PAD PASTE MASK 0.625 0.28 ROUNDED LANDING PADS EXPOSED GROUND PADDLE PAD LANDING 3.80 2.80 3.80x2.80 RECTANGLE EXPOSED GROUND PADDLE SOLDER MASK 3.90 2.90 0.100mm OVERPAD LANDING (SMD) EXPOSED GROUND PADDLE PASTE MASK 3.80 2.80 3.80x2.80 RECTANGLE EXPOSED GROUND PADDLE VIA PATTERN - - 0.30mm DIAMETER, 3x3 ARRAY 0.80mm PITCH Figure 11: Metal Landing Pattern Spreadtrum Communications Page 22 of 29 Datasheet
Figure 12: Solder Mask Land Pattern Spreadtrum Communications Page 23 of 29 Datasheet
Figure 13: SR528 Pin Diagram (TOP VIEW) 28-Pin QFN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 REF EN 20 NC 19 VDD1 18 I+ TEMP OUT US/EGSM TX DCS/PCS TX SR528 17 16 15 I- Q+ Q- PCS RX+ PCS RX- DCS RX+ DCS RX- EGSM RX+ EGSM RX- USGSM RX+ USGSM RX- REF OUT REF2 OUT REF IN+ REF IN - VDD DIG DATA CLK LE REF2 EN VDD2 5mm x 4mm (Topside View, Note the PADDLE is chip ground connection) This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Spreadtrum Communications Page 24 of 29 Datasheet
Figure 14: SR528 Pin Diagram (BOTTOM VIEW) 28-Pin QFN 20 19 18 17 16 15 14 13 12 11 10 9 8 7 21 22 23 24 25 26 27 28 REF2 EN VDD2 I+ I- Q+ Bottom View Paddle 1 2 3 4 5 REF EN NC VDD1 TEMP OUT US/EGSM TX Q- 6 DCS/PCS TX USGSM RX- USGSM RX+ EGSM RX- EGSM RX+ DCS RX- DCS RX+ PCS RX- PCS RX+ LE CLK DATA VDD DIG REF IN - REF IN+ REF2 OUT REF OUT 5mm x 4mm (Bottom View, Note the PADDLE is chip ground connection) This device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the gates. Spreadtrum Communications Page 25 of 29 Datasheet
PIN Signal Name Type Description Table 16: SR528 Signal Descriptions 1 REF EN I Enable REF OUT reference clock output (active high) 2 NC I Not Connected 3 VDD1 S Analog supply, bypass with 0.1µF capacitors 4 TEMP OUT O Internal analog temperature sensor output 5 US/EGSM TX O USGSM850/EGSM900 transmit RF terminal [50Ω impedance] 6 DCS/PCS TX O DCS1800/PCS1900 transmit RF terminal [50Ω impedance] 7 PCS RX+ I PCS1900 RX front end LNA positive terminal [200Ω differential impedance] 8 PCS RX- I PCS1900 RX front end LNA negative terminal [200Ω differential impedance] 9 DCS RX+ I DCS1800 RX front end LNA positive terminal [200Ω differential impedance] 10 DCS RX- I DCS1800 RX front end LNA negative terminal [200Ω differential impedance] 11 EGSM RX+ I EGSM900 RX front end LNA positive terminal [200Ω differential impedance] 12 EGSM RX- I EGSM900 RX front end LNA negative terminal [200Ω differential impedance] 13 USGSM RX+ I USGSM850 RX front end LNA positive terminal [200Ω differential impedance] 14 USGSM RX- I USGSM850 RX front end LNA negative terminal [200Ω differential impedance] 15 Q- I/O Bi-directional baseband analog port Q-channel negative terminal 16 Q+ I/O Bi-directional baseband analog port Q-channel positive ter`minal 17 I- I/O Bi-directional baseband analog port I-channel negative terminal 18 I+ I/O Bi-directional baseband analog port I-channel positive terminal 19 VDD2 S Analog Supply, bypass with 10pF and 0.1µF capacitors after a series 18nH IND 20 REF2 EN I Enable REF2 OUT reference clock output (active high) 21 LE I Radio Configuration Bus latch enable input (low during DATA latching) 22 CLK I Radio Configuration Bus clock input 23 DATA I/O Radio Configuration Bus data input 24 VDD DIG S Supply for digital 25 REF IN- I Digitally controlled crystal oscillator negative input. This pin needs to be bypassed to ground via a 10pF capacitor when using an external reference. 26 REF IN+ I Digitally controlled crystal oscillator positive input/external reference signal input. External reference inputs to this terminal must be DC blocked. 27 REF2 OUT O Buffered 26MHz clock output 28 REF OUT O Buffered 26MHz clock output Paddle GND G Package ground connection Spreadtrum Communications Page 26 of 29 Datasheet
Figure 15: Power-Up Timing Parameter Description Min Typ Max Unit t CKset VDD stable to clock stable* 3 ms * Definition of clock stable : 95% of max. amplitude and DC offset reached at 0.1ppm frequency accuracy Table 17: Typical Frequencies of Operation GSM Transceiver Band of Operation Receive Input Frequency (MHz) Transmit Input Frequency (MHz) D (MHz) NxLo US GSM850 European EGSM900 European DCS1800 US PCS1900 Low 869 925 1805 1930 Mid High Low 881.6 894 824 942.6 960 880 1842.6 1880 1710 1960 1990 1850 Mid 836.6 897.6 1747.6 1880 High 849 45 915 45 1785 95 1910 80 4 4 2 2 Description of item 16, GSM Transceiver SR528: Part Number Part Description Package Type Operating Temperature SR528 SR528, Single chip Quad-band GSM/GPRS Radio Transceiver 28L QFN -40 to +85 C Spreadtrum Communications Page 27 of 29 Datasheet
Document History: Rev Date Changes 1.0 May 3, 2010 Initial Draft 1.1 May 4, 2010 Internal review 1.2 May 5, 2010 Top view diagram correction 1.3 May 18,2010 Updated supply bypass information and reference out amplitude register value 1.4 Jul 20,2010 Updated Ref Enable logic level (same as other digital logic levels) 1.5 Oct 10,2010 Updated Feature List and TX description 1.6 Oct 13, 2010 Added additional package diagrams 1.7 Oct 19, 2010 Added additional comment for package diagrams Spreadtrum Communications Page 28 of 29 Datasheet
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