High-Voltage (600 V) GaN Power Devices: Status and Benefits Power Electronics Conference 2017 Munich Airport Hilton, December 05, 2017 Th. Detzel, O. Häberlen, A. Bricconi, A. Charles, G. Deboy, T. McDonald Infineon Technologies Austria AG
This talk is about G SK D S GaN Devices & Performance Benchmark Industrial Implementation: Manufacturing & Quality Value Proposition & Application Examples 2
GaN HEMTs available configurations Infineon chose Emode (normoff) CASCODE GaN Suitable for standard gate drivers Low Vf body diode Not ideally suited for multi-chip solutions Not scalable to low voltage Complex balance between the two chips Cascode GaN HEMT G Good but limited in flexibility and performance D S Depletion-Mode GaN HEMT Low Voltage Si MOSFET ENHANCEMENT MODE GaN Excellent for hard and soft switching topologies TurnON and TurnOFF optimized Needed for LV applications Key for integration at chip and/or package level G SK D S P Gate Enhancement mode GaN HEMT The technology for innovative solutions and high volumes Infineon is focusing on Emode GaN for all consumer and industrial applications, with the most robust and performing concept in the market 3
Through recessed and regrowth gate technology from Panasonic: Best performance Device concept Key features Fully recessed 1 st barrier Regrowth of 2 nd barrier and p-gan layer Excellent V th stability p-gan structure at drain for dynamic R DSON optimization Hole injection at drain side Proceedings of ISPSD 2015 (Hongkong) and ISPSD 2016 (Prague) 4
Comparison of key Figures-of-Merit for Si, GaN and SiC devices 2017: emode GaN sets the performance benchmark among currently available 600 V devices Device Rating [V] R DS [mω] R DS *Q OSS [mωµc] R DS *Q RR [mωµc] R DS *E OSS [mωµj] R DS *Q G [mωnc] VF@15A [V] Si SJ [1] 600 57 22.6 32.5 440 3800 1.0 GaN emode [2] 600 55 2.2 0 350 320 2.7 GaN Cascode [3] 600 52 3.8 7.0 730 1460 1.4 SiC DMOS [4] 900 65 4.5 8.5 570 1950 2.7 SiC TMOS [5] 650 60 3.8 3.3 540 3480 3.3 [1] Infineon CoolMOS IPP60R070CFD7 Datasheet [2] Infineon CoolGaN Preliminary Values (Qrr excl. of Qoss) [3] TransPhorm TPH3205WS Datasheet [4] Wolfspeed C3M0065090J Datasheet [5] Rohm SCT3060AL Datasheet All numbers are typical values extracted from data sheet at 25 C 5
GaN HEMTs offer a very linear output capacitance curve; 190 mohm, 600 V devices longer delay times 10000 8 mohm*cm² SJ tech. Output capacitance Coss [pf] 1000 100 S G D 24 mohm*cm² SJ tech. 38.5 mohm*cm² SJ tech. GaN HEMT lower Eoss 10 2DEG 1 10 100 1.000 Drain-Source voltage VDS [V] 6
Industrial Implementation: Manufacturing
Infineon Technologies Austria AG Villach Lead site for development and manufacturing of power semiconductors at Infineon 22,000 m² clean room area 2015: Awarded the most efficient production plant in Austria 1,800 product types 35 technology families 16,3 billion chips (FY 2016) Wafer diameters: 150, 200, 300 mm Materials: Si, SiC, GaN 8
Advanced R&D eco-system and development partnerships make GaN a reality PowerBase Enhanced substrates and GaN pilot lines enabling compact power applications 39 Partners 9 Countries 87 million Cost 37 million Grant 6028 Person months 8 Work packages Time line 2015-2018 9
PowerBase goes beyond state-of-the-art: Most advanced GaN epi and devices GaN-on-Si hetero epitaxy pilot line Breakdown voltage > 1000 V Wafer bow (std. thickness) < 50 µm Dynamic Ron @600 V < 10% 150 mm GaN process pilot line Norm-On process line established Contact resistance R c < 0.5 Wmm Off-State leakage I dss < 100 na/mm Mechanical yield > 90% Advanced Process Modules Installation of a full scale industrial manufacturing line for large wafer diameter GaN-on-Si technology including the GaN hetero epitaxy on silicon wafers for normally-on and normally-off power transistors with a wide range of voltage classes up to 600 V. This WP lays the foundation for an European high volume manufacturing base for advanced GaN power electronics. Norm-Off process established Fully recessed 1 st barrier Regrowth of 2 nd barrier and p-gan layer Excellent V th stability 10
Industrial Implementation: Quality
Reliability: Differences vs. well-known Silicon devices are in focus Si Mature technology GaN Standards yet to be defined 1 2 3 4 S p D n G n+ p+ S 1 p-n body diode and termination stressed during HTRB 2 3 4 Gate oxide dielectric stressed by HTGB test Passivation and mould compound stressed by Temperature, Humidity and Bias (THB) and autoclave (AC) tests Top aluminum metal and wire bonds stressed during temperature cycling (TC) 1 2 3 4 GaN G 2 Si 2DEG channel and GaN buffer stressed by HTRB and IOL tests Gate module stressed by HTGB test Top interlevel dielectrics, top metal and wire bonds stressed during TC Passivation and mould compound stressed by THB and AC tests Reliability testing tailored to the GaN material system 3 1 And many more 4 D 12
Lifetime testing CoolGaN TM 70 mω-toll Lifetime projection at 480 V & 125 C Life Time Model: LL tt = AA ee γγγγ ee EE aa kkkk JEDEC testing 3 x 77 parts, 480 V, 1000 h 1 FIT Lifetime requirement: < 1 FIT for 15 years at 480 V, 125 C Very tight distribution (high ß good process control) The conservative model predicts a lifetime of ~55 years at 1 FIT, 480 V and 125 C > 3X safety margin 13
Dynamic R DS(on) : How to test? As implicated by it's name dynamic R DS(on) testing is strongly dependent on timing as the trapped charges relax with time Competition is typically giving dynr DS(on) data measured 2.5 µs after turn-on for 400 V Infineon CoolGaN For hundreds of khz up to MHz switching this is not enough E.g. 40% dynr DS(on) turns a 35 mω device into a 50 mω one Infineon's CoolGaN has been characterized down to 100 ns for a full 600 V blocking with no dynr DS(on) increase We have 100% test coverage with 600 V / 700 ns 14
Dynamic R DS(on) 600 V CoolGaN technology reliability Application level test example Dyn. R DS(on) measured real time during hard switching! At full rate Percent by which Rds(on) shifts 70% 60% 50% 40% 30% 20% 10% 0% -10% Percent Dynamic R DS (ON) shift vs. applied voltage Infineon measurement: Some competitor parts show increase in dyn. RDSON above 400V Published data for competitor listed as 0% up to 400V (no data > 400V) 100 200 300 400 500 600 applied voltage (Volts) Competitor X Infineon Data taken at 25 C, with 700ns delay after device turns on Negligible shift at full rated voltage True application measurements taken a few hundreds ns after hard switching device turn on! Still no impacts on datasheet! 15
Device level stress with application related test setup PFC ruggedness test system is used to prove reliable performance of GaN technology under application conditions Ω Ω 16
Application-related reliability test concept for GaN HEMT power devices established How to assure device reliability under application conditions? JEDEC qualification TC, HTRB, IOL Lab testing SOA, double pulse Customer life test @ system level Device level stress testing with application related test setup External devices Active Load Power Supply Host PC Application board Guard Switch Ethernet Blocking Diodes I SENS V SENS Control module PWM GaN test board I OUT I IN GaN GaN Totem Pole PFC Boost stage 700 V / 20 A / 250 khz max. 17
Value Proposition & Application Examples
PFC GaN enables simpler and more efficient topologies Nowadays, several high efficiency topologies for CCM PFC are available. BOM costs and part count depend on efficiency targets Interleaved Stages Bridge Rectifier AC IN L2 L1 Q1 D1 Q2 D2 Cbus Body diode (Qrr) prevents half bridge topologies Dual Boost AC IN D3 D4 L2 L1 Q1 D1 Q2 D2 Cbus GaN technology enables to use simpler and cost effective HalfBridge / Hard switching topologies and at the same time to achieve higher efficiency HB TOTEMPOLE 400 V FB TOTEMPOLE 400 V AC IN L1 Q1 D1 GaN has zero Qrr AC IN L1 Q1 Q3 Q2 D2 Q2 Q4 The investment on GaN has a compelling payback which allows to absorb very rapidly the initial higher costs of GaN switches 19
Performance of Full-Bridge PFC FB TOTEMPOLE 400 V Efficiency vs Load (f sw = 45kHz) * AC IN L1 Q1 Q3 Q2 Q4 IGLD60R070D1 MEASURED VALUES All available boards within +/- 0.1% 2x 70 mohm CoolGaN in DFN8x8 2x 33mOhm CoolMOS (2x 1EDI for GaN) (2x Driver IC for CoolMOS) FLAT EFFICIENCY > 99% over wide load range * No external power supplies everything included. Vin = 230 V ac, Vout = 390 V dc, t = 25 C Ambient 20
Typical application example: High-Power SMPS Totem-Pole Full-Bridge PFC Stage LLC Resonant DC-DC with Sync Rectifier CoolGaN Half-bridge + CoolMOS Half-bridge CoolGaN Full-bridge OptiMOS Sync-Rect (LV GaN in development) 21
Actual power density of mobile chargers Source: X.Huang, F. Lee, Q. Li, "High efficiency high density GaN based AC/DC adapter" Power management consortium meeting, Santa Clara, Aug 2016 22
can be doubled with GaN 93.5% efficiency @ 90 V AC 24 W/in 3 20 15 10 5 Source: X.Huang, F. Lee, Q. Li, "High efficiency high density GaN based AC/DC adapter" Power management consortium meeting, Santa Clara, Aug 2016 23
Conclusion GaN will enable a significant step forward towards energy efficiency and size & weight reduction in a variety of applications Emode (normoff) will likely be the ultimate concept to exploit full potential of GaN, targeting innovative, integrated solutions in the long term Key GaN device FOM's are demonstrated with 10x improvement over silicon (Qoss, Qg) and zero Qrr Stable 6" GaN epitaxy and device processes are available in Si power fab Infineon is committed to maintaining its differentiating quality standards in new technologies such as GaN without compromise on quality and reliability Infineon's reliable CoolGaN is ready for the mass market now 24
Acknowledgement The project "PowerBase" has received funding from the Electronic Component Systems for European Leadership Joint Undertaking under grant agreement No 662133. A big Thank You to all colleagues and partners involved in Infineon's GaN program! This Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation program and from Austria, Belgium, Germany, Italy, Netherlands, Norway, Slovakia, Spain and the United Kingdom. 25
Summary of GaN benefits Technology 600 V Lateral p-gate HEMT R DSon [typ mω] R DS *Q OSS [mωµc] R DS *Q RR [mωµc] R DS *E OSS [mωµj] R DS *Q G [mωnc] 55 2.2 0 350 320 10x higher breakdown field and 2x higher mobility 10x lower output charge Zero reverse recovery charge 10x lower gate charge and linear C oss characteristic Very low R DS(on) and large cost-down potential Better efficiency in resonant circuits New topologies and current modulation Fast and (near) lossless switching 27