CMOS Digital Integrated Circuits 74HC29D Silicon Monolithic 74HC29D 1. Functional Description -Bit Addressable Latch 2. General The 74HC29D is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable input G is held low, the data is written into the bit selected by address inputs, the other biold their previous conditio. When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other inputs. When both of CLEAR and G held low, all bits which isn't selected by adress inputs are resent to low. All inputs are equipped with protection circuits agait static discharge or traient excess voltage. 3. Features (1) High speed: t pd = 1 (typ.) at CC = (2) Low power dissipation: I CC = 4. (max) at T a = 2 (3) Balanced propagation delays: t PLH t PHL (4) Wide operating voltage range: CC(opr) = to 4. Packaging SOIC16 1 Start of commercial production 216-
. Pin Assignment 6. Marking 7. IEC Logic 2
. Truth Table D: The level at the data input QiO: The level before the indicared steady-state input conditio were established (i =, 1,... 7) 9. System Diagram 3
1. Absolute imum Ratings (Note) Note Rating Supply voltage Input voltage Output voltage Input diode current Output diode current Output current CC /ground current Power dissipation Storage temperature CC IN OUT I IK I OK I OUT I CC P D T stg (Note 1) -. to 7. -. to CC +. -. to CC +. ±2 ±2 ±2 ± -6 to 1 Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditio (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ( Handling Precautio / Derating Concept and Methods ) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: P D derates linearly with - mw/ above 11. Operating Ranges (Note) ma ma ma ma mw Rating Supply voltage Input voltage Output voltage Operating temperature Input rise and fall times Note: CC IN OUT T opr t r,t f to to CC to CC -4 to 12 to The operating ranges are required to eure the normal operation of the device. Unused inputs must be tied to either CC or GND. µs 4
12. Electrical 12.1. DC (Unless otherwise specified, T a = 2 ) CC () Typ. High-level input voltage IH 1. 3.1 4.2 Low-level input voltage IL. 1.3 1. High-level output voltage OH IN = IH or IL I OH = -2 1.9 4.4.9 I OH = -4 ma 4.1 4.31 I OH = -.2 ma.6. Low-level output voltage OL IN = IH or IL I OL = 2... I OL = 4 ma 7.26 I OL =.2 ma.26 Input leakage current I IN IN = CC or GND ± Quiescent supply current I CC IN = CC or GND 4. 12.2. DC (Unless otherwise specified, T a = -4 to ) CC () High-level input voltage IH 1. 3.1 4.2 Low-level input voltage IL. 1.3 1. High-level output voltage OH IN = IH or IL I OH = -2 1.9 4.4.9 I OH = -4 ma 4.13 I OH = -.2 ma.63 Low-level output voltage OL IN = IH or IL I OL = 2 I OL = 4 ma.33 I OL =.2 ma.33 Input leakage current I IN IN = CC or GND ±1. Quiescent supply current I CC IN = CC or GND 4.
12.3. DC (Unless otherwise specified, T a = -4 to 12 ) CC () High-level input voltage IH 1. 3.1 4.2 Low-level input voltage IL. 1.3 1.3 High-level output voltage OH IN = IH or IL I OH = -2 1.9 4.4.9 I OH = -4 ma 3.7 I OH = -.2 ma.2 Low-level output voltage OL IN = IH or IL I OL = 2 I OL = 4 ma.4 I OL =.2 ma.4 Input leakage current I IN IN = CC or GND ±1. Quiescent supply current I CC IN = CC or GND 16. 13. Timing Requirements (Unless otherwise specified, T a = 2,, Input: tr = tf = 6 ) CC () Limit imum pulse width (G) 7 1 13 imum pulse width (CLEAR) 7 1 13 imum setup time 1 9 imum setup time 2 imum hold time 2 imum hold time 6
13.1. Timing Requirements (Unless otherwise specified, T a = -4 to,, Input: t r = t f = 6 ) CC () Limit imum pulse width (G) 9 19 16 imum pulse width (CLEAR) 9 19 16 imum setup time 6 12 11 imum setup time 3 6 imum hold time 3 6 imum hold time 13.2. Timing Requirements (Unless otherwise specified, T a = -4 to 12,, Input: t r = t f = 6 ) CC () Limit imum pulse width (G) 11 23 2 imum pulse width (CLEAR) 11 23 2 imum setup time 7 1 13 imum setup time 4 7 imum hold time 4 7 imum hold time 7
14. AC (Unless otherwise specified, C L = 1 pf, CC =, T a = 2,, Input: t r = t f = 6 ) Typ. Output traition time t TLH,t THL 4 (DATA IN - Q) 1 22 (A, B, C - Q) 21 32 (G - Q) 16 2 (CLEAR - Q) t PHL 13 23 14.1. AC (Unless otherwise specified, C L = pf, T a = 2,, Input: t r = t f = 6 ) Note CC () Typ. Output traition time (DATA IN - Q) (A, B, C - Q) (G - Q) (CLEAR - Q) Input capacitance Power dissipation capacitance t TLH,t THL t PHL C IN C PD (Note 1) Note 1: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation. I CC(opr) = C PD CC f IN + I CC 3 7 6 1 1 3 2 21 67 2 17 2 16 14 3 7 1 13 13 26 22 1 37 31 16 33 2 13 27 23 pf pf
14.2. AC (Unless otherwise specified, C L = pf, T a = -4 to,, Input: t r = t f = 6 ) CC () Output traition time t TLH,t THL 9 19 16 (DATA IN - Q) 16 33 2 (A, B, C - Q) 23 46 39 (G - Q) 2 41 3 (CLEAR - Q) t PHL 17 34 29 14.3. AC (Unless otherwise specified, C L = pf, T a = -4 to 12,, Input: t r = t f = 6 ) CC () Output traition time t TLH,t THL 11 23 2 (DATA IN - Q) 19 39 33 (A, B, C - Q) 2 6 4 (G - Q) 23 47 4 (CLEAR - Q) t PHL 2 41 3 9
Package Dimeio : mm Weight: g (typ.) Package Name(s) Nickname: SOIC16 1
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