6 7 8 9 CC1101 CC1101 Low-Cost Low-Power Sub-1GHz RF Transceiver (Enhanced CC1100 ) Applications Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands Wireless alarm and security systems Industrial monitoring and control Product Description The CC1101 is a low-cost sub- 1 GHz transceiver designed for very low-power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868, and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-348 MHz, 387-464 MHz and 779-928 MHz bands. CC1101 is an improved and code compatible version of the CC1100 RF transceiver. The main improvements on the CC1101 include: Improved spurious response Better close-in phase noise improving Adjacent Channel Power (ACP) performance Higher input saturation level Improved output power ramping Extended frequency bands of operation, i.e. CC1100: 400-464 MHz and 800-928 MHz CC1101: 387-464 MHz and 779-928 MHz Wireless sensor networks AMR Automatic Meter Reading Home and building automation The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kbaud. CC1101 provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. The main operating parameters and the 64- byte transmit/receive FIFOs of CC1101 can be controlled via an SPI interface. In a typical system, the CC1101 will be used together with a microcontroller and a few additional passive components. 1 2 3 4 5 20 19 18 17 CC1101 16 10 15 14 13 12 11 SWRS061B Page 1 of 93
Key Features RF Performance High sensitivity ( 111 dbm at 1.2 kbaud, 868 MHz, 1% packet error rate) Low current consumption (14.7 ma in RX, 1.2 kbaud, 868 MHz) Programmable output power up to +10 dbm for all supported frequencies Excellent receiver selectivity and blocking performance Programmable data rate from 1.2 to 500 kbaud Frequency bands: 300-348 MHz, 387-464 MHz and 779-928 MHz Analog Features 2-FSK, GFSK, and MSK supported as well as OOK and flexible ASK shaping Suitable for frequency hopping systems due to a fast settling frequency synthesizer: 90us settling time Automatic Frequency Compensation (AFC) can be used to align the frequency synthesizer to the received center frequency Integrated analog temperature sensor Digital Features Flexible support for packet oriented systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling Efficient SPI interface: All registers can be programmed with one burst transfer Digital RSSI output Programmable channel filter bandwidth Programmable Carrier Sense (CS) indicator Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support for per-package Link Quality Indication (LQI) Optional automatic whitening and dewhitening of data Low-Power Features 400 na sleep mode current consumption Fast startup time: 240us from sleep to RX or TX mode (measured on EM reference design [5] and [6]) Wake-on-radio functionality for automatic low-power RX polling Separate 64-byte RX and TX data FIFOs (enables burst mode data transmission) General Few external components: Completely onchip frequency synthesizer, no external filters or RF switch needed Green package: RoHS compliant and no antimony or bromine Small size (QLP 4x4 mm package, 20 pins) Suited for systems targeting compliance with EN 300 220 (Europe) and FCC CFR Part 15 (US). Support for asynchronous and synchronous serial receive/transmit mode for backwards compatibility with existing radio communication protocols SWRS061B Page 2 of 93
Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power MSK Minimum Shift Keying ADC Analog to Digital Converter N/A Not Applicable AFC Automatic Frequency Compensation NRZ Non Return to Zero (Coding) AGC Automatic Gain Control OOK On-Off Keying AMR Automatic Meter Reading PA Power Amplifier ASK Amplitude Shift Keying PCB Printed Circuit Board BER Bit Error Rate PD Power Down BT Bandwidth-Time product PER Packet Error Rate CCA Clear Channel Assessment PLL Phase Locked Loop CFR Code of Federal Regulations POR Power-On Reset CRC Cyclic Redundancy Check PQI Preamble Quality Indicator CS Carrier Sense PQT Preamble Quality Threshold CW Continuous Wave (Unmodulated Carrier) PTAT Proportional To Absolute Temperature DC Direct Current QLP Quad Leadless Package DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying ESR Equivalent Series Resistance RC Resistor-Capacitor FCC Federal Communications Commission RF Radio Frequency FEC Forward Error Correction RSSI Received Signal Strength Indicator FIFO First-In-First-Out RX Receive, Receive Mode FHSS Frequency Hopping Spread Spectrum SAW Surface Aqustic Wave 2-FSK Binary Frequency Shift Keying SMD Surface Mount Device GFSK Gaussian shaped Frequency Shift Keying SNR Signal to Noise Ratio IF Intermediate Frequency SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Devices ISM Industrial, Scientific, Medical TBD To Be Defined LC Inductor-Capacitor T/R Transmit/Receive LNA Low Noise Amplifier TX Transmit, Transmit Mode LO Local Oscillator UHF Ultra High frequency LSB Least Significant Bit VCO Voltage Controlled Oscillator LQI Link Quality Indicator WOR Wake on Radio, Low power polling MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most Significant Bit XTAL Crystal SWRS061B Page 3 of 93
Table Of Contents APPLICATIONS...1 PRODUCT DESCRIPTION...1 KEY FEATURES...2 RF PERFORMANCE...2 ANALOG FEATURES...2 DIGITAL FEATURES...2 LOW-POWER FEATURES...2 GENERAL...2 ABBREVIATIONS...3 TABLE OF CONTENTS...4 1 ABSOLUTE MAXIMUM RATINGS...7 2 OPERATING CONDITIONS...7 3 GENERAL CHARACTERISTICS...7 4 ELECTRICAL SPECIFICATIONS...8 4.1 CURRENT CONSUMPTION...8 4.2 RF RECEIVE SECTION...10 4.3 RF TRANSMIT SECTION...12 4.4 CRYSTAL OSCILLATOR...13 4.5 LOW POWER RC OSCILLATOR...14 4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS...14 4.7 ANALOG TEMPERATURE SENSOR...15 4.8 DC CHARACTERISTICS...15 4.9 POWER-ON RESET...15 5 PIN CONFIGURATION...16 6 CIRCUIT DESCRIPTION...17 7 APPLICATION CIRCUIT...18 8 CONFIGURATION OVERVIEW...21 9 CONFIGURATION SOFTWARE...23 10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE...23 10.1 CHIP STATUS BYTE...25 10.2 REGISTER ACCESS...25 10.3 SPI READ...26 10.4 COMMAND STROBES...26 10.5 FIFO ACCESS...26 10.6 PATABLE ACCESS...27 11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...27 11.1 CONFIGURATION INTERFACE...27 11.2 GENERAL CONTROL AND STATUS PINS...27 11.3 OPTIONAL RADIO CONTROL FEATURE...28 12 DATA RATE PROGRAMMING...28 13 RECEIVER CHANNEL FILTER BANDWIDTH...29 14 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION...29 14.1 FREQUENCY OFFSET COMPENSATION...29 14.2 BIT SYNCHRONIZATION...29 14.3 BYTE SYNCHRONIZATION...30 15 PACKET HANDLING HARDWARE SUPPORT...30 15.1 DATA WHITENING...31 15.2 PACKET FORMAT...31 15.3 PACKET FILTERING IN RECEIVE MODE...33 SWRS061B Page 4 of 93
15.4 PACKET HANDLING IN TRANSMIT MODE...33 15.5 PACKET HANDLING IN RECEIVE MODE...34 15.6 PACKET HANDLING IN FIRMWARE...34 16 MODULATION FORMATS...35 16.1 FREQUENCY SHIFT KEYING...35 16.2 MINIMUM SHIFT KEYING...35 16.3 AMPLITUDE MODULATION...35 17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION...36 17.1 SYNC WORD QUALIFIER...36 17.2 PREAMBLE QUALITY THRESHOLD (PQT)...36 17.3 RSSI...36 17.4 CARRIER SENSE (CS)...38 17.5 CLEAR CHANNEL ASSESSMENT (CCA)...39 17.6 LINK QUALITY INDICATOR (LQI)...39 18 FORWARD ERROR CORRECTION WITH INTERLEAVING...39 18.1 FORWARD ERROR CORRECTION (FEC)...39 18.2 INTERLEAVING...40 19 RADIO CONTROL...41 19.1 POWER-ON START-UP SEQUENCE...41 19.2 CRYSTAL CONTROL...42 19.3 VOLTAGE REGULATOR CONTROL...43 19.4 ACTIVE MODES...43 19.5 WAKE ON RADIO (WOR)...43 19.6 TIMING...44 19.7 RX TERMINATION TIMER...45 20 DATA FIFO...45 21 FREQUENCY PROGRAMMING...47 22 22.1 VCO...47 VCO AND PLL SELF-CALIBRATION...47 23 VOLTAGE REGULATORS...48 24 OUTPUT POWER PROGRAMMING...48 25 SHAPING AND PA RAMPING...49 26 SELECTIVITY...51 27 27.1 CRYSTAL OSCILLATOR...52 REFERENCE SIGNAL...53 28 EXTERNAL RF MATCH...53 29 PCB LAYOUT RECOMMENDATIONS...53 30 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS...54 31 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION...56 31.1 ASYNCHRONOUS OPERATION...56 31.2 SYNCHRONOUS SERIAL OPERATION...56 32 SYSTEM CONSIDERATIONS AND GUIDELINES...56 32.1 SRD REGULATIONS...56 32.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS...57 32.3 WIDEBAND MODULATION NOT USING SPREAD SPECTRUM...57 32.4 DATA BURST TRANSMISSIONS...57 32.5 CONTINUOUS TRANSMISSIONS...58 32.6 CRYSTAL DRIFT COMPENSATION...58 32.7 SPECTRUM EFFICIENT MODULATION...58 32.8 LOW COST SYSTEMS...58 32.9 BATTERY OPERATED SYSTEMS...58 32.10 INCREASING OUTPUT POWER...58 SWRS061B Page 5 of 93
33 CONFIGURATION REGISTERS...59 33.1 CONFIGURATION REGISTER DETAILS REGISTERS WITH PRESERVED VALUES IN SLEEP STATE...63 33.2 CONFIGURATION REGISTER DETAILS REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE...83 33.3 STATUS REGISTER DETAILS...84 34 PACKAGE DESCRIPTION (QLP 20)...87 34.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20)...88 34.2 PACKAGE THERMAL PROPERTIES...88 34.3 SOLDERING INFORMATION...88 34.4 TRAY SPECIFICATION...88 34.5 CARRIER TAPE AND REEL SPECIFICATION...89 35 ORDERING INFORMATION...89 36 REFERENCES...90 37 GENERAL INFORMATION...91 37.1 DOCUMENT HISTORY...91 37.2 PRODUCT STATUS DEFINITIONS...91 38 ADDRESS INFORMATION...92 39 TI WORLDWIDE TECHNICAL SUPPORT...92 SWRS061B Page 6 of 93
1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Parameter Min Max Units Condition Supply voltage 0.3 3.9 V All supply pins must have the same voltage Voltage on any digital pin 0.3 VDD + 0.3 max 3.9 Voltage on the pins RF_P, RF_N, and DCOUPL 0.3 2.0 V Voltage ramp-up rate 120 kv/µs Input RF level +10 dbm Storage temperature range 50 150 C Solder reflow temperature 260 C According to IPC/JEDEC J-STD-020C ESD 750 V According to JEDEC STD 22, method A114, Human Body Model (HBM) ESD 400 V According to JEDEC STD 22, C101C, Charged Device Model (CDM) Table 1: Absolute Maximum Ratings V 2 Operating Conditions The operating conditions for CC1101 are listed Table 2 in below. Parameter Min Max Unit Condition Operating temperature -40 85 C Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage Table 2: Operating Conditions 3 General Characteristics Parameter Min Typ Max Unit Condition/Note Frequency range 300 348 MHz 387 464 MHz 779 928 MHz Data rate 1.2 500 kbaud 2-FSK 1.2 250 kbaud GFSK, OOK, and ASK 26 500 kbaud (Shaped) MSK (also known as differential offset QPSK) Optional Manchester encoding (the data rate in kbps will be half the baud rate) Table 3: General Characteristics SWRS061B Page 7 of 93
4 Electrical Specifications 4.1 Current Consumption Tc = 25 C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([5] and [6]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See for additional details on current consumption and sensitivity. Parameter Min Typ Max Unit Condition Current consumption in power down modes 0.2 1 µa Voltage regulator to digital part off, register values retained (SLEEP state). All GDO pins programmed to 0x2F (HW to 0) 0.5 µa Voltage regulator to digital part off, register values retained, lowpower RC oscillator running (SLEEP state with WOR enabled 100 µa Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) 165 µa Voltage regulator to digital part on, all other modules in power down (XOFF state) Current consumption 9.8 µa Automatic RX polling once each second, using low-power RC oscillator, with 460 khz filter bandwidth and 250 kbaud data rate, PLL calibration every 4 th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 34.2 µa Same as above, but with signal in channel above carrier sense level, 1.95 ms RX timeout, and no preamble/sync word found. 1.5 µa Automatic RX polling every 15 th second, using low-power RC oscillator, with 460kHz filter bandwidth and 250 kbaud data rate, PLL calibration every 4 th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 39.3 µa Same as above, but with signal in channel above carrier sense level, 29.3 ms RX timeout, and no preamble/sync word found. 1.7 ma Only voltage regulator to digital part and crystal oscillator running (IDLE state) 8.4 ma Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state. Current consumption, 315MHz 15.4 ma Receive mode, 1.2 kbaud, reduced current, input at sensitivity limit 14.4 ma Receive mode, 1.2 kbaud, reduced current, input well above sensitivity limit 15.2 ma Receive mode, 38.4 kbaud, reduced current, input at sensitivity limit 14.3 ma Receive mode,38.4 kbaud, reduced current, input well above sensitivity limit 16.5 ma Receive mode, 250 kbaud, reduced current, input at sensitivity limit 15.1 ma Receive mode, 250 kbaud, reduced current, input well above sensitivity limit 27.4 ma Transmit mode, +10 dbm output power 15.0 ma Transmit mode, 0 dbm output power 12.3 ma Transmit mode, 6 dbm output power SWRS061B Page 8 of 93
Parameter Min Typ Max Unit Condition Current consumption, 433MHz Current consumption, 868/915MHz 16.0 ma Receive mode, 1.2 kbaud, reduced current, input at sensitivity limit 15.0 ma Receive mode, 1.2 kbaud, reduced current, input well above sensitivity limit 15.7 ma Receive mode, 38.4 kbaud, reduced current, input at sensitivity limit 15.0 ma Receive mode, 38.4 kbaud, reduced current, input well above sensitivity limit 17.1 ma Receive mode, 250 kbaud, reduced current, input at sensitivity limit 15.7 ma Receive mode, 250 kbaud, reduced current, input well above sensitivity limit 29.2 ma Transmit mode, +10 dbm output power 16.0 ma Transmit mode, 0 dbm output power 13.1 ma Transmit mode, 6 dbm output power 15.7 ma Receive mode, 1.2 kbaud, reduced current, input at sensitivity limit 14.7 ma Receive mode, 1.2 kbaud, reduced current, input well above sensitivity limit 15.6 ma Receive mode, 38.4 kbaud, reduced current, input at sensitivity limit 14.6 ma Receive mode, 38.4 kbaud, reduced current, input well above sensitivity limit 16.9 ma Receive mode, 250 kbaud, reduced current, input at sensitivity limit 15.6 ma Receive mode, 250 kbaud, reduced current, input well above sensitivity limit 32.3 ma Transmit mode, +10 dbm output power 16.8 ma Transmit mode, 0 dbm output power 13.1 ma Transmit mode, 6 dbm output power Table 4: Electrical Specifications SWRS061B Page 9 of 93
4.2 RF Receive Section Tc = 25 C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Digital channel filter bandwidth 58 812 khz User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.0 MHz crystal). 315 MHz, 1.2 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 khz deviation, 58 khz digital channel filter bandwidth) Receiver sensitivity -111 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.2 ma to 15.4 ma at sensitivity limit. The sensitivity is typically reduced to -109 dbm 315 MHz, 500 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kbaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 khz digital channel filter bandwidth) -88 dbm 433 MHz, 1.2 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 5.2 khz deviation, 58 khz digital channel filter bandwidth Receiver sensitivity -112 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.0 ma to 16.0 ma at sensitivity limit. The sensitivity is typically reduced to -110 dbm 433 MHz, 38.4 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 20 khz deviation, 100 khz digital channel filter bandwidth) Receiver sensitivity 104 dbm 433 MHz, 250 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 127 khz deviation, 540 khz digital channel filter bandwidth) Receiver sensitivity -95 dbm 868 MHz, 1.2 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 khz deviation, 58 khz digital channel filter bandwidth) Receiver sensitivity 111 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.0 ma to 15.7 ma at sensitivity limit. The sensitivity is typically reduced to -109 dbm Saturation 14 dbm FIFOTHR.CLOSE_IN_RX=0 Adjacent channel rejection Alternate channel rejection Image channel rejection, 868MHz 37 db Desired channel 3 db above the sensitivity limit. 100 khz channel spacing 37 db Desired channel 3 db above the sensitivity limit. 100 khz channel spacing See Figure 24 for plot of selectivity versus frequency offset 31 db IF frequency 152 khz Desired channel 3 db above the sensitivity limit. 868 MHz, 38.4 kbaud data rate, sensitivity optimized (GFSK, 1% packet error rate, 20 bytes packet length, 20 khz deviation, 100 khz digital channel filter bandwidth) Receiver sensitivity 103 dbm Saturation 16 dbm Adjacent channel rejection Alternate channel rejection Image channel rejection, 868MHz 20 db Desired channel 3 db above the sensitivity limit. 200 khz channel spacing 30 db Desired channel 3 db above the sensitivity limit. 200 khz channel spacing See Figure 25 for plot of selectivity versus frequency offset 23 db IF frequency 152 khz Desired channel 3 db above the sensitivity limit. SWRS061B Page 10 of 93
Parameter Min Typ Max Unit Condition/Note 868 MHz, 250 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 khz digital channel filter bandwidth) Receiver sensitivity 94 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 19.2 ma to 16.9 ma at sensitivity limit. The sensitivity is typically reduced to -91 dbm Saturation 17 dbm FIFOTHR.CLOSE_IN_RX=0 Adjacent channel rejection 25 db Desired channel 3 db above the sensitivity limit. 750 khz channel spacing Alternate channel rejection Image channel rejection, 868MHz 40 db Desired channel 3 db above the sensitivity limit. 750 khz channel spacing See Figure 26 for plot of selectivity versus frequency offset 17 db IF frequency 304 khz Desired channel 3 db above the sensitivity limit. 915 MHz, 1.2 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 khz digital channel filter bandwidth) Receiver sensitivity 111 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.0 ma to 15.7 ma at sensitivity limit. The sensitivity is typically reduced to -109 dbm 915 MHz, 38.4 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 20 khz deviation, 100 khz digital channel filter bandwidth) Receiver sensitivity 103 dbm 915 MHz, 250 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 khz digital channel filter bandwidth) Receiver sensitivity 94 dbm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 19.2 ma to 16.9 ma at sensitivity limit. The sensitivity is typically reduced to -91 dbm 915 MHz, 500 kbaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kbaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 khz digital channel filter bandwidth) Receiver sensitivity 87 dbm Blocking Blocking at ±2 MHz offset, 1.2 kbaud, 868 MHz Blocking at ±2 MHz offset, 500 kbaud, 868 MHz Blocking at ±10 MHz offset, 1.2 kbaud, 868 MHz Blocking at ±10 MHz offset, 500 kbaud, 868 MHz -50 dbm Desired channel 3dB above the sensitivity limit. -50 dbm Desired channel 3dB above the sensitivity limit -39 dbm Desired channel 3dB above the sensitivity limit. -40 dbm Desired channel 3dB above the sensitivity limit. SWRS061B Page 11 of 93
Parameter Min Typ Max Unit Condition/Note General Spurious emissions -68-66 57 47 dbm dbm Table 5: RF Receive Section 25 MHz 1 GHz (Maximum figure is the ETSI EN 300 220 limit) Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit) Typical radiated spurious emission is -49 db measured at the VCO frequency. RX latency 9 bit Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit. 4.3 RF Transmit Section Tc = 25 C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Differential load impedance 315 MHz 433 MHz 868/915 MHz Output power, highest setting Output power, lowest setting 122 + j31 116 + j41 86.5 + j43 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1101EM reference design ([5] and [6]) available from theti website. +10 dbm Output power is programmable, and full range is available in all frequency bands (Output power may be restricted by regulatory limits. See also Application Note AN039 [3]. Delivered to a 50Ω single-ended load via CC1101EM reference design ([5] and [6]) RF matching network. -30 dbm Output power is programmable, and full range is available in all frequency bands. Delivered to a 50Ω single-ended load via CC1101EM reference design([5] and [6]) RF matching network. Harmonics, radiated Measured on CC1101EM reference designs([5] and [6]) with CW, 10dBm output power 2 nd Harm, 433 MHz 3 rd Harm, 433 MHz -49-40 dbm The antennas used during the radiated measurements (SMAFF- 433 from R.W.Badland and Nearson S331 868/915) play a part in attenuating the harmonics 2 nd Harm, 868 MHz 3 rd Harm, 868 MHz -39-64 Harmonics, conducted Measured with 10 dbm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz, or 915.00 MHz 315 MHz < -35 < -53 dbm Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < -43 < -45 Frequencies below 1 GHz Frequencies above 1 GHz 868 MHz < -39 915 MHz < -33 SWRS061B Page 12 of 93
Parameter Min Typ Max Unit Condition/Note Spurious emissions, conducted Harmonics not included 315 MHz < -58 < -53 dbm Measured with 10 dbm CW, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz or 915.00 MHz Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < -50 < -54 < -56 Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz 868 MHz 915 MHz General < -50 < -51 < -53 < -51 < -51 Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz. All radiated spurious emissions are within the limits of ETSI. The peak conducted spurious emission is -53 dbm at 699 MHz, which is in a frequency band limited to -54 dbm by EN 300 220. An alternative filter that can be used to reduce the emission at 699 MHz below -54 dbm, for conducted measurements, is shown in Figure 4. Frequencies below 960 MHz Frequencies above 960 MHz TX latency 8 bit Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports. Table 6: RF Transmit Section 4.4 Crystal Oscillator Tc = 25 C @ VDD = 3.0 V if nothing else is stated. Parameter Min Typ Max Unit Condition/Note Crystal frequency 26 26 27 MHz Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. ESR 100 Ω Start-up time 150 µs Measured on the CC1101EM reference designs ([5] and [6]) using crystal AT-41CD2 from NDK. This parameter is to a large degree crystal dependent. Table 7: Crystal Oscillator Parameters SWRS061B Page 13 of 93
4.5 Low Power RC Oscillator Tc = 25 C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([5] and [6]). Parameter Min Typ Max Unit Condition/Note Calibrated frequency 34.7 34.7 36 khz Calibrated RC Oscillator frequency is XTAL frequency divided by 750 Frequency accuracy after calibration ±1 % Temperature coefficient +0.5 % / C Frequency drift when temperature changes after calibration Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after calibration Initial calibration time 2 ms When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Table 8: RC Oscillator Parameters 4.6 Frequency Synthesizer Characteristics Tc = 25 C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference designs ([5] and [6]). Min figures are given using a 27 MHz crystal. Typ and max are given using a 26 MHz crystal. Parameter Min Typ Max Unit Condition/Note Programmed frequency resolution Synthesizer frequency tolerance 412 Hz 26-27 MHz crystal. 397 F XOSC / 2 16 The resolution (in Hz) is equal for all frequency bands. ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing. RF carrier phase noise 92 dbc/hz @ 50 khz offset from carrier RF carrier phase noise 92 dbc/hz @ 100 khz offset from carrier RF carrier phase noise 92 dbc/hz @ 200 khz offset from carrier RF carrier phase noise 98 dbc/hz @ 500 khz offset from carrier RF carrier phase noise 107 dbc/hz @ 1 MHz offset from carrier RF carrier phase noise 113 dbc/hz @ 2 MHz offset from carrier RF carrier phase noise 119 dbc/hz @ 5 MHz offset from carrier RF carrier phase noise 129 dbc/hz @ 10 MHz offset from carrier PLL turn-on / hop time 85.1 88.4 88.4 µs Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running. PLL RX/TX settling time 9.3 9.6 9.6 µs Settling time for the 1 IF frequency step from RX to TX PLL TX/RX settling time 20.7 21.5 21.5 µs Settling time for the 1 IF frequency step from TX to RX PLL calibration time 694 721 721 µs Calibration can be initiated manually or automatically before entering or after leaving RX/TX. Table 9: Frequency Synthesizer Parameters SWRS061B Page 14 of 93
4.7 Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Parameter Min Typ Max Unit Condition/Note Output voltage at 40 C 0.651 V Output voltage at 0 C 0.747 V Output voltage at +40 C 0.847 V Output voltage at +80 C 0.945 V Temperature coefficient 2.45 mv/ C Fitted from 20 C to +80 C Error in calculated temperature, calibrated Current consumption increase when enabled -2 * 0 2 * C From 20 C to +80 C when using 2.45 mv / C, after 1-point calibration at room temperature 0.3 ma * The indicated minimum and maximum error with 1- point calibration is based on simulated values for typical process parameters Table 10: Analog Temperature Sensor Parameters 4.8 DC Characteristics Tc = 25 C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 ma output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 ma output current Logic "0" input current N/A 50 na Input equals 0V Logic "1" input current N/A 50 na Input equals VDD Table 11: DC Characteristics 4.9 Power-On Reset When the power supply complies with the requirements in Table 12 below, proper Power-On-Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 41 for further details. Parameter Min Typ Max Unit Condition/Note Power-up ramp-up time. 5 ms From 0V until reaching 1.8V Power off time 1 ms Minimum time between power-on and power-off Table 12: Power-On Reset Requirements SWRS061B Page 15 of 93
5 Pin Configuration SI GND DGUARD RBIAS GND 20 19 18 17 16 SCLK 1 SO (GDO1) 2 GDO2 3 DVDD 4 DCOUPL 5 15 AVDD 14 AVDD 13 RF_N 12 RF_P 11 AVDD 6 GDO0 (ATEST) 7 CSn 8 XOSC_Q1 9 AVDD 10 XOSC_Q2 GND Exposed die attach pad Figure 1: Pinout Top View Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip. Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output. Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use: Test signals FIFO status signals Clear Channel Indicator Clock output, down-divided from XOSC Serial output RX data 4 DVDD Power (Digital) 1.8-3.6 V digital power supply for digital I/O s and for the digital core voltage regulator 5 DCOUPL Power (Digital) 1.6-2.0 V digital power supply output for decoupling. NOTE: This pin is intended for use with the CC1101 only. It can not be used to provide supply voltage to other devices. 6 GDO0 (ATEST) Digital I/O Digital output pin for general use: Test signals FIFO status signals Clear Channel Indicator Clock output, down-divided from XOSC Serial output RX data Serial input TX data Also used as analog test I/O for prototype/production testing 7 CSn Digital Input Serial configuration interface, chip select 8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input 9 AVDD Power (Analog) 1.8-3.6 V analog power supply connection SWRS061B Page 16 of 93
Pin # Pin Name Pin type Description 10 XOSC_Q2 Analog I/O Crystal oscillator pin 2 11 AVDD Power (Analog) 1.8-3.6 V analog power supply connection 12 RF_P RF I/O Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 13 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 14 AVDD Power (Analog) 1.8-3.6 V analog power supply connection 15 AVDD Power (Analog) 1.8-3.6 V analog power supply connection 16 GND Ground (Analog) Analog ground connection 17 RBIAS Analog I/O External bias resistor for reference current 18 DGUARD Power (Digital) Power supply connection for digital noise isolation 19 GND Ground (Digital) Ground connection for digital noise isolation 20 SI Digital Input Serial configuration interface, data input Table 13: Pinout Overview 6 Circuit Description RADIO CONTROL RF_P RF_N LNA PA RC OSC BIAS 0 90 ADC ADC XOSC DEMODULATOR FREQ SYNTH MODULATOR FEC / INTERLEAVER PACKET HANDLER RXFIFO TXFIFO DIGITAL INTERFACE TO MCU SCLK SO (GDO1) SI CSn GDO0 (ATEST) GDO2 RBIAS XOSC_Q1 XOSC_Q2 Figure 2: CC1101 Simplified Block Diagram A simplified block diagram of CC1101 is shown in Figure 2. CC1101 features a low-if receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronization are performed digitally. The transmitter part of CC1101 is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part. A 4-wire SPI serial interface is used for configuration and data buffer access. The digital baseband includes support for channel configuration, packet handling, and data buffering. SWRS061B Page 17 of 93
7 Application Circuit Only a few external components are required for using the CC1101. The recommended application circuits are shown in Figure 3 and Figure 4. The external components are described in Table 14, and typical values are given in Table 15. Bias Resistor The bias resistor R171 is used to set an accurate bias current. Balun and RF Matching The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C121, L121 and L131 for the 315/433 MHz reference design [5]. L121, L131, C121, L122, C131, C122 and L132 for the 868/915 MHz reference design [6]) form a balun that converts the differential RF signal on CC1101 to a single-ended RF signal. C124 is needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 Ω antenna (or cable). Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table 15. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC1101EM reference design [5] and [6]. Crystal The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See Section 27 on page 52 for details. Additional Filtering Additional external components (e.g. an RF SAW filter) may be used in order to improve the performance in specific applications. Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC1101EM reference design ([5] and [6]) should be followed closely. Component C51 C81/C101 C121/C131 C122 C123 C124 C125 C126 C127 L121/L131 L122 L123 L124 L125 L132 R171 XTAL Description Decoupling capacitor for on-chip voltage regulator to digital part Crystal loading capacitors, see Section 27 on page 52 for details RF balun/matching capacitors RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz). RF LC filter/matching capacitor RF balun DC blocking capacitor RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna) RF LC filter/matching capacitor/dc-block (868/915 MHz) RF LC filter/matching capacitor (868/915 MHz) RF balun/matching inductors (inexpensive multi-layer type) RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz). (inexpensive multi-layer type) RF LC filter/matching filter inductor (inexpensive multi-layer type) RF LC filter/matching filter inductor (inexpensive multi-layer type) RF LC filter/matching filter inductor (inexpensive multi-layer type) (868/915 MHz) RF balun/matching inductor. (inexpensive multi-layer type) Resistor for internal bias current reference. 26MHz - 27MHz crystal, see Section 27 on page 52 for details. Table 14: Overview of External Components (excluding supply decoupling capacitors) SWRS061B Page 18 of 93
1.8V-3.6V power supply R171 SI Digital Inteface SCLK SO (GDO1) GDO2 (optional) C51 1 SCLK 2 SO (GDO1) 3 GDO2 4 DVDD 5 DCOUPL SI 20 6 GDO0 GND 19 7 CSn DGUARD 18 8 XOSC_Q1 RBIAS 17 CC1101 DIE ATTACH PAD: 9 AVDD GND 16 10 XOSC_Q2 AVDD 15 AVDD 14 RF_N 13 RF_P 12 AVDD 11 C131 L131 C121 L121 C124 L122 L123 C122 C125 C123 Antenna (50 Ohm) GDO0 (optional) CSn XTAL C81 C101 Figure 3: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors) Digital Interface 6 GDO0 7 CSn 8 XOSC_Q1 9 AVDD 10 XOSC_Q2 SI 20 GND 19 DGUARD 18 RBIAS 17 GND 16 Figure 4: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply decoupling capacitors) SWRS061B Page 19 of 93
Component Value at 315MHz Value at 433MHz Value at 868/915MHz Manufacturer C51 100 nf ± 10%, 0402 X5R Murata GRM1555C series C81 27 pf ± 5%, 0402 NP0 Murata GRM1555C series C101 27 pf ± 5%, 0402 NP0 Murata GRM1555C series C121 6.8 pf ± 0.5 pf, 0402 NP0 3.9 pf ± 0.25 pf, 0402 NP0 1.0 pf ± 0.25 pf, 0402 NP0 Murata GRM1555C series C122 12 pf ± 5%, 0402 NP0 8.2 pf ± 0.5 pf, 0402 NP0 1.5 pf ± 0.25 pf, 0402 NP0 Murata GRM1555C series C123 6.8 pf ± 0.5 pf, 0402 NP0 5.6 pf ± 0.5 pf, 0402 NP0 3.3 pf ± 0.25 pf, 0402 NP0 Murata GRM1555C series C124 220 pf ± 5%, 0402 NP0 220 pf ± 5%, 0402 NP0 100 pf ± 5%, 0402 NP0 Murata GRM1555C series C125 220 pf ± 5%, 0402 NP0 220 pf ± 5%, 0402 NP0 100 pf ± 5%, 0402 NP0 Murata GRM1555C series C126 2.2 pf ± 0.25%, 0402 NP0 C127 2.2 pf ± 0.25%, 0402 NP0 Murata GRM1555C series Murata GRM1555C series C131 6.8 pf ± 0.5 pf, 0402 NP0 3.9 pf ± 0.25 pf, 0402 NP0 1.5 pf ± 0.25 pf, 0402 NP0 Murata GRM1555C series L121 33 nh ± 5%, 0402 monolithic 27 nh ± 5%, 0402 monolithic 12 nh ± 5%, 0402 monolithic Murata LQG15HS series L122 18 nh ± 5%, 0402 monolithic 22 nh ± 5%, 0402 monolithic 18 nh ± 5%, 0402 monolithic Murata LQG15HS series L123 33 nh ± 5%, 0402 monolithic 27 nh ± 5%, 0402 monolithic 12 nh ± 5%, 0402 monolithic Murata LQG15HS series L124 12 nh ± 5%, 0402 monolithic L125 9.1 nh ± 5%, 0402 monolithic Murata LQG15HS series Murata LQG15HS series L131 33 nh ± 5%, 0402 monolithic 27 nh ± 5%, 0402 monolithic 12 nh ± 5%, 0402 monolithic Murata LQG15HS series L132 18 nh ± 5%, 0402 monolithic Murata LQG15HS series R171 56 kω ± 1%, 0402 Koa RK73 series XTAL 26.0 MHz surface mount crystal NDK, AT-41CD2 Table 15: Bill Of Materials for the Application Circuit The Gerber files for the CC1101EM reference designs ([5] and [6]) are available from the TI website. SWRS061B Page 20 of 93
8 Configuration Overview CC1101 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed: Power-down / power up mode Crystal oscillator power-up / power-down Receive / transmit mode RF channel selection Data rate Modulation format RX channel filter bandwidth RF output power Data buffering with separate 64-byte receive and transmit FIFOs Packet radio hardware support Forward Error Correction (FEC) with interleaving Data Whitening Wake-On-Radio (WOR) Details of each configuration register can be found in Section 33, starting on page 59. Figure 5 shows a simplified state diagram that explains the main CC1101 states, together with typical usage and current consumption. For detailed information on controlling the CC1101 state machine, and a complete state diagram, see Section 19, starting on page 41. SWRS061B Page 21 of 93
Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.7 ma. SIDLE SPWD or wake-on-radio (WOR) IDLE CSn = 0 SXOFF Used for calibrating frequency SCAL synthesizer upfront (entering CSn = 0 receive or transmit mode can Manual freq. then be done quicker). synth. calibration SRX or STX or SFSTXON or wake-on-radio (WOR) Transitional state. Typ. current consumption: 8.4 ma. Sleep Crystal oscillator off Lowest power mode. Most register values are retained. Current consumption typ 400 na, or typ 900 na when wake-on-radio (WOR) is enabled. All register values are retained. Typ. current consumption; 165 µa. Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.typ. current consumption: 8.4 ma. Frequency synthesizer on SFSTXON Frequency synthesizer startup, optional calibration, settling STX Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption: 8.4 ma. SRX or wake-on-radio (WOR) STX TXOFF_MODE = 01 SFSTXON or RXOFF_MODE = 01 Typ. current consumption: 13.1 ma at -6 dbm output, 16.8 ma at 0 dbm output, 32.8 ma at +10 dbm output. Transmit mode STX or RXOFF_MODE=10 SRX or TXOFF_MODE = 11 Receive mode Typ. current consumption: from 14.7 ma (strong input signal) to 15.7 ma (weak input signal). In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.7 ma. TXOFF_MODE = 00 RXOFF_MODE = 00 Optional transitional state. Typ. current consumption: 8.4 ma. TX FIFO underflow Optional freq. synth. calibration RX FIFO overflow In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption: 1.7 ma. SFTX SFRX IDLE Figure 5: Simplified State Diagram, with Typical Current Consumption at 1.2 kbaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized). Freq. Band = 868 MHz SWRS061B Page 22 of 93
9 Configuration Software CC1101 can be configured using the SmartRF Studio software [7]. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF Studio user interface for CC1101 is shown in Figure 6. After chip reset, all the registers have default values as shown in the tables in Section 33. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. Figure 6: SmartRF Studio [7] User Interface 10 4-wire Serial Configuration and Data Interface CC1101 is configured via a simple 4-wire SPIcompatible interface (SI, SO, SCLK and CSn) where CC1101 is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interface are done most significant bit first. All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), and a 6-bit address (A 5 A 0 ). The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16. When CSn is pulled low, the MCU must wait until CC1101 SO pin goes low before starting to SWRS061B Page 23 of 93
transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low. Figure 7: Configuration Registers Write and Read Operations Parameter Description Min Max Units f SCLK SCLK frequency 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). - 10 MHz SCLK frequency, single access No delay between address and data byte - 9 SCLK frequency, burst access No delay between address and data byte, or between data bytes - 6.5 t sp,pd CSn low to positive edge on SCLK, in power-down mode 150 - µs t sp CSn low to positive edge on SCLK, in active mode 20 - ns t ch Clock high 50 - ns t cl Clock low 50 - ns t rise Clock rise time - 5 ns t fall Clock fall time - 5 ns t sd Setup data (negative SCLK edge) to positive edge on SCLK (t sd applies between address and data bytes, and between data bytes) Single access Burst access 55 76 - - ns t hd Hold data after positive edge on SCLK 20 - ns t ns Negative edge on SCLK to CSn high. 20 - ns Table 16: SPI Interface Timing Requirements Note: The minimum t sp,pd figure in Table 16 can be used in cases where the user does not read the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC1101EM reference designs ([5] and [6]) using crystal AT-41CD2 from NDK. SWRS061B Page 24 of 93
10.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1101 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting. The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free. Table 17 gives a status byte summary. Bits Name Description 7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface. 6:4 STATE[2:0] Indicates the current main state machine mode Value State Description 000 IDLE IDLE state (Also reported for some transitional states instead of SETTLING or CALIBRATE) 001 RX Receive mode 010 TX Transmit mode 011 FSTXON Fast TX ready 100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling 110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX 111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX 3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 17: Status Byte Summary 10.2 Register Access The configuration registers on the CC1101 are located on SPI addresses from 0x00 to 0x2E. Table 35 on page 60 lists all configuration registers. It is highly recommended to use SmartRF Studio [7] to generate optimum register settings. The detailed description of each register is found in Section 33.1 and 33.2, starting on page 63. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A 5 A 0 ) set the start address in an internal address counter. This counter is SWRS061B Page 25 of 93
incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x30-0x3D, the burst bit is used to select between status registers, burst bit is one, and command strobes, burst bit is zero (see 10.4 below). Because of this, burst access is not available for status registers and they must be accesses one at a time. The status registers can only be read. 10.3 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1101 Errata Notes [1] for more details. 10.4 Command Strobes Command Strobes may be viewed as single byte instructions to CC1101. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 13 command strobes are listed in Table 34 on page 59. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and will determine how the FIFO_BYTES_AVAILABLE field in the status byte should be interpreted. When writing command strobes, the status byte is sent on the SO pin. A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRES strobe is being issued, one will have to waith for SO to go low again before the next header byte can be issued as shown in Figure 8. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high. Figure 8: SRES Command Strobe 10.5 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the R/W bit is one. The TX FIFO is write-only, while the RX FIFO is read-only. The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. The following header bytes access the FIFOs: 0x3F: Single byte access to TX FIFO 0x7F: Burst access to TX FIFO 0xBF: Single byte access to RX FIFO 0xFF: Burst access to RX FIFO When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 7. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEP state. SWRS061B Page 26 of 93