Implementation of a Block Interleaver Structure for use in Wireless Channels BARNALI DAS, MANASH P. SARMA and KANDARPA KUMAR SARMA Gauhati University, Deptt. of Electronics and Communication Engineering, Guwahati-781014, Assam, INDIA. barnalidasgimt@gmail.com, manashpelsc@gmail.com, kandarpaks@gmail.com NIKOS MASTORAKIS Technical University - Sofia Sofia 1000, Kl. Ohridski 8, Bulgaria mastor@tu-sofia.bg Abstract: Wireless communication is an indispensable part of todays technology, but the quality of service (QoS) degrades due to the stochastic behaviour of the wireless channels. Since reliabilty of data has always been a matter of concern, various techniques are developed to reduce the error prone nature of the wireless channels. Interleaving is one of the simplest and convenient techniques which is used efficiently in wireless applications. It has found its application for combating burst errors that creeps up in the channel during transmission. In this paper, an efficient model of a block interleaver using a hardware description language (Verilog) is proposed. The proposed technique reduces consumption of FPGA resources to a large extent, which implies low power consumption. Key Words: Block Interleaver, Verilog, FPGA. 1 Introduction In wireless communication, it is necessary that the communication systems must be robust in order to transmit the information from the source to the destination through a communication channel with high reliability. This in fact is a difficult task since in the physical world there exist many error causing factors. Detecting and correcting errors is very important while transmitting information. If errors occur and we cannot detect and correct them, the received information at the receiver will be of no use, as it will differ considerably from the original source information. These considerable imperfections in the information sequence, caused by the channel are required to be minimized. So, to mitigate this problem, interleavers are used which provides a reliable transmission of data. Interleaving is the process of rearranging the ordering of data sequence before transmission. An interleaver [1] is a device that performs interleaving. A deinterleaver is always associated with every interleaver, that restores the original input data sequence. Many papers in the literature have addressed the issue of designing interleaver in order to achieve low bit error rate. On the other hand, very few papers have addressed the efficient implementation issue of the interleavers. In this paper we have proposed an efficient technique to model and implement a block interleaver for use in wireless channels on field programmable gate array (FPGA) platform. We have modeled and implemented a block interleaver for different length of the input codeword i.e. 8-bit, 16-bit, 32-bit and 64-bit to the transmitter. Along with the transmitter, we have also constructed where we have used a de-interleaver to perform the reverse function of an interleaver. We determine the performance of the system using block interleaver by evaluating the percentage of error in the received bits, percentage of device utilization of the interleaver and power consumption by the interleaver for different codeword length. In Section II, we briefly explain the working of a block interleaver for the proposed work, and a brief overview of related works of implementations of interleavers. The description of the proposed model is included in Section III. Results are shown in Section IV. Conclusion and future work are included in Section V. 2 Background and Related Work 2.1 Block Interleaver Interleaving is a process which disperse the positions of the data bits before transmission, so that the cor- ISBN: 978-960-474-383-4 277
Figure 1: Block Interleaver rupted information can be recovered at the receiver by rearranging the data. Block interleaver is a popular interleaver employed in digital data transmission. It is simple and easy to implement whereas the other types of interleavers offer complexity in implementing. A block interleaver [9] is in the form of a row-column matrix of size R C; where R is total number of rows and C is the total number of columns. To perform interleaving, the information is written to the R C row-column matrix row wise and read back in column wise as shown in Figure 1. There are no inter-row or inter-column permutations used in this illustration, thus the interleaved sequence holds some systematic order. The block de-interleaver performs the inverse operation of the interleaver in which the information is written to the R C row-column matrix column wise and read back in row wise. 2.2 Related Works This section presents some previous works related to interleavers. In [2], the performance of turbo codes with matrix interleaving is studied. Investigations of various issues related to the code performance are done. These include the design of the relative dimensions of the matrix interleaver, the effect of the interleaver length, the interaction between the interleaver and the number of decoding iterations, and the effect of interchanging the interleaver. In [3], the performance of turbo codes with different types of interleaver have been studied. The effect of the interleaver length, the interaction between the interleaver and the number of decoding iterations,and the effect of interchanging the interleaver between input and output are the various issues that have been investigated related to the code performance. In [4], a comparison between two interleavers viz. random and master random interleaver has been presented based on the frequency of operation and hardware requirement. In [5], the authors presents an efficient technique to model convolutional interleaver using a hardware description Figure 2: Block diagram of the implementation model language is proposed and implemented on field programmable gate array (FPGA) chip. The proposed technique reduces consumption of FPGA resources to a large extent compared to conventional implementation technique using flip-flop. This implies lower power consumption and reduced delay in the interconnection network of the FPGA. In [6], the authors describes the performance analysis of a four arm interleaver design. The four arm interleaver generates each sequence of random pattern with four independently generated patterns, due to which the memory requirement decreases in comparison with power interleavers. The authors in [7] have designed an architecture with minimal hardware complexity and maximum reusable interleaver that can support two standards 3GPP WCDMA and 3GPP LTE. The proposed interleaver/ deinterleaver architecture receives an input data stream of any size established by the 3GPP standard and delivers the interleaved or deinterleaved stream depending on the user requirements. In [8], the authors have used Reed- Solomon Codes using interleaver for error correction and detection. They also developed a simulation program using MATLAB for Reed -Solomon Codes using interleaver and modulation schemes i.e. 16 PSK and QPSK using AWGN. 3 Proposed Approach The communication system model that has been designed to implement in the FPGA platform is given in Figure 2. The flow chart of the proposed interleaver is given in Figure 3. At the transmitter side, random data is taken as the source of information. A random data stream is generated with the help of T-flipflops. The random data that has been generated is then interleaved using block interleaving technique as described in the flow chart shown in Figure 3. A RAM has been created for the purpose of using as an interleaver. the rows and columns of the interleaver depends on the length of the input codeword. The interleaved sequence is ISBN: 978-960-474-383-4 278
Figure 4: Generation of an 8-bit codeword at the transmitter Figure 3: Flow Chart of the proposed block interleaver then modulated using BPSK modulation. The channel is modeled using the tap delay model of a finite impulse response (FIR) filter. At the receiver, the received data is now demodulated with BPSK demodulation technique. The demodulated data is then deinterleaved which follows the inverse operation of interleaver. Thus the original data can be recovered. 4 Results and Discussions In our experimentation, we have used Xilinx ISE Design Suite 13.2 to verify the system model. At the transmitter, we have generated 8-bit, 16-bit, 32-bit and 64-bit codeword separately, which would be fed to the input of the interleaver. The interleaver memory size is accordingly generated for different size of the codeword. Each code symbols of the codeword is applied to the respective rows of the interleaver. The codeword gets scrambled as it progresses through the interleaver. The scrambled codeword is then applied to the input of a BPSK modulator for modulation. Thus, we get a modulated codeword which is ready for transmission. At the receiver, the data from the transmitter output is now fed to the input of the BPSK demodulator. The codeword from the output of the demodulator is applied as input to the deinterleaver. It is observed that the scrambled codeword is converted into its original form at the output of the deinterleaver in which some bits are corrupted. For an 8-bit input codeword 11010010 transmitted, we receive the codeword 11000010 at the receiver i.e. 1- bit of the data gets corrupted. Timing diagram for an 8-bit codeword transmitter and receiver is shown in Figure 5: Receiver output of an 8-bit codeword Table 1: Performance comparison for different length of input codeword Codeword length No. of errors(in bits) % of error (per frame) 8-bit 1 12.5% 16-bit 2 12.5% 32-bit 3 9.375% 64-bit 5 7.81% Figure 4 and 5. For a 16-bit input codeword 0101100101010101 transmitted, we receive the codeword 0101100001010111 at the receiver i.e. 2-bits of the data get corrupted. For a 32-bit input codeword 11001010101001001101001010101010 transmitted, we receive the codeword 11001010111001001001001010001010 at the receiver i.e. 3-bits of the data get corrupted. For a 64-bit input codeword 1110001110001110001110001110001110001110001 110001110001110001110 transmitted, we receive the codeword 111000111010111000111000011000101000111100111 0001110001100001110 at the receiver i.e. 5-bits of the data get corrupted. The percentage of error for the different length of input codeword is tabulated in Table 1. From Table 1, it is noticed that the percentage of ISBN: 978-960-474-383-4 279
Table 5: Device utilization summary of the interleaver for 64-bit codeword Number of Slices: 74 768 9% Number of Slice Flip Flops: 128 1536 8% Number of bonded IOBs: 63 63 100% Table 6: Memory usage of the interleaver for different length of input codeword 8-bit 16-bit 32-bit 64-bit Memory usage(kilobytes) 239892 239956 240020 241108 Figure 6: RTL schematic of a Block Interleaver 4 Table 2: Device utilization summary of the interleaver for 8-bit codeword Number of Slices: 9 768 1% Number of Slice Flip Flops: 16 1536 1% Number of bonded IOBs: 18 63 28% Table 3: Device utilization summary of the interleaver for 16-bit codeword Number of Slices: 18 768 2% Number of Slice Flip Flops: 32 1536 2% Number of bonded IOBs: 34 63 53% Table 4: Device utilization summary of the interleaver for 32-bit codeword Number of Slices: 37 768 4% Number of Slice Flip Flops: 64 1536 4% Number of bonded IOBs: 56 63 78% Table 7: On- Chip Power Summary of the interleaver On- chip 8-bit(W) 16-bit(W) 32-bit(W) 64-bit(W) Clock 0.004 0.006 0.007 0.010 Logic: 0.000 0.000 0.000 0.001 BRAM 0.005 0.091 0.181 0.272 PLL 0.114 0.114 0.114 0.114 Other 0.332 0.332 0.332 0.332 IO 0.766 0.766 0.766 0.766 Device Statistics 0.185 0.186 0.187 0.188 Table 8: Power consumption of the interleaver Length of input Power(W) 8-bit 1.406 16-bit 1.495 32-bit 1.588 64-bit 1.683 length of the input codeword increases. Therefore, the memory usage of the device also increases. But the utilization of the device is less than other conventional methods. The memory utilization of the interleaver for the various input codeword length are tabulated in Table 6. The power estimation for different input codeword length which is measured using Xilinx Power Estimator (XPE) 13.2 is shown in Table 7 and 8. From the power consumption table of the interleaver, it is clear that interleaving with higher length of codeword consumes more power, but the power consumption is lower than other conventional methods. %subsectionsubsection error decreases as we increase the length of the input codeword. The RTL schematic of the interleaver design is shown in Figure 6, which consists of D-flipflops. Table 2, 3, 4 and 5 gives the device utilization summary of the interleaver for different length of input codeword. From the device utilization summary, we see that the number of slice and flip flop usage increases as the 5 Conclusion In this paper an efficient implementation of a block interleaver on FPGA platform has been proposed. The main objective was to build an interleaver design with minimum possible resources and verify the transmission and reception process of the given system model. The proposed model is verified by implementing every module separately. Simulation result in the form ISBN: 978-960-474-383-4 280
of timing diagram using Xilinx ISE Design Suite 13.2 is presented which endorses the successful operation of the model. This technique reduces FPGA resource utilization and power consumption compared to other implementation technique. Techniques can be devised to address the issue of time consumption to make the system more efficient for real time high data rate situations. [9] R. Asghar, Flexible Interleaving Sub-systems for FEC in Baseband Processors, Department of Electrical Engineering, Linkoping University, Sweden, 2010. Acknowledgements: This work was supported by Manash Pratim Sarma and Dr. Kandarpa Kumar Sarma, Department of ECE, Gauhati University and would like to avail this opportunity to extend my hearty thanks to them for their continuous support and wholehearted collaboration in this project. References: [1] K. Andrews, C. Heegard and D. Kozen, A Theory of Interleavers, School of Electrical Engineering, Department of Computer Science, Cornell University, Ithaca, New York. [2] M. A. Kousa, Performance of turbo codes with matrix interleavers, The Arabian Journal for Science and Engineering, vol. 28, no. 2B, pp. 211-220, October 2003. [3] Y. J. Harbi, Effect of the Interleaver types on the Performance of the Parallel Concatenation Convolutional Codes, International Journal of Electrical and Computer Sciences IJECS- IJENS, vol. 12, no. 03, pp. 25-31, June 2012. [4] A. Rai, N. Yadav., P. Chauhan, Performance Comparison of Interleavers, International Journal of Electronics Engineering, pp.277-278, 2010. [5] B. K. Upadhyaya and S. K. Sanyal, VHDL Modeling of Convolutional Interleaver- Deinterleaver for Efficient FPGA Implementation, International Journal of Scientific Research, vol. 2, no. 6, pp. 66-68, November, 2009. [6] Md. E. Lodhi and S. Kumari, Four Arm Interleaver: Performance analysis, International Journal of Scientific Research, vol. 2, Issue 8, pp. 140-142, August, 2013. [7] S. Badrinarayanan, J.M. Mathana, R.R. Hemamalini, VLSI Architecture of Dual Standard Interleaver for Turbo Codes, Journal of Theoretical and Applied Information Technology, pp. 408-416, vol. 60, no. 2, February, 2014. [8] G. K. Sodhi, G. Saini and K. Sharma, Performance Evaluation of Interleaver in RS Codes using 16 PSK and QPSK, Journal of Information Systems and Communication, vol. 3, Issue 1, pp. 38-40, February, 2012. ISBN: 978-960-474-383-4 281