Spread-Spectrum Clocking in Switching Regulators to Reduce EMI

Spread-Spectrum Clocking in Switching Regulators to Reduce EMI H. Sadamura, T. Daimon, T. Shindo, H. Kobayashi, M. Kono EE Dept. Gunma University, Japan T. Myono, T. Suzuki, S. Kawai, T. Iijima Sanyo Electric Co. Ltd., Japan

Contents Research Background and Goal Principle of DC-DC Converters Proposal of Noise Power Spectrum Spread Method in DC-DC Converters Implementation and Measurement Results Summary

Contents Research Background and Goal Principle of DC-DC Converters Proposal of Noise Power Spectrum Spread Method in DC-DC Converters Implementation and Measurement Results Summary

Research Background Mobile equipment prevails everywhere Mobile phone, Digital still camera, PDA Small size, High efficiency Multiple supply voltages Low-voltage supply

Features of Switching Regulator Merit High efficiency Continuously varying output voltage Large output current Demerit Coil is required. bulky and costly Switching noise

Research Goal We focus on a big problem of switching regulator: Switching and harmonic noises Proposal of EMI reduction technique by spreading noise power spectrum

Contents Research Background and Goal Principle of DC-DC Converters Proposal of Noise Power Spectrum Spread Method in DC-DC Converters Implementation and Measurement Results Summary

Vdd Principle of DC-DC Converter(1) L Vout In case Clk=ON IL Clk D C In case Clk=OFF T; clock period Output voltage Vout is determined by the clock duty.

Principle of DC-DC Converter(2) Vdd: Input voltage CLK: Switching clock L, C: Low pass filter for smoothing Vout : Output voltage LPF CLK DUTY=25% OUT 2.5V 10V DUTY=50% 5V 7.5V DUTY=75%

DC-DC Converter with PWM Controller PWM Circuit rf Vcc 3.3[V] R2 r0 Comparator Vout R1 vb Error Amplifier OSC Output voltage setting FeedBack Comparator output Error amplifier output Triangular wave

Features of PWM Control Advantage ON/OFF switching High efficiecy ON OFF Negative feedback control Output is stable regardless of output load. + Output voltage setting Disadvantage - PWM Switching Regulator Output voltage Output Load Synchronization with clock Harmonic noises in specific frequencies

EMI and Switching Regulator Shield Costly, Large in size Shield is required to meet EMI Regulations Proposal of EMI reduction circuit

Contents Research Background and Goal Principle of DC-DC Converters Proposal of Noise Power Spectrum Spread Method in DC-DC Converters Implementation and Measurement Results Summary

Proposed Method Conventional DC-DC Converter + Extra Digital Control Circuit Generated switching noise power spectrum are in specific frequencies. EMI regulation limits (Conventional) (Proposed) By spreading the spectrum of switching noise power, EMI reduction is realized.

Principle of Pseudo-Random Digital Modulation (PRM) Driving Clock Regulator Output Normal Clock PRM Clock Effect of Phase Modulation V = L di dt Switching Control with Pulse Switching Noise Large Switching Noises Large Harmonic Noises Pseudo-Random Spread Spectrum of Noise Power

PRM Circuit Implementation - 3bit LFSR case - Reset D Q D Q D Q LFSR Input SEL1 SEL2 SEL3 MUX in1 in2 in6 in7 Output D Q D Q D Q Clock Shift Register

PRM Timing Chart 3bit LFSR case SEL 2 SEL 1 SEL 0 SEL PRM input in7 in6 in5 in4 in3 in2 in1 PRM output 4 1 2 5 3 7 6 50 100 150 200 250 300 350 Time [ μs ] 4

DC-DC Converter with PRM Reset PRM input Clock Proposed PRM Circuit PRM Output Power Circuit DC-DC Converter DC-DC Converter Output PWM output PWM Controller Control Circuit Conventional Circuit VOUT (No need for modification)

Optimal Clock Phase Shift(1) Normal clock ( Conventional ) When clock phase shift is too large, output ripple becomes too large PRM clock ( proposed ) When clock phase shift is too small, noise spectrum are not spread sufficiently. Optimal phase shift is obtained by measurement.

Optimal Clock Phase Shift(2) Optimal value of maximum phase shift (Tshift) Tshift= Tpwm 2 Tpwm=PWM clock period Tshift Tshift 0 -T pwm /2 T pwm /2 Tpwm

Contents Research Background and Goal Principle of DC-DC Converters Proposal of Noise Power Spectrum Spread Method in DC-DC Converters Implementation and Measurement Results Summary

FPGA Design Evaluation Board Design Item Technology:FLEX10K30EQC208 3 (Altera) Item Spectrum Spread Method Shift Register Clock PWM Input PN code Control Clock Supply Voltage PN-code Code Length The Number of DFFs Spec. Direct 6MHz 187kHz 187kHz 3.3V M- Sequence 31 37

Measurement Setup Flex Board (Proposed) D Q D Q D Q D Q D Q GPIB fdata Vdd Reset sel 0 sel 1 sel 2 sel 3 sel 4 Mux in1 in2 in3 in31 Spectrum Analyzer (HP ESA-1500A) μpc1933(pwm) Driver Circuit PWMOUT D Q D Q D Q fclk Shift Resister D Q Vdd PWM - IN Buck Converter PWM (Control circuit)

Measured Power Spectrum of Driving Clock Power [dbm] Power [dbm] 20 0-20 -40-60 -80 16.2dBm 6.9dBm 20 3.5dBm 2.6dBm -1.5dBm -1.0dBm 0-20 -40-60 -80-100 0 200k 400k 600k 800k 1M 1.2M Frequency [Hz] -100 0 200k 400k 600k 800k 1M 1.2M Frequency [Hz] Power spectrum of normal clock (Conventional) Maximum peak reduction by 12.7dBm Power spectrum of PRM output clock with 5bit M-sequencer (Proposed)

Measured Output Voltage Waveform of DC-DC Converter Amplitude [V] Input voltage Vdd=3.3V, Clock duty = 50% Amplitude [V] 1.7 1.7 1.6 1.6 0 20 40 60 80 100 Time [us] Output waveform with normal clock (Conventional) 0 20 40 60 80 100 Time [us] Output waveform with PRM clock. (Proposed)

Power [dbm] 20 0-20 -34.9dBm -27.3dBm Measured Output Power Spectrum of DC-DC Converter -35.5dBm Power [dbm] 20 0-20 -39.6dBm -42.9dBm -48.3dBm -40-60 -80-40 -60-80 -100-100 0 200k 400k 600k 800k 1M 1.2M 0 200k 400k 600k 800k 1M 1.2M Frequency [Hz] Output power spectrum with normal clock (Conventional) Frequency [Hz] Output power spectrum with PRM clock (Proposed) Maximum peak reduction by 12.3dBm

Clock Duty vs. Output Voltage 3.0 2.5 Vout [V] 2.0 1.5 1.0 0.5 Ideal Proposed Conventional 0 10 20 30 40 50 60 70 80 90 Duty [%] Match to the theoretical output voltage. The proposed method does not affect the (average) output voltage.

Efficiency vs. Output Current 94 93 92 Conventional Proposed Effiency [%] 91 90 89 88 87 86 4 6 8 10 12 14 16 18 20 Iout [ma] The proposed method does not affect efficiency.

Peak Noise Power Spectrum vs. the Number of M-Sequencer Bits Muximum Noise Power [dbm] 12 11 10 9 8 7 6 5 4 3 3 4 5 6 7 LFSR Bit numbver Peak Noise Power Spectrum of Driving Clock Muximum Noise Power [dbm] -29.5-30.0-30.5-31.0-31.5-32.0-32.5-33.0 3 4 5 6 7 LFSR Bit numbver Peak Noise Power Spectrum of Switching Regulator Output 5-bit and 6-bit are reasonable trade-off.

Summary Proposal of Noise Power Spectrum Spread Technique Addition of simple digital circuitry can realize EMI reduction. - Low cost, Low power - Robust against temperature variation, aging No need for modification of the other parts. Applicable also for voltage-boosting converter. Implementation with FPGA Confirmation of its effectiveness by measurements Max. Peak Fundamental 2nd-harmonics 3rd-harmonics Reduction by 12.3dBm 5.7dBm 15.6dBm 12.8dBm