Low Voltage, Dual SPDT Analog Switch with Charge Pump

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Transcription:

Low Voltage, Dual SPDT Analog Switch with Charge Pump DG, DG, DG DESCRIPTION The DG, DG, DG are monolithic CMOS analog switching products designed for high performance switching of analog signals. Combining low power, high speed, low on-resistance and small physical size, the DG, DG, DG are ideal for portable and battery powered applications. The DG, DG, DG have built-in charge-pump circuitry which lowers the minimum supply voltage to +. V while maintaining low on-resistance. The Control circuitry allows the DG, DG, DG to operate in different configurations. Built on 's low voltage process, the DG, DG, DG has an epitaxial layer that prevents latch-up. Break-before-make is guaranteed. The DG, DG, DG are manufactured in space saving DFN- (. x. mm). And as a committed partner to the community and the environment, manufactures this product with lead (Pb)-free device terminations and is % RoHS compliant. FEATURES Low voltage operation (. V to. V) Low on-resistance - R ON :. Ω typ. at. V Fast switching: t ON = 9 ns t OFF = ns DFN- package BENEFITS Reduced power consumption High accuracy Reduce board space TTL/. V logic compatible High bandwidth APPLICATIONS Cellular phones Audio and video signal routing PCMCIA cards Battery operated systems RoHS PLIANT FUNCTIONAL BLOCK DIAGRAM AND P CONFIGURATION TRUTH TABLE DG Logic NC, NO, ON OFF OFF ON TRUTH TABLE DG SHDN/EN Logic Logic NC, NO, Charge Pump ON OFF ON OFF ON ON x OFF OFF OFF TRUTH TABLE DG SHDN/EN Logic Logic NC, NO, Charge Pump ON OFF ON OFF ON ON ON OFF OFF OFF ON OFF ORDERG FORMATION Temp. Range Package Part Number - C to C DFN- DGDN-T-E DGDN-T-E DGDN-T-E S-9-Rev. B, -Sep-

DG, DG, DG DG 9 NC NC NO NO Top View DG/DG SHDN/EN 9 NC NC NO NO Top View ABSOLUTE MAXIMUM RATGS T A = C, unless otherwise noted Parameter Limit Unit Reference to -. to.,, NC, NO a -. to ( +.) V Current (Any terminal except NO, NC or ) Continuous Current (NO, NC, or ) ± ma Peak Current (Pulsed at ms, % Duty Cycle) ± Storage Temperature (D-Suffix) - to Package Solder Reflow Conditions d C Power Dissipation (Packages) b DFN- c 9 mw Notes: a. Signals on NC, NO, or or exceeding will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate.9 mw/ C above C d. Manual soldering with iron is not recommended for leadless components. The DFN- is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. S-9-Rev. B, -Sep-

DG, DG, DG SPECIFICATIONS = V Parameter Analog Switch Symbol Test Conditions Otherwise Unless Specified = V, ± %, V =. or. V e Temp. a Limits - C to C Min. b Typ. c Max. b V NO, V NC, Analog Signal Range d V V =. V, V =. V, I NO, I NC = ma... =. V, V =. V, I NO, I NC = ma. On-Resistance R ON =. V, V =. V, I NO, I NC = ma... =. V, V =. V, I NO, I NC = ma... Ω R ON Flatness d R ON =. V, V =. V,. V,.. Flatness I NO, I NC = ma R ON Match d ΔR ON. On Resistance (Shutdown) R SHDN =. V, V =. V, I NO, I NC = ma I NO(off), - I Switch Off Leakage Current NC(off) =. V, V NO, V NC =. V/. V, - V =. V/. V - I (off) na - Channel-On Leakage - I (on) =. V, V NO, V NC = V =. V/. V Current - Digital Control =. V. Input High Voltage V H =. V to. V. =. V. Input Low Voltage V L =. V to. V. V Input Capacitance C in. pf Input Current I L or I H V = or - µa Dynamic Characteristics 9 9 Turn-On Time t ON =. or. V, V NO or V NC =. V, 9 9 ns Turn-Off Time t OFF R L = Ω, C L = pf Break-Before-Make Time t d Charge Injection d Q J C L = nf, V GEN = V, R GEN = Ω pc R L = Ω, C L = pf, f = MHz - Off-Isolation d OIRR R L = Ω, C L = pf, f = MHz - R L = Ω, C L = pf, f = MHz - db Crosstalk d, f X TALK R L = Ω, C L = pf, f = MHz - N O, N C Off Capacitance d C NO(off) 9 C NC(off) f = MHz pf C NO(on) Channel-On Capacitance d C NC(on) 9 Unit S-9-Rev. B, -Sep-

DG, DG, DG SPECIFICATIONS = V Test Conditions Otherwise Unless Specified Limits - C to C Parameter Symbol = V, ± %, V =. or. V e Temp. a Min. b Typ. c Max. b Unit Power Supply Power Supply Range.. V Power Supply Current I+ =. V, V = or, SHDN/EN = V =. V, V = or, SHDN/EN =. µa Notes: a. = C, = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, not subjected to production test. e. V = input voltage to perform proper function. f. Crosstalk measured between channels. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S-9-Rev. B, -Sep-

t t I l i t TYPICAL CHARACTERISTICS T A = C, unless otherwise noted DG, DG, DG On-Resistance (Ω) - R O N 9 =. V =. V =. V =. V =. V =. V =. V =. V T = C I NO/NC = ma e (Ω) c n a s s e R - n R O N - O 9 =. V, Is = ma + C + C - C....... V - Analog Voltage (V) R ON vs. V and Supply Voltage V - Analog Voltage (V) R ON vs. Analog Voltage and Temperature On-Resistance (Ω) 9 =. V, Is = ma + C + C - C y C u r r e n t ( µa ) u p p =. V - R O N + - S......... V - Analog Voltage (V) R ON vs. Analog Voltage and Temperature - - - Temperature ( C) Supply Current vs. Temperature =.V =. V ( p A ) L e a k a g e C u r r e n I I NO(off) (off) I (on) ( p A ) L e a k a g e C u r r e n - - I NO(off) /I NC(off) I (off) I (on) - - - - - Temperature ( C) Leakage Current vs. Temperature -....... V - Analog Voltage (V) Leakage vs. Analog Voltage S-9-Rev. B, -Sep-

j t i DG, DG, DG TYPICAL CHARACTERISTICS T A = C, unless otherwise noted t ON, t OFF - Switching Time (ns) t ON =. V t ON =. V t OFF =. V t OFF =. V LOSS, OIRR, X TALK (db) - - - - - - - - - 9 Loss OIRR XTalk =. V R L = Ω - - - Temperature ( C) Switching Time vs. Temperature - k M M M G Frequency (Hz) Insertion Loss, Off-Isolation Crosstalk vs. Frequency. - Switching Th reshold (V ) V T... o n ( p C ) e c Q - C h a r g e I n =. V =. V =. V -. - Supply Voltage (V) Switching Threshold vs. Supply Voltage -......... V - Analog Voltage (V) Charge Injection vs. Analog Voltage S-9-Rev. B, -Sep-

DG, DG, DG TEST CIRCUITS Switch Input Logic Input NO or NC Switch Output R L Ω V OUT C L pf Logic Input Switch Output V H V L V % t r t f < ns < ns.9 x V OUT V t ON t OFF C L (includes fixture and stray capacitance) ( ) R V OUT = V L R + L R ON Logic "" = Switch On Logic input waveforms inverted for switches that have the opposite logic sense. Figure. Switching Time Logic Input V H t r < ns t f < ns V NO NO V O V L V NC NC R L Ω C L pf V NC = V NO V O 9 % Switch Output V t D t D C L (includes fixture and stray capacitance) Figure. Break-Before-Make Interval V gen + R gen V = - NC or NO V OUT C L = nf V OUT On ΔV OUT Off On Q = ΔV OUT x C L depends on switch configuration: input polarity determined by sense of switch. Figure. Charge Injection S-9-Rev. B, -Sep-

DG, DG, DG TEST CIRCUITS nf nf NC or NO V,. V R L V,. V NC or NO Meter HP9A Impedance Analyzer or Equivalent Analyzer Off Isolation V = log V NO /NC f = MHz Figure. Off-Isolation Figure. Channel Off/On Capacitance maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http:///ppg?. S-9-Rev. B, -Sep-

Package Information DFN- LEAD ( X ) e D Terminal Tip NXb D/. M C A B Index Area D/ E/ E/ NXL E Exposed Pad. C x ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ E D BOTTOM VIEW Index Area D/ E/. C x TOP VIEW //. C NX. C A A A SEATG PLANE SIDE VIEW NOTES:. All dimensions are in millimeters and inches.. N is the total number of terminals.. Dimension b applies to metallized terminal and is measured between. and. mm from terminal tip.. Coplanarity applies to the exposed heat sink slug as well as the terminal.. The pin # identifier may be either a mold or marked feature, it must be located within the zone iindicated. MILLIMETERS CHES Dim Min Nom Max Min Nom Max A..9....9 A...... A. BSC. BSC b.....9. D. BSC. BSC D.....9.9 E. BSC. BSC E.9...9..9 e. BSC. BSC L...... *Use millimeters as the primary measurement. ECN: S- Rev. A, 9-Nov- DWG: 9 Document Number: 9-Nov-

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