Flying-Adder Frequency and Phase Synthesis Architecture Liming XIU Texas Instruments Inc, HPA/DAV 01/30/2005 February 15, 2005 Slide 1
What is it? An novel frequency synthesis architecture that takes a digital value and generates a signal of requested frequency (and phase)...0100101... f (Hz) Continued February 15, 2005 Slide 2
Background Material This presentation is based on five papers: IEEE Journal of Solid-State Circuit, 06/2000, An Architecture of High Performance Frequency and Phase Synthesis. IEEE Trans. on VLSI, 10/2002, A Flying-Adder Architecture of Frequency and Phase Synthesis with Scalability. IEEE Trans. on Circuit & System II, 03/2003, A New Frequency Synthesis Method based on Flying-Adder Architecture. IEEE Journal of Solid-State Circuit, 03/2004, A Novel All Digital Phase Lock Loop with Software Adaptive Filter. IEEE Trans. on VLSI, 02/2005, A Flying-Adder Frequency Synthesis Architecture of Reducing VCO Stages. February 15, 2005 Slide 3
History Started in late 1998, MSP/Video Group. Being continuously refined/improved. Thanks to Hugh Mair February 15, 2005 Slide 4
Presentation Outline The principal Idea Implementation: First Generation Implementation: Second Generation Integer-Flying-Adder Architecture February 15, 2005 Slide 5
Principal Idea Using multiple equally-spaced phases generated from a VCO to synthesis various frequency and phase, by triggering the flip-flops at predestined time. Reference PFD CHARGE PUMP Filter VCO N DIVIDER Frequency and Phase FREQUENCY AND PHASE Z Control Word SYNTHESIZER Z_SHIFT Continued February 15, 2005 Slide 6
Principal Idea, continued VCO Output waveforms, for N=32 VCOOUT[0] VCOOUT[1] VCOOUT[2] VCOOUT[3] VCOOUT[30] VCOOUT[31] Continued February 15, 2005 Slide 7
Principal Idea, continued Triggering the flip-flop at predestined time to generate the desired frequency, by utilizing the multiple VCO outputs. VCOOUT <31:0> 32 to 1 MUX 123 D Q' Q Z @ f Hz 1 2 3 10-bit Reg 10-bit Adder FREQ<9:0> Continued February 15, 2005 Slide 8
Numerical Example VCO running at 156.25 MHz (6.4 ns) => = 6.4/32 = 0.2 (ns) Wanted: 204.08 MHz, or T = 4.9 ns => FREQ[9:0] = T/(2 ) = 4.9/0.4 = 12.25 = 01100.01000b Integer portion is used for selecting tick, fractional portion is for error accumulation. Continued February 15, 2005 Slide 9
Numerical Example, continued 0 00000 12 01100 24 11000 4 00100 17 10001 29 11101 12 12 12 13 12 00000.00000 + 01100.01000 01100.01000 + 01100.01000 11000.10000 + 01100.01000 00100.11000 + 01100.01000 10001.00000 + 01100.01000 01100.01000 11000.10000 00100.11000 10001.00000 11101.01000 February 15, 2005 Slide 10
Key Facts VCO has to be in multiple-delay-stages style, single-ended or differential. The PLL/VCO is running at a fixed frequency, no loop dynamic responds requirement. Output frequency range, theoretically: (1/2)fvco <= fout <= (N/2)fvco In practice, the high-frequency is limited by the speed of the process in which this architecture is implemented. Has inherent jitter if fractional bits are used. Frequency resolution (step): δf = 2 k * * f 2 February 15, 2005 Slide 11
February 15, 2005 Slide 12 Inherent Jitter r M T FREQ or FREQ T + = = = /, * + = = 1)* ( * M T M T l s r P P r P l s l = = = 1 1 = = s l pk pk T T J 0 ) ( ) ( = + = T T P T T P J s s l l mean 2 2 2 ) ( ) ( r r T T P T T P J s s l l rms = + =
Output frequency vs. FREQ (an example) February 15, 2005 Slide 13
Frequency divider and Phase divider To generate frequencies, divider can be used. But divider ratio has to be integer available frequencies are limited. Flying-Adder architecture can be viewed as phase divider which provides additional level of frequency divide more available frequencies. February 15, 2005 Slide 14
Presentation Outline The principal Idea Implementation: First Generation Implementation: Second Generation Integer-Flying-Adder Architecture February 15, 2005 Slide 15
Implementation: Problems Two problems: The glitch of the MUX VCOOUT <31:0> 32 to 1 MUX 123 D Q' Q Z 1 2 3 The speed of the adder 10-bit Reg 10-bit Adder FREQ<9:0> February 15, 2005 Slide 16
The Glitch of the MUX IN0 IN1 IN2 Z IN31 Sel[4:0] IN0, 00000 IN21, 10101 IN31, 11111 Z Z February 15, 2005 Slide 17 t
Implementation: Two Paths FREQ_B<4:0> 5-bit Adder PATH_B 5-bit Reg CLK1 VCOOUT <31:0> D Q Q' Z D Q' Q 10-bit Reg CLK2 FREQ_A<9:0> 10-bit Adder PATH_A Continued February 15, 2005 Slide 18
Implementation: Two Paths Solved the glitch problem: the two paths are interlocked CLK1 CLK2 Path_A blocked MUX_A decoding Path_A open MUX_A stable Path_B open MUX_B stable Path_B blocked MUX_B decoding Continued February 15, 2005 Slide 19
Implementation: Two Paths Relaxed the constrain on adders => double the circuit speed One path generates the rising edge, the other for falling edge Accumulator in Path B Path B Path B Path A Path A Accumulator in Path A Continued February 15, 2005 Slide 20
Implementation: Two Paths This two paths architecture solved the previous two problems, but created a new problem: the synchronization of the two paths. In other words, MUX_A and MUX_B s address values are unrelated => duty cycle is uncontrollable. Path B Location unknown Depend on initial value Path A Path A February 15, 2005 Slide 21
Implementation: Synchronized FREQ_B<4:0> 5-bit Adder PATH_B 5-bit Reg CLK1 VCOOUT <31:0> D Q Q' Z D Q' Q 10-bit Reg CLK2 FREQ_A<9:0> 10-bit Adder PATH_A Continued February 15, 2005 Slide 22
Implementation: Synchronized Now MUX_B s address is related to MUX_A s New problem: Adder in PATH_B doesn t have full cycle to work Path B Adder in Path B Path B Path A Accumulator in Path A Path A February 15, 2005 Slide 23
Implementation: Pipelined FREQ<10:6> 5-bit Adder PATH_B 5-bit Reg 5-bit Reg CLK1 D Q VCOOUT <31:0> Q' Z t2 t3 t4 D Q' t5 Q t6 5-bit Reg t1 CLK2 10-bit Reg 10-bit Adder PATH_A Continued FREQ<9:0> February 15, 2005 Slide 24
Implementation: Pipelined Now both the accumulator in PATH_A and the adder in PATH_B have full cycle to work. Timing constrain: see below a t1+ t2+ t3 t ab t4+ t5+ t6 t bc b c February 15, 2005 Slide 25
Implementation: First Generation First generation development history: One Path Two Paths Synchronized Pipelined Key features of this architecture: interlocking between paths self-clocking pipeline February 15, 2005 Slide 26
Summary: The Advantages The output frequency can be changed instantly without any dynamic process. With enough fraction bits, any frequency within certain range can be generated with any accuracy. Phase shift version of the output signal can be generated. Output signal with various duty cycle can be generated. Since VCO running at fixed frequency, VCO and PLL design are much simplified, the PLL is much robust against temperature draft, process and voltage variation. The increment value can be modulated to produce a highly accurate and predictable spread spectrum clock source. February 15, 2005 Slide 27
Phase Synthesis: The idea 32 to 1 MUX D Q' Q Z VCOOUT <31:0> 10-bit Reg FREQ<9:0> 10-bit Adder FREQ_GEN 32 to 1 MUX D Q' Q Z_SHIFT 5-bit Reg PHASE<4:0> 5-bit Adder PHASE_GEN Continued February 15, 2005 Slide 28
Phase Synthesis: The idea The MUX address used in PHASE_GEN is the sum of the MUX_A s address and PHASE[4:0] The data used in DFF of PHASE_GEN is the same as data used in FREQ_GEN The Z_SHIFT is a delay version of Z. The delay amount: PHASE[4:0] * Z ϕ = PHASE[4:0] * Z_SHIFT February 15, 2005 Slide 29
<4:0> Phase Synthesis: Implementation 32-bit Adder PATH_B_SHIFT <5:0> >=31? '1' '0' 5-bit Adder 5-bit Reg 5-bit Reg DFTOUT_UP 5-bit Reg D Q VCOOUT <30:0> Q' Z_SHIFT Q' February 15, 2005 Slide 30 PHASE<4:0> LOW_TO_UP<4:0> FREQ<32:27> <5:0> >=31? 5-bit Reg 5-bit Reg 5-bit Adder '0' '1' 32-bit Adder <4:0> D DFTOUT_LOW Q PATH_A_SHIFT <5:0> >=31? 5-bit Adder 32-bit Adder '0' '1' <4:0>
Phase Synthesis: Problems Problems: Dead-zone Dual-stability February 15, 2005 Slide 31
Presentation Outline The principal Idea Implementation: First Generation Implementation: Second Generation Integer-Flying-Adder Architecture February 15, 2005 Slide 32
Second Generation Architecture The new architecture: the operating speed is greatly improved. has scalability for higher output frequency. has an internal node whose frequency is higher than that of the synthesized output. eliminates the dead-zone and dual-stability for phase synthesis. Continued February 15, 2005 Slide 33
Second Generation Architecture FREQ<10:6> 5-bit Adder PATH_B FREQ<32:28> EN + 5 5-bit Reg 5 Bits CLK2 5-bit Reg CLK1 5 Bits CLK1 D SET Q VCOOUT <31:0> CLR Q Z VCOOUT<31:0> 0 TRIGGER D CLK Q CLK1 CLK2 t3 t2 t4 SET D CLR Q t5 Q t6 1 CLK1 5-bit Reg t1 CLK2 5 Bits CLK2 10-bit Reg 32 Bits CLK2 10-bit Adder PATH_A FREQ<9:0> FREQ<31:0> February 15, 2005 Slide 34 EN + 32 Continued
Sec. Gen. Arch.: Scalability CLK 1 CLK CLK CNTL 2CLK D Q 3CLK 4 TRIGGER CLK Z SEL5 MUX 5 SEL1 MUX 1 MUX MUX SEL2 2 SEL3 3 SEL4 MUX 4 Tick[31:0] REG 1 + ADDER 1 CLK 1 CLK 1 REG 2 FREQ[31:0 ] FREQ[33:29] CLK 2 CLK 1 1 + ADDER + ADDER + 2 FREQ [32:28]+ FREQ[27] February 15, 2005 Slide 35 REG 3 3 CLK 3 CLK REG 4 FREQ[32:28]+ FREQ[33:29] CLK 4 CLK 1 ADDER 4 Continued
Sec. Gen. Arch.: Scalability Multiple paths (more than two) to relax the constrains on adders further -> higher output frequency Continued February 15, 2005 Slide 36
Sec. Gen. Arch.: Scalability The clocks signals and the mechanism of interlocking TRIGGER 1 2 3 4 5 6 7 8 9 10 11 12 Z and SEL5[1:0] 01 MUX2 11 MUX3 10 MUX4 00 MUX1 01 MUX2 11 MUX3 10 MUX4 00 MUX1 01 MUX2 11 MUX3 CLK1 CLK2 CLK3 CLK4 February 15, 2005 Slide 37
Sec. Gen. Arch.: Phase Synthesis FREQ<32:28> + 5 FREQ<32:28> + 5 5 Bits INIT1 CLK2 5 Bits INIT2 CLK2 EN1 1 0 EN2 1 0 5 Bits CLK1 EN CLK2 D CLK Q EN1 5 Bits CLK1 EN1 CLK2 D CLK Q EN2 VCOOUT<31:0> 0 1 TRIGGER D CLK Q CLK1(Z) CLK2 VCOOUT<31:0> 0 1 1 CLK1 0 TRIGGER EN2 D CLK Q CLK1 (Z_SHIFT) CLK2 CLK1 CLK1 5 Bits CLK2 5 Bits CLK2 EN1 0 1 EN2 0 1 INIT1 32 Bits CLK2 INIT2 32 Bits CLK2 + 32 FREQ<31:0 FREQ<31:0> February 15, 2005 > Slide 38 + Fig. 16. The circuitry for Z. Fig. 17. The circuitry for Z_SHIFT 32
Presentation Outline The principal Idea Implementation: First Generation Implementation: Second Generation Integer-Flying Flying-Adder Architecture February 15, 2005 Slide 39
Integer-Flying-Adder Architecture Issues with current architecture: since PLL/VCO is running at a fixed frequency => need fractional bits to achieve certain frequency, -> periodic carry-in bit, frequency modulation of the output signal, or, inherent jitter Continued February 15, 2005 Slide 40
Integer-Flying-Adder Architecture Idea: Make PLL programmable Get ride of fractional bit Eliminate the inherent jitter February 15, 2005 Slide 41
Integer-Flying-Adder: Method FREQ = T/ = 1/(f* ) = ((f in *N)/(f*P)) *M Using two integers, FREQ and M, to approximate a real number f. 2 <= FREQ <= 2N, M1 <= M <= M2 February 15, 2005 Slide 42
Integer-Flying-Adder: Algorithm The algorithm to search the best control parameters error_min = very_big_number for ( M 1 <=M<=M 2 ) { freq = ((fin*n)/(f*p))*m error = min( freq-floor(freq), ceiling(freq)-freq ) if (error < error_min ) { error_min = error M best = M if (freq floor(freq)) < 0.5 { FREQ = floor(freq) } else { FREQ = ceiling(freq) } } } February 15, 2005 Slide 43
Integer-Flying-Adder: Error Upper- Bound T-T /T = r* /T <= (1/2) * ((fin*n)/(f*p)) / (((fin*n)/(f*p))*m) = 1/(2*M) <= 1/(2*M 1 ) February 15, 2005 Slide 44
for (2<=F<=64) { for (M 1 <=M<=M 2 ) { F-M-seq(index) = M/F } } Integer-Flying-Adder: Error Distribution Envelope foreach M/F in F-M-sorted-seq(index) { F-M_curr = M/F p_max = 2/(F-M_curr + F-M_prev) e_max = (F-M_curr - F-M_prev)/( F-M_curr + F F-M_prev = F-M_curr } -M_prev) See paper on TCASII (3th paper) for mathematical prove Continued February 15, 2005 Slide 45
Integer-Flying-Adder: Error Distribution Envelope February 15, 2005 Slide 46
Integer-Flying-Adder: Error Distribution Envelope The effect of M2 on the error distribution envelope February 15, 2005 Slide 47
Integer-Flying-Adder: Summary Comparing to original architecture: eliminate the inherent jitter but the PLL loop need adjustment Comparing to Integer-N, the frequency range is much wider. Comparing to Fractional-N, no need to compensate the spurious signals. February 15, 2005 Slide 48
One Application Example: All Digital Phase Lock Loop flying-adder synthesizer All loop variables are digital values, no analog voltage! February 15, 2005 Slide 49
ADPLL: A New Idea FREQ1 Known high frequency Synthesizer1 f hi VCO Synthesizer2 f out f in Measure Frequency frequency of f in Conversion FREQ2 Flying-adder February 15, 2005 Slide 50
ADPLL: A New Idea Goal: fout = N * fin Procedure: Using synthesizer1 to generate a known high frequency fhi (e.g. > 500 MHz), by FREQ1. Using fhi to measure fin.( a simple counter) Get a frequency number of fin. Multiple this frequency number by N and convert it to FREQ2. Using synthesizer2 to generate the fout, by FREQ2. Advantage: fout is not directly related to fin electrically, noise in fin is isolated. PFD and filter are not required. Especially good for multiplying the input frequency to a large number (N is big). The VCO used for flying-adder synthesizers can be a very simple one with minimum analog complexity. Synthesis1 in above diagram can be a very simple one (no fractional part) February 15, 2005 Slide 51
Conclusion A novel frequency synthesis architecture is presented. This architecture can be used to generate many, many frequencies. February 15, 2005 Slide 52
F = p *M F + 1 F + 2 As M sweep As M sweep F F + 1 p, a required frequency February 15, 2005 Slide 53