adashi Suetsugu et al., Vol.3, No., 013 Claping of Switch Peak Voltage with Diode and ransforer at Output of Class E Aplifier for enewable Energy Applications adashi Suetsugu*, Xiuqin Wei * *Departent of Electronics Engineering and Coputer Science, Fukuoka University suetsugu@fukuoka-u.ac.jp, xiuqinwei@fukuoka-u.ac.jp Corresponding Author; adashi Suetsugu, 8-19-1, Nanakua, Johnan, Fukuoka, 814-0180 Japan, +81 98 716 631, suetsugu@fukuoka-u.ac.jp eceived: 7.0.013 Accepted: 04.04.013 Abstract- Solar cells should have shortened life tie in order to achieve effect circulation of renewable energy. In the seiconductor anufacturing operations, plasa process such as CVD, etching doinates large value of energy consuption. educing energy consuption of plasa processing is urged. With using switching power aplifier as a replaceent of linear aplifier, significant energy reduction can be done. However, switching power aplifier has a drawback of destruction of switching device due to high transient switch voltage during practical operation. In this paper, a voltage clap circuit consists of diode and transforer is proposed. his circuit reduces the transient peak switch voltage of the class E aplifier. With adjusting winding ratio of transforers, clap voltage can be arbitrary value. Naely, the diodes can be inactivated in ordinary variations of load ipedance. But, it activates in sudden and significant change of load ipedance. Siulation results showed that the proposed diode clap circuit successfully reduces the transient peak switch voltage. Keywords- Voltage clap circuit, renewable energy, transforer, transient peak switch voltage, axiu perissible value. 1. Introduction It is expected that the Class E aplifier [1-3] can be serve as a replaceent of low efficient linear power aplifiers of F energy sources, especially in application of plasa generator [4]. In plasa generation, the load ipedance varies significantly during operation [5, 6]. In the plasa chaber, the load resistance is ual to via ipedance atcher when the plasa spark resues. On the other hand, the load resistance is approxiately an open circuit when the plasa spark diinishes. Because the load ipedance suddenly varies to an open circuit during operation, the aplitude of output voltage of the class E aplifier becoes very high and soeties a high switch voltage destroys the switching device. In order to avoid a high peak switch voltage, several voltage clap ethods were proposed. In [7] and [8], a Zener diode across the switch [7] and the choke coil [8] of a class E aplifier were presented. Fig. 1. Basic circuit of voltage switching class E aplifier. However, in both ethods, a significant power loss occurred in the Zener diode. Lossless voltage claping with transforer and diode was proposed [9]. However, it could not reduce the peak switch voltage as expected due to leakage inductance of the transforer. Hence, lossless voltage claping using transission transforer was introduced [10]. hese efforts to reduce the peak switch voltage were dedicated for the steady-state operation.
adashi Suetsugu et al., Vol.3, No., 013 herefore, due to leakage inductance of the transforer, they could not reduce the transient peak switch voltage enough. Instruents copany MKS invented diode claping circuit to reduce the transient peak switch voltage [5]. However, the peak switch voltage could not be reduced enough by using the circuit. 50, duty ratio D 0.5, and the loaded-quality factor of output L-C- band-pass filter Q 5. Fig. 3. Conventional diode clap circuit [10]. he circuit coponents are derived in [1] and are given by the following uations: Fig.. Switch voltage wavefor and output voltage wavefor at duty ratio D = 0.5. In this paper, a voltage clap circuit for the class E aplifier is proposed to reduce the transient peak switch voltage. his circuit claps the output voltage of the class E aplifier when the aplitude of output voltage goes over the designated clap voltage level. A rough estiation of the aplitude of output current when the output voltage is claped is described. It was shown with siulation that the transient peak switch voltage was reduced by the proposed clap circuit.. Class E Aplifier and Peak Switch Voltage due to Load Variation A basic circuit of the zero-voltage switching (ZVS) class E aplifier [1] is shown in Fig. 1. his circuit inputs a dc voltage fro the dc power supplyv. he MOSFE switch is driven by a high-fruency gate signal and it switches periodically at the switching fruency f. A periodical switch voltage v S, which is shown as Fig., is generated across drain and source of the switching device. he L-C band-pass filter extracts the fundaental fruency coponent fro the switch voltage wavefor v S. A sinusoidal voltage wavefor is output to the load resistance. A choke inductance L FC is high enough to reduce the ac coponent in it. Hence, the input current through the choke inductance can be considered as a dc current. he loadedquality factor of L-C- band-pass filter is high enough so that the output current can be considered as a pure sinusoid. Hence, the current through the switch is the su of a dc current and a sinusoidal current. he class E aplifier can achieve high efficiency when the switch turns on at zero voltage. In this paper, the class E aplifier was designed to operate under ZVS operation at switching fruency f MHz, dc supply voltage V 15 V, load resistance 8 P 4 V 8 1 C1 4 (1) () Q L (3) and 1 1 C 4 Q 16 (4) f is the angular fruency of the switching fruency f. hen, the circuit paraeters are calculated to be as follows: C1 9 pf, C 413 pf, and L 0 F. If the class E aplifier is operated with the designed load resistance 50, the peak switch voltage is approxiately 5.5 V. Naely, it is approxiately 3.5 ties higher than the dc supply voltage V. On the other hand, the peak switch voltage changes with load variations. he steady-state value of the peak switch voltage was calculated in [11] when the load resistance stayed away fro the designed value. In [11], the peak switch voltage is higher than the designed value when the load resistance is lower than designed value. And the peak switch voltage is lower than that of the designed value when the load resistance is higher than the designed value. However, in soe applications, e.g. in the plasa generation, the load resistance suddenly changes to uch higher than the design value, even to be open-circuited, which results in high peak switch voltage. In particular, it also causes extreely high transient peak switch voltage. Both the high peak switch voltage and extreely high peak switch voltage bring about the daage of the switching devices. Hence, one reedy for this proble is reducing the uivalent load ipedance by short circuiting the load 360
adashi Suetsugu et al., Vol.3, No., 013 resistance by a diode. Fig. 3 shows a conventional diode clap circuit invented by MKS [5]. Fig. 4. Single power supply configuration of diode clap circuit for class E aplifier using transforer. In this circuit, the diode turns on when the voltage across C- circuit drops below ground level. hen, the uivalent load resistance is reduced and the peak switch voltage is also reduced. However, there is a proble in this circuit. he dc bias of the voltage across the load resistance can ove to a higher voltage when the load resistance is open-circuited. hen, the voltage wavefor is not claped by the diode. 3. Claping of Switch Peak Voltage with Diode and ransforer In this paper, we propose a odification of this circuit. Fig. 4 shows the proposed diode claped class E aplifier. wo diodes, transforer, and dc voltage source V, connected to the load resistance, for a voltage liiter. he dc supply voltage source V of the class E aplifier is used as one of the dc voltage source of the voltage liiter. he output voltage of the class E aplifier in the range V v o V. In this circuit, even if the bias of the output voltage wavefor oves to a higher or lower voltage, two diodes clap the output voltage wavefor. Hence, the output voltage is successfully claped and the uivalent output ipedance is reduced. In addition, because of the application of the transforer, the circuit ruires only one dc supply, which can decrease the circuit scale. he effect of diode claping is estiated by deriving an expression for the uivalent load resistance when the output voltage is claped. Fig. 5 shows a typical claped voltage wavefor. In this analysis, it is assued that the output current is a pure sinusoid and can be described as i sin o I t (5) If the clap diode is not present, it is assued that the output voltage is sinusoidal and can be described as v O sin v V sin t I t (6) O he actual output voltage is claped by the diode when V. herefore, the output voltage wavefor is described as v and O t t1 V sin t when t t t1 t t t1 t t V when t1 t t (7) 1 V sin V t1 (8) t 1 V sin V (9) hen, the uivalent load resistance can be obtained using Fourier analysis to find the fundaental fruency coponent I v sin t dt (10) o 0 is the uivalent load resistance and /. Expanding and rearranging (10), is obtained as vo tsin t dt I 0 vo t sin t dt I 0 t 1 t sin sin 4 I t dt V t dt 0 t1 / I 0 I sin t dt t 0 1 V V V sin 1 V V V t (11) t (1) 1 V sin V t1 (13) 1 V sin V t (14) 361
adashi Suetsugu et al., Vol.3, No., 013 exaple circuit, we can be obtain 56., I 0.6 A. he currents flowing through the clap diodes are i D1 nv I sin t t t t 0 otherwise when 1 (15) Fig. 5. (a) Claped output voltage wavefor and (b) transition of load resistance. i D n nv I sin t when t1 t t 0 otherwise (16) L L 1 (17) Hence, the peak diode currents are nv ax id1 ax id I (18) 4. Siulation esults Fig. 6. Graphical deterination of aplitude of output current I. he uivalent reactance is the even function. X is obviously 0 because v O Applying (11) to the circuit paraeters described in Section, is plotted as a function of I as a solid line in Fig. 6. In this plot, it is assued that 500 k. On the other hand, in the operation of the class E aplifier, I varies with load resistance [] because it is outside the designed condition. I versus outside the design conditions as was obtained in []. Both functions I and I are extreely coplicated nonlinear functions. Hence, graphical ethod is one easy way to deterine the operating point. Plotting I of [] versus in Fig. 6, we can find a intersection point of two plots I and I his point is the operating point of I and. In the Siulation was done at f MHz, dc supply voltage V 15 V, load resistance 50, and duty ratio D 0.5 of the class E aplifier. he siulated circuit paraeters were C1 10 pf, C 430 pf, L 18 H, and LFC 175 H. Spice odel of power MOSFE IF510 were used as switching devices and diode D1N4148 as claping devices. Self inductances of transforer were 100μH, 100μH, and 00μH. he gate port G I was operated at MHz and 4 Vp-p and - V offset rectangular signal. In addition, the load resistance is connected to a MOSFE which is driven by GII as shown in Fig. 7. herefore, the load resistance varied between 50 and open circuit periodically at 10 khz. Fig. 7. Actual diode clap circuit for siulation. 36
adashi Suetsugu et al., Vol.3, No., 013 Fig. 8. ransient switch voltage wavefors of class E aplifier. (a) Basic class E aplifier of Fig. 1. (b) Proposed class E aplifier of Fig. 4. Siulation wavefors are shown in Fig. 8. In the basic circuit of Fig. 1, the transient peak switch voltage was approxiately 110 V (Fig. 3(a)). In the proposed circuit, transient peak switch voltage was reduced to 70 V (Fig. 8(b)). able 1. Coaprision of easured peak switch voltages Peak voltage in transient state Peak voltage in steady state Basic class E 110 V 73 V Proposed class E 70 V 60 V 5. Conclusion In this paper, a peak voltage clap circuit was proposed. his circuit can reduce the peak transient voltage if the class E aplifier with diodes and transforers without consuing significant power loss. his claping circuit excludes danger of destruction of switching device during operation of plasa load. In the siulation results, the proposed circuit reduced the transient spike of switch voltage at sudden cut off of load ipedance by approxiately 37%. Further, the peak switch voltage for open circuit load becae lower than that of basic class E aplifier. his also reduces switching loss at open circuit load condition. And, it reduces danger of destruction of switching device due to heat by switching loss, too. eferences [1] M. K. Kaziierczuk and D. Czarkowski, esonant Power Converters, nd ed., vol., New York, NY: John Wiley & Sons, Inc., 011, ch. 1. [] N. O. Sokal and A. D. Sokal, Class E A new class of high-efficiency tuned single-ended switching power aplifiers, IEEE J. Solid-State Circuits, vol. SC-10, pp. 168-176, June 1975. [3]. Suetsugu and M. K. Kaziierczuk, "Diode peak voltage claping of class E aplifier", 37th Annual Conference of the IEEE Industrial Electronics Society (IECON011), Melbourne, Australia, pp. 1318-13, 7-10 Noveber 011. [4] H. Yoo, S. H. Chun, D. H. Lee, J. Y. Ki, J. H. Ki, "High efficiency and high stability 1KW F generator for plasa applications," 0th Asia-Pacific Microwave Conference, Macau, pp. 1-4, 16-0 Deceber 008. [5] D. Lincoln and P. Bennett, "Class E aplifier with inductive clap", US Patent 7,180,758 B, January 004. [6] Y. aniguchi and K. Harada, "he present state and future prospects for radio-fruency induction theral plasa systes", Journal of Plasa and Fusion esearch, vol. 76, no. 8, pp. 754-757, August 000. [7]. Suetsugu and M. K. Kaziierczuk, "Voltage claped class E aplifier with a Zener diode across the choke coil", Proceedings of IEEE International Syposiu on Circuit and Systes (ISCAS00), Arizona, USA, pp. 505-508, May 00 [8]. Suetsugu and M. K. Kaziierczuk, "Voltage claped class E aplifier with Zener diode", IEEE ransactions on Circuits and Systes-I, egular Papers, vol. 50, no. 10, pp. 1347-1348, October 003. [9]. Suetsugu and M. K. Kaziierczuk, "Design procedure of lossless voltage-claped class E aplifier with a transforer and a diode", IEEE ransactions on Power Electronics, vol. 0, no. 1, pp. 56-64, January 005. [10]. Suetsugu and M. K. Kaziierczuk, "Voltageclaped class E aplifer with transission-line transforer", Proceedings of IEEE International Syposiu on Circuits and Systes (ISCAS005), Kobe, Japan, pp. 71-715, 3-6 May 005. [11]. Suetsugu and M. K. Kaziierczuk, "Steady-state behavior of class E aplifier outside designed conditions", IEEE Int. Syp. Circuits Syst. (ISCAS005), Kobe, Japan, pp.708-711, 3-6 May 005 363