CMOS RESET IC Rohm's and are series of high-accuracy, low-power VOLTGE DETECTOR ICs with a CMOS process. For flexible choice according to the application, series with N channel open drain output and series with CMOS output are available in 38 voltage types from.3 V to 6. V in steps of.1 V in different packages, totaling 15 models. pplications Every kind of appliances with microcontroller and logic circuit Features 1) Detection voltage:.1v step line-up.3~6.v (Typ.) ) High-accuracy detection voltage: ±1.5% guaranteed (bility ±1%) 3) Ultra low current consumption:.8µ typ. (Output is High.) 4) Nch open drain output ( series), CMOS output ( series) 5) Small package VSOF5(EMP5) : BD48XXFVE/BD49XXFVE SSOP5(SMP5C) : BD48XXG/BD49XXG Selection guide For BD4XXXX series, detection voltage, output circuit types (Refer to the block diagram at P3), and package (Refer to the dimension at P14) can be selected for your own application. Part number of devices for each specification is shown below. Part No. : B D 4 X X X X Part No. Specification Contents 1 Output circuit types 8 : Open drain output 9 : CMOS output 3 Detection voltage Package 1 3 Ex. : VS : described in each.1v step for.3v~6.v range (9 means.9v) G : SSOP5 (SMP5C) FVE : VSOF5 (EMP5) 1/15
Line-up Detection voltage VS 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V 5.V 5.1V 5.V 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V 4.V 4.1V 4.V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V 3.3V 3.V 3.1V 3.V.9V.8V.7V.6V.5V.4V.3V Nch Open drain output ( ) BD4859G/FVE BD4858G/FVE BD4857G/FVE BD4856G/FVE BD4855G/FVE BD4854G/FVE BD4853G/FVE BD485G/FVE BD4851G/FVE BD485G/FVE BD4849G/FVE BD4848G/FVE BD4847G/FVE BD4846G/FVE BD4845G/FVE BD4844G/FVE BD4843G/FVE BD484G/FVE BD4841G/FVE BD484G/FVE BD4839G/FVE BD4838G/FVE BD4837G/FVE BD4836G/FVE BD4835G/FVE BD4834G/FVE BD4833G/FVE BD483G/FVE BD4831G/FVE BD483G/FVE BD489G/FVE BD488G/FVE BD487G/FVE BD486G/FVE BD485G/FVE BD484G/FVE BD483G/FVE CMOS output ( ) BD4959G/FVE BD4958G/FVE BD4957G/FVE BD4956G/FVE BD4955G/FVE BD4954G/FVE BD4953G/FVE BD495G/FVE BD4951G/FVE BD495G/FVE BD4949G/FVE BD4948G/FVE BD4947G/FVE BD4946G/FVE BD4945G/FVE BD4944G/FVE BD4943G/FVE BD494G/FVE BD4941G/FVE BD494G/FVE BD4939G/FVE BD4938G/FVE BD4937G/FVE BD4936G/FVE BD4935G/FVE BD4934G/FVE BD4933G/FVE BD493G/FVE BD4931G/FVE BD493G/FVE BD499G/FVE BD498G/FVE BD497G/FVE BD496G/FVE BD495G/FVE BD494G/FVE BD493G/FVE Detection voltage VS ( V ) Ta=5 C Min. Typ. Max. 6.V BD486G/FVE BD496G/FVE 5.91 6. 6.9 5.81 5.713 5.615 5.516 5.418 5.319 5.1 5.1 5.4 4.95 4.87 4.78 4.63 4.531 4.433 4.334 4.36 4.137 4.39 3.94 3.84 3.743 3.645 3.546 3.448 3.349 3.51 3.15 3.54.955.857.758.66.561.463.364.66 5.9 5.8 5.7 5.6 5.5 5.4 5.3 5. 5.1 5. 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4. 4.1 4. 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3. 3.1 3..9.8.7.6.5.4.3 5.989 5.887 5.786 5.684 5.583 5.481 5.38 5.78 5.177 5.75 4.974 4.87 4.771 4.669 4.568 4.466 4.365 4.63 4.16 4.6 3.959 3.857 3.756 3.654 3.553 3.451 3.35 3.48 3.147 3.45.944.84.741.639.538.436.335 Hysteresis voltage ( V,Typ. ) VS X.5 Package Pin layout Pin layout of VSOF5(EMP5) and SSOP5(SMP5C) is different as shown below. (Fig.1, Fig.) When used as replacement, please consider the difference. (The detail of packages is shown at P14.) BD48XXG/BD49XXG BD48XXFVE/BD49XXFVE 1 5 N.C. 1 SUB VSOF5 (EMP5) Package 5 1.6mm SSOP5 (SMP5C) Package.9mm N.C. 3 4 3 4 N.C. 1.mm 1.6mm Fig.1 Fig. (Note) Connect SUB pin with pin. /15
Block diagram Two output types can be used. One is (Fig.3) of open drain output type, and the other is (Fig.4) of CMOS output type. : Open drain output : CMOS output Vref Vref Fig.3 Fig.4 bsolute maximum rating (Ta=5 C) To prevent the functional deterioration or thermal damage of semiconductor devices and ensure their service life and reliability, they must be designed and reviewed in such a way that the absolute maximum rating can not be exceeded in any cases or even at any moment. Parameter Symbol Limits Unit Power supply voltage.3 ~ + 1 V Output Nch Open drain output.3 ~ + 1 voltage CMOS output.3 ~ +.3 V Power dissipation SSOP5 (SMP5C) * 1 Pd 15 mw Power dissipation VSOF5 (EMP5) * *3 Pd 1 mw Operating temperature Topr 4 ~ + 85 C Storage temperature Tstg 55 ~ + 15 C *1 Derating : 1.5mW/ C for operation above Ta=5 C * Derating : 1.mW/ C for operation above Ta=5 C *3 When only IC is used. Power supply voltage This voltage is the applied voltage between and. The applied voltage should not exceed the indicated value. Output voltage pin voltage should not exceed the indicated value. For Nch open drain output type, applied voltage and pin H output voltage can be used independently. Both of them should not exceed the each indicated value. Operating temperature range The circuit function is guaranteed within the temperature range. However, the operating characteristics are different from that of Ta=5 C. If they are any questions about the extent of guarantee of circuit functions in this operating temperature range, please ask for more technical information. Storage temperature range This IC can be stored up to this temperature range without deterioration of characteristics. However, an abrupt thermal shock of extreme temperature fluctuations may cause the deterioration of characteristics. 3/15
Power dissipation Power consumption of the IC Circuit current at ON/OFF is very small. Power consumption in output depends on each load connected with pin. Please note that total power consumption must be within a power dissipation range in the secure area of the entire operating temperature. Power dissipation of these packages; SSOP5 (SMP5C) package (BD48XXG/BD49XXG) Fig.5, and VSOF5 (EMP5) package (BD48XXFVE/BD49XXFVE) Fig.6 is shown below. SSOP5 (SMP5C) package BD48XXG BD49XXG EMP5 (VSOF5) package BD48XXFVE BD49XXFVE Power dissipation (mw) 15 1 Power dissipation (mw) 15 1 5 5 5 5 75 1 15 5 5 75 1 15 mbient temperature Ta( C) Fig.5 Thermal derating curve mbient temperature Ta( C) Fig.6 Thermal derating curve When it is used in the ambient temperature of (Ta)=5 C and more, make reference to each thermal derating characteristics of used package. Both Fig.5 and Fig.6 show these characteristic when only IC is used. Electrical characteristics (Unless otherwise noted; Ta=-5 C ~ 85 C) Parameter Symbol Min. Tap. Max. Unit Conditions Detection voltage temperature coefficient VS/ T ±1 ±36 ppm/ C Hysteresis voltage VS VS X.3 VS X.5 VS X.8 V RL=47kΩ, =L H L "H" transfer delay time TPLH 1 µs CL=1pF, RL=1kΩ * = 5% *1.51 1.53 VS=.3~3.1V Circuit current when ON ICC1.56 1.68 VS=3.~4.V µ =Vs.V.6 1.8 VS=4.3~5.V.66 1.98 *1 VS=5.3~6.V.75.5 VS=.3~3.1V Circuit current when OFF.8.4 µ VS=3.~4.V ICC =Vs+V.85.55 VS=4.3~5.V.9.7 *1 VS=5.3~6.V Min. operating voltage VOPL.95 V RL=47kΩ, VOL.4V *1 "L" output current IOL.4 1 VDS=.5V, =1.V m. 4 VDS=.5V, =.4V (VS.7V).7 1.4 VDS=.5V, =4.8V VS=.3~4.V "H" output current IOH.9 1.8 m VDS=.5V, =6.V VS=4.3~5.V 1.1. VDS=.5V, =8.V VS=5.3~6.V Output leak current Ileak.1 µ =VDS=1V *1 *1 Operation is guaranteed forta=5 C. * TPLH : =(VS typ..5v) (VS typ.+.5v). Note) RL is not necessary for CMOS output type. Note) Minimum operating voltage output becomes inconsistent if the is equal to or lower than the operating limit voltage. It goes open, H, or L. Note) Hysteresis voltage=(reset release voltage)-(reset detection voltage) [V] Reference Fig.33 Fig.31 Fig.1,13 15,17 Fig.8 Fig.31 Fig.9 Fig.3 Fig.3 Term explanation Detection voltage (VS) : voltage when the output (Vout) goes from "H" to "L". Release voltage (VS+ VS) : voltage when output (Vout) goes from "L" to "H". Hysteresis voltage : The difference between detection voltage and release voltage. Malfunction due to noise in (within hysteresis voltage) could be avoided by hysteresis voltage. 4/15
Operating explanation Ex.) For both open drain type (Fig.7) and CMOS output type (Fig.8), detection voltage and release voltage are threshold voltage. When voltage applied to pin reaches each threshold voltage, pin voltage goes "H" "L" or "L" "H". series are open drain types and pull-up resistor must be connected to, or other power supply. (In this case, output () H voltage is, or other power supply voltage.) Vref R1 RL Vref R1 Q R R R3 Q1 R3 Q1 Fig.7 (BD48XX type Internal block diagram) Fig.8 (BD49XX Internal block diagram) SWEEP DOWN for When is equal to or more than the release voltage (Vs+ Vs), output is in "H" mode. (Nch output transistor Q1 is OFF, Pch output transistor Q is ON.) When is gradually decreased, output () turns "L" in the detection voltage (Vs). (Nch output transistor Q1 is ON, Pch output transistor Q is OFF.) SWEEP UP for When is equal to or lower than the detection voltage (Vs+ Vs), output is in "L" mode. (Nch output transistor Q1 is ON, Pch output transistor Q is OFF.) When is gradually increased, output () turns "H" in the release voltage (Vs). (Nch output transistor Q1 is OFF, Pch output transistor Q is ON.) Some hysteresis is given such a way that the release voltage is the detection voltage X (1.5 Typ.). The output becomes inconsistent if the is equal to or lower than the operating limit voltage. Timing waveform Ex.) The relation between input voltage and output voltage when is increased and decreased is shown below. (Circuit is shown above. Fig7, 8) VS+ VS VS VOPL V VOH VOL TPLH TPHL TPLH 1 3 4 If the is equal to or lower than the operating limit voltage (VOPL) at power-up, the output is inconsistent. When the is equal to or lower than the reset release voltage (Vs+ Vs), =L. When exceeds the Reset Release Voltage, turns H with a delay of TPLH. See Fig. 15 and 17 for the reference waveform. If the goes below the detection (Vs) at power-down or instantaneous power failure, turns L with a delay of TPHL. 1 3 4 Fig.9 See Fig.16 and 18 for the reference waveform. The potential difference between the detection voltage and the release voltage is called hysteresis ( Vs). The products are designed so as to prevent power supply fluctuation within this hysteresis from causing fluctuation in output in order to avoid malfunction due to noise. 5/15
pplication circuit 1)pplication circuit as ordinal supply detection reset is shown below. 1 1 RL BD48XXX ( ) CL RST Micro controller BD49XXX ( ) CL RST Micro controller (Noise filtering capacitor) (Noise filtering capacitor) Fig.1 Open collector output type Fig.11 CMOS output type Output type of series (Open drain type) and series (CMOS type) is different. n example of usage is shown below. When the power supply of microcontroller () and power supply for the reset detection (1) is different. Provide RL for the output of a product with open drain output ( series) on the side, as shown in Fig.1. When the power supply of microcontroller and that of reset is same (1). product with CMOS output ( series) can be used as shown in Fig.11. Or if RL is provided with open drain output ( series) on the 1 side, it can be used. When the capacitor CL for noise filtering and for delay time setting is connected to pin (reset signal input pin of microcontroller), make a setting in consideration of the wave rounding of the rise and fall of. (See the delay shown in Fig.14 as the reference.) delay time (µs) 1 1 1 1 1 Output delay time "L H" 1 1 CL Capacitance (pf) delay time (µs) 8 79 78 77 76 75 74 73 7 71 7 1 Output delay time "H L" 1 1 CL Capacitance (pf) 5V 5V RL=1KΩ RL=1KΩ VS±.5V CL VS±.5V CL Fig.1 Fig.13 Release voltage (VS+ VS).5V.5V Detection voltage VS [V] 5V =5V X.5 [V] TPLH TPHL Fig.14 Delay time I/O condition 6/15
Test data TPLH TPHL Fig.15 BD4845G TPLH output waveform Fig.16 BD4845G TPHL output waveform TPLH TPHL Fig.17 BD4945G TPLH output waveform Fig.18 BD4945G TPHL output waveform 1k Reference data : BD4845G test data RL=1kΩ CL=1pF BD4845G 1pF Reference data : BD4945G test data CL=1pF BD4945G 1pF 7/15
)pplication circuit when microcontroller is reset with OR connection of the two types of the detection voltage is shown below. 1 3 BD48XXX BD48XXX RL RST Micro controller Fig.19 When there is more than one system power supply and it is necessary to individually monitor the power supply (1, ) to reset the microcontroller, open drain output type series can be connected to form an OR circuit as shown in Fig.19 for pulling up to an arbitrary voltage (3) to adjust the H voltage of the output to the microcontroller power supply (3). 3)pplication circuit when it is used as Power-on reset is shown below. (However, it can be used for only series.) R Di BD48XXX RL Micro controller C Fig. If the power supply voltage is lower than the guaranteed range, power-on reset of the microcontroller is necessary to prevent program runaways and unwanted memory register updates. power-on reset circuit used with series (Nch open drain) is shown in Fig.. C and R conneceted to pin of RESET IC make the wave rounding of the pin and generate input signal with time constant. When the input power supply is fallen, the electric charge of the capacitor is discharged through Di connected between pin and. The value of the resister R should be enough to prevent malfunction caused by circuit current through series. Set in such a way that the following expression stands: Hysteresis > R X { (Circuit current at ON) - (Circuit current at OFF) } Do not use series (CMOS output) for the power-on reset because malfunction may occur. (Oscillation at output etc.) The feed through current (CMOS output) at detection may cause malfunction mentioned above. (Feed through current is the current flowed from into instantly when output goes "H" "L". ) ICC Feed through current Feed through current VS Fig.1 CMOS output circuit Fig. Current consumption Vs. power supply voltage 8/15
Establishment of RESET transfer delay time Delay time at the rise and fall of can be established by RL, CL connected to pin. Delay time at the rise of TPLH : Time until when is 1/ of after the rise of, and beyond the release voltage (Vs+ Vs).(See P7). It is the total time established by IC internal transfer delay time TD and external RL, and CL. RESET pin voltage OUT Output Tr OFF RL CL RESET voltage [V] 63% 5% =CL X RL Fig.3 t Time.69 X Fig.4 RESET pin voltage If the threshold voltage of the RESET terminals is 1/ of VCC, delay time TPLH at the rise of is shown in the expression below. TPLH=.69 X CL X RL+TD TD=Internal circuit delay of BD48XX : bout 35µs (typ.) =(Vs.5V) CL : Capacity of external capacitor beween pin and RL : External resistance between pin and power supply (Vs+.5V) Delay time at the fall of TPHL : Time until when is 1/ of after across the detection voltage (Vs).(See P7). It is the total time established by IC internal transfer delay time TD and external RL, and CL. Output Tr ON IOL RL CL Fig.5 RESET TPHL=+B = bout 7µs(Typ.) : Internal IC transfer delay time of BD484 Vout voltage[v] Vs t B Time Fig.6 RESET pin voltage B = CL X Vs : Delay time by external CL, RL IOL CL : Capacity of external capacitor beween pin and Vs : Detection voltage IOL : "L" output current of BD48XX Make sure to test in actual because it depends on detection voltage. Reference:VS=.4V, =bout 8m at :typ. TPLH.5V.5V TPHL Fig.7 Delay time I/O condition Detection voltage VS [V] = X.5 [V] 9/15
Characteristic data (Reference data) 18 45 [BD494G/FVE] 1.5 15 4 35 3 IDD [µ] 1..5 IOL [m] 1 5 =.4V =1.V IDS [m] 5 15 1 5 =8.V =6.V =4.8V 1 3 4 5 6 7 8 9 1 [V].5 1 VDS [V] 1.5.5 1 3 4 5 6 VDS [V] VDS VDS Fig.8 Circuit current Fig.9 "L" output current Fig.3 "H" output current 9 4 8 3 7 6 1 [V] 5 4 3 Ileak [µ] -1 - Ta=5 C -3 1 Ta=5 C -4.5 1 1.5.5 3 3.5 4 4.5 5 5.5 [V] 4 6 8 1 1 VDS [V] RL=47KΩ V VDS Fig.31 I/O characteristic Fig.3 Output leak current 1/15
5.4 5. 1. 1. 4.6 low to high(vs+ VS) VS [V] 4. high to low(vs) IDD [µ].5 IDD [µ].5 3.8 3.4 4 5 Ta [ C] 9-4 - 4 6 8 1 Ta [ C] -4-4 6 8 1 Ta [ C] RL=47KΩ V Fig.33 Detection voltage (VS) Release voltage (VS+ VS) Fig.34 Circuit current on ON (VS-.V) Fig.35 Circuit current on OFF (VS+.V) 1. 1 Ileak [µ] -1 VOPL[V].5 - -4-4 6 8 1 Ta [ C] -4-4 6 8 Ta [ C] 1 RL=47KΩ V VDS Fig.36 Output leak current Fig.37 Operating limit voltage 11/15
Taping specification 1)Dimension of tape Rectangular recess to hold a component Circular feed hole D E F W B t K D1 P P1 P Fig.38 Package SSOP5 (SMP5C) (mm) Symbol B D D1 E F P P1 Dimension 3.±.1 3.1±.1 1.5 +.1 1.1±.1 1.75±.1 3.5±.5 4.±.1 4.±.1 Symbol P t K W Dimension.±.5.3±.5 1.3±.1 8.±. Package VSOF5 (EMP5) (mm) Symbol B D D1 E F P P1 Dimension 1.83±.1 1.83±.1 1.5 +.1.5±.1 1.75±.1 3.5±.5 4.±.1 4.±.1 Symbol P t K W Dimension.±.5.5±.5.75±.1 8.±. 1/15
)Dimension of reel TMX E D C B W t Fig.39 (mm) Symbol B C D E W t TMax. Dimension 18 Max. 6±. 13.±.5. Min. 1.5 Min. 9.±.3 Label side(1.) Back side(1.) 17.4 3)Standard packaged quantity and IC direction The standard packaged quantity is 3, pcs/reel. Orders should be in multiples of the standard packaged quantity. The ICs are TR oriented (as shown below). First pin Fig.4 (Leader side) 13/15
Recommended mounting conditions SSOP5 (SMP5C) allows either reflow or flow soldering mounting. VSOF5 (EMP5) allows reflow mounting. The mounting conditions are shown below. 1)Reflow Max. 1s Max.4 C 35 C 14 C 16 C 9±3s Up to two reflows are allowed. Fig.41 )Flow soldering Treatment process Preheating section Solder bath Condition Temperature Time 15±1 C 6~1s Max. 6 C Max. 1s 3)Product storage conditions Store the products in an environment of 5~3 C in temperature and 7% RH or lower in humidity. Dimension 1.6±.5 1.±.5 5 4 (UNIT:mm).MX.8±. +. 1.6 -.1.9±. (5) (4) (UNIT:mm) 4 + 6-4.MIN 1.6±.5 1.±.5.6MX 1.5 3 Lot No..±.5.13±.5.8 M (1) 1.5MX 1.1±.5±.5.5 () (3).95.1 +.5.13.3.4 +.5 -.4 VSOF5 (EMP5) SSOP5 (SMP5C) 14/15
Reference land pattern VSOF5 (EMP5) SSOP5 (SMP5C) e e e e e1 e1 b Fig.4 Fig.43 b Lead pitch e Lead pitch e1 Land length Unit:mm Land width b.5 1.35.35.5 Lead pitch e Lead pitch e1 Land length Unit:mm Land width b.95.4 1..6 For actual designing, take the board density, mountability, dimension tolerance, etc. for optimization. Part number and marking of samples The BD48XX and BD49XX series products allow optimum selection of detection voltage, output circuit type and package according to the application. Part No. B D 4 X X X X 1 3 Part No. Specification Contents 1 3 Output circuit type Detection voltage Package 8 : Open drain output 9 : CMOS output Ex : VS : described in each.1v step for.3v~6.v range (9 means.9v) G : SSOP5 (SMP5C) FVE : VSOF5 (EMP5) Marking Voltage Part No. Marking Voltage Part No. Marking Voltage Part No. Marking Voltage Part No. EW 6.V BD486 EB 4.1V BD4841 GW 6.V BD496 GB 4.1V BD4941 EV EU ET ES ER EQ EP 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V BD4859 BD4858 BD4857 BD4856 BD4855 BD4854 BD4853 E DV DU DT DS DR DQ 4.V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V BD484 BD4839 BD4838 BD4837 BD4836 BD4835 BD4834 GV GU GT GS GR GQ GP 5.9V 5.8V 5.7V 5.6V 5.5V 5.4V 5.3V BD4959 BD4958 BD4957 BD4956 BD4955 BD4954 BD4953 G FV FU FT FS FR FQ 4.V 3.9V 3.8V 3.7V 3.6V 3.5V 3.4V BD494 BD4939 BD4938 BD4937 BD4936 BD4935 BD4934 EN EM 5.V 5.1V BD485 BD4851 DP DN 3.3V 3.V BD4833 BD483 GN GM 5.V 5.1V BD495 BD4951 FP FN 3.3V 3.V BD4933 BD493 EL 5.V BD485 DM 3.1V BD4831 GL 5.V BD495 FM 3.1V BD4931 EK EJ EH EG EF EE ED 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V BD4849 BD4848 BD4847 BD4846 BD4845 BD4844 BD4843 DL DK DJ DH DG DF DE 3.V.9V.8V.7V.6V.5V.4V BD483 BD489 BD488 BD487 BD486 BD485 BD484 GK GJ GH GG GF GE GD 4.9V 4.8V 4.7V 4.6V 4.5V 4.4V 4.3V BD4949 BD4948 BD4947 BD4946 BD4945 BD4944 BD4943 FL FK FJ FH FG FF FE 3.V.9V.8V.7V.6V.5V.4V BD493 BD499 BD498 BD497 BD496 BD495 BD494 EC 4.V BD484 DD.3V BD483 GC 4.V BD494 FD.3V BD493 BD48XXG/BD49XXG SSOP5 (SMP5C) (5) (4) (1) () (3) Mark BD48XXFVE/BD49XXFVE VSOF5 (EMP5) (5) (4) (1) () (3) Lot.No Mark Lot.No 15/15
ppendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. pplication circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. ny data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document use silicon as a basic material. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. bout Export Control Order in Japan Products described herein are the objects of controlled goods in nnex 1 (Item 16) of Export Trade Control Order in Japan. In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause) on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction. ppendix1-rev1.