GHz Low Noise Silicon MMIC Amplifier Technical Data INA-63 Features Ultra-Miniature Package Internally Biased, Single 5 V Supply (12 ma) db Gain 3 db NF Unconditionally Stable Applications Amplifier for Cellular, Cordless, Special Mobile Radio, PCS, ISM, Wireless LAN, DBS, TVRO, and TV Tuner Applications Surface Mount SOT-363 (SC-7) Package Pin Connections and Package Marking GND 1 GND 2 INPUT 3 6 OUTPUT 5 GND 4 Description Hewlett-Packard s INA-63 is a Silicon monolithic amplifier that offers excellent gain and noise figure for applications to GHz. Packaged in an ultra-miniature SOT-363 package, it requires half the board space of a SOT-143 package. The INA-63 uses a topology which is internally biased, eliminating the need for external components and providing decreased sensitivity to ground inductance. Equivalent Circuit (Simplified) Note: Package marking provides orientation and identification. The INA-63 is fabricated using HP s 3 GHz f MAX ISOSAT TM Silicon bipolar process which uses nitride self-alignment submicrometer lithography, trench isolation, ion implantation, gold metallization, and polyimide intermetal dielectric and scratch protection to achieve superior performance, uniformity, and reliability. INPUT OUTPUT GROUND 6-1 5965-968E
Absolute Maximum Ratings Absolute Symbol Parameter Units Maximum [1] Supply Voltage, to ground V 12 P in CW Input Power dbm +13 T j Junction Temperature C 15 T STG Storage Temperature C -65 to 15 INA-63 Electrical Specifications [3], T C = 25 C, Z O = 5 Ω, = 5 V Note: 3. Reference plane per Figure 9 in Applications Information section. 6-152 Thermal Resistance [2] : θ jc = 2 C/W Notes: 1. Operation of this device above any one of these limits may cause permanent damage. 2. T C = 25 C (T C is defined to be the temperature at the package pins where contact is made to the circuit board) Symbol Parameters and Test Conditions Units Min. Typ. Max. G p Power Gain ( S 21 2 ) f = 15 MHz db 18 NF Noise Figure f = 15 MHz db 3 P 1dB Output Power at 1 db Gain Compression f = 15 MHz dbm - IP 3 Third Order Intercept Point f = 15 MHz dbm +6 VSWR Input VSWR f = 15 MHz 1.3 Output VSWR f = 15 MHz 1.8 I cc Device Current ma 12 14 ι d Group Delay f = 15 MHz ps 24 INA-63 Typical Scattering Parameters [3], T C = 25 C, Z O = 5 Ω, = 5. V Freq. S 11 S 21 S 12 S 22 K GHz Mag Ang db Mag Ang db Mag Ang Mag Ang Factor.5 7 177 2.8 1.94-4 -3.9.29-1.23-5 1.65 7 175 2.8 1.95-7 -3.8.29-2.23-8 1.65.2 6 17 2.8 1.94-14 -3.9.28-4.23-16 1.7.3 6 166 2.7 1.89-21 -31..28-5.23-25 1.7.4 4 162 2.8 1.94-28 -31.2.28-7.24-33 1.69.5 3 159 2.8 1.96-35 -31.3.27-9.24-43 1.74.6 2 158 2.8 11. -42-31.5.27-1.24-52 1.74.7 158 2.9 11.6-49 -31.6.26-12.24-61 1.79.8.8 164 2.9 11.6-57 -31.9.26-14.25-69 1.78.9.7 172 2.9 11.1-64 -32.1.25-15.26-77 1.83 1..7-174 2.9 11.1-72 -3.24-17.26-85 1.89 1.1.7-156 2.9 11.14-8 -32.7.23-18.27-94 1.95 1.2.8-142 2.9 11.11-88 -33.2.22-21.27-13 2.2 1.3-135 2.9 11.8-96 -33.5.21-23.28-113 2.1 1.4 2-131 2.8 11.1-15 -33.9.2-25.28-122 2.19 1.5 4-131 2.7 1.88-113 -34.6.19-28.28-131 2.31 1.6 7-132 2.6 1.71-122 -35.2.17-3.28-14 7 1.7 9-134 1.45-131 -36..16-33.28-15 2.77 1.8.22-135 2 16-139 -36.8.14-36.27-159 3.2 1.9.24-139 19.8 9.78-148 -37.8.13-39.27-168 3.53 2..26-142 19.4 9.37-157 -39.1.11-42.25-177 4.32 2.1.28-145 19. 8.9-165 -4.6.9-47.24 175 5.49 2.2.3-148 18.5 8.42-174 -42.2.8-53.22 166 6.49 2.3.32-1 18. 7.96 179-44.3.6-63.21 158 9.3.33-154 17.4 7.45 171-46.7.5-79.2 15 11..35-157 16.9 6.98 164-48.9.4-18 8 143 15.2 3..41-169 13.8 4.89 133-39..11 163 115 7.64 3.5.45-179 1.8 3.48 18-31.9.25 146.3 123 4.61 4..5 172 8.3 9 88-26.9.45 132.5-132 3.29
INA-63 Typical Performance, T C = 25 C, Z O = 5 Ω, = 5 V 24 5. 4 GAIN (db) 22 2 18 16 14 5. V NOISE FIGURE (db) 4.5 4. 3.5 3. 2. 5. V P 1 db (dbm) 2-2 -4-6 5. V 12 1.5-8 1.5.45.85 1.25 1.65 5 1..5.9 1.3 1.7 2.1-1.9 1.5 2.1 2.7 Figure 1. Gain vs. Frequency and Voltage. Figure 2. Noise Figure vs. Frequency and Voltage. Figure 3. Output Power for 1 db Gain Compression vs. Frequency and Voltage. GAIN (db) 24 22 2 18 16 14 NOISE FIGURE (db) 5. 4.5 4. 3.5 3. 2. P 1 db (dbm) 6 4 2-2 -4-6 12 1.6 1.2 1.8 3. 1.5 1..3.6.9 1.2 1.5 1.8 2.1 2.7-8 -1.6 1.2 1.8 Figure 4. Gain vs. Frequency and Temperature. Figure 5. Noise Figure vs. Frequency and Temperature. Figure 6. Output Power for 1 db Gain Compression vs. Frequency and Temperature. 2.2 25 VSWR (n:1) 2. 1.8 1.6 1.4 1.2 VSWR IN VSWR OUT I CC (ma) 2 15 1 5 1..5.45.85 1.25 1.65 5 1 2 3 4 5 6 7 (V) Figure 7. Input and Output VSWR vs. Frequency. Figure 8. Supply Current vs. Voltage and Temperature. 6-153
INA-63 Applications Information Introduction The INA-63 is a silicon IC amplifier with a 5 Ω input and output. The INA-63 is easy to use for low noise and multipurpose gain block applications up to GHz. Phase Reference Planes The positions of the reference planes used to measure S-Parameters are shown in Figure 9. As seen in the illustration, the reference planes are located at the point where the package leads contact the test circuit. Biasing The INA-63 is a voltage biased device and operates from a single +5 volt power supply with a typical current drain of only 12 ma. All bias regulation circuitry is integrated into the IC. The supply voltage for the INA-63 is fed in through the separate pin of the device and does not require isolation from the input or output. No additional external DC components are needed. REFERENCE PLANES Operating Details The INA-63 is very easy to use. The basic application of the INA- 63 is shown in Figure 1. DC blocking capacitors are placed in series with the Input and Output to isolate adjacent stages from the internal bias voltages that are present at these terminals. The values of the blocking capacitors are determined by the lowest operating frequency. The values for the blocking capacitors are chosen such that their reactances are small relative to 5 Ω. As an example, use of the INA-63 for a GHz application would require blocking capacitors of at least 33 pf. The connection to the amplifier must be bypassed by placing a capacitor to ground directly at the bias pin of the package. Like the DC blocking capacitors, the value of the bypass capacitor is determined by the lowest operating frequency for the amplifier. This value may typically be the same as that of the DC blocking capacitors. If long bias lines are used to connect the amplifier to the supply, additional bypass capacitors may be needed to prevent resonances that would otherwise result in undesirable gain responses. A well-bypassed line is also desirable to prevent possible oscillations that may occur due to feedback through the bias line from other stages in a cascade. SOT-363 PCB Layout The INA-63 is packaged in the miniature SOT-363 (SC-7) surface mount package. A PCB pad layout for the SOT-363 package is shown in Figure 11 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the high frequency performance of the INA-63. The layout is shown.35.26.16 Figure 11. PCB Pad Layout (Dimensions in Inches)..7 TEST CIRCUIT Figure 9. Reference Planes. INPUT C block C block OUTPUT C bypass Figure 1. Basic Amplifier Application. 6-154
with a nominal SOT-363 package footprint superimposed on the PCB pads. Layout The layout in Figure 12 is suggested as a starting point for designs using the INA-63 amplifier. Adequate grounding is needed to obtain maximum performance and to reduce the possibility of potential instability. All three ground pins of the IC should be connected to C ground by using plated through holes (vias) near the package terminals. The power supply connection to the amplifier must be bypassed by placing a capacitor directly to ground at the pin of the package. It is recommended that the PCB traces for the ground pins NOT be connected together underneath the body of the package. PCB pads hidden under the package cannot be adequately inspected for SMT solder quality. FR-4 or G-1 PCB material is a good choice for most low cost wireless applications. Typical board thickness is.25 or.31 inches. The width of 5 Ω microstriplines in these PCB thicknesses is also convenient for mounting chip components such as the series inductor at the input for impedance matching or for DC blocking capacitors. For noise figure sensitive applications, the use of PTFE/glass dielectric materials may be warranted to minimize transmission line losses at the amplifier input. OUTPUT 5 Ω 5 Ω Figure 12. Layout. INPUT INA-63 Part Number Ordering Information Part Number Devices per Container Container INA-63-TR1 3, 7" reel INA-63-BLK 1 Antistatic bag Package Dimensions Outline 63 (SOT-363/SC-7) 1.3 (.) REF. 2.2 (.87) 2. (.79) 1.35 (.53) 1.15 (.45) 2.2 (.87) 1.8 (.71).65 BSC (.25).425 (.17) TYP. (.4). (.).3 REF..25 (.1) 5 (.6) 1. (.39).8 (.31) 1.3 (.12) (.4).2 (.8) (.4) DIMENSIONS ARE IN MILLIMETERS (INCHES) 6-155