Easily Interfaced to Microprocessors On-Chip Data Latches Monotonic Over the Entire A/D Conversion ange Interchangeable With Analog Devices AD72 and PMI PM-72 Fast Control Signaling for Digital Signal Processor (DSP) Applications Including Interface With TMS20 Voltage-Mode Operation CMOS Technology KEY PEFOMANCE SPECIFICATIONS esolution Linearity Error Power Dissipation at VDD = V Settling Time at VDD = V Propagation Delay Time at VDD = V bits /2 LSB 20 mw 00 ns 0 ns TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 (MSB) DB7 DB DB DB4 DW O N PACKAGE (TOP VIEW) 2 4 7 9 0 20 9 7 4 2 FN PACKAGE (TOP VIEW) V DD DB0 (LSB) DB DB2 DB description The TLC72C, TLC72E, and TLC72I are dual, -bit, digital-to-analog converters designed with separate on-chip data latches and feature exceptionally close DAC-to-DAC matching. Data is transferred to either of the two DAC data latches through a common, -bit, input port. Control input determines which DAC is to be loaded. The load cycle of these devices is similar to the write cycle of a random-access memory, allowing easy interface to most popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, where glitch impulse is typically the strongest. These devices operate from a -V to -V power supply and dissipates less than mw (typical). The 2- or 4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than a current output. efer to the typical application information in this data sheet. The TLC72C is characterized for operation from 0 C to 70 C. The TLC72I is characterized for operation from 2 C to C. The TLC72E is characterized for operation from 40 C to C. AVAILABLE OPTIONS (MSB) DB7 DB PACKAGE TA SMALL OUTLINE (DW) CHIP CAIE (FN) PLASTIC DIP (N) 0 C to 70 C TLC72CDW TLC72CFN TLC72CN 2 C to C TLC72IDW TLC72IFN TLC72IN 40 C to C TLC72EDW TLC72EFN TLC72EN 4 2 20 9 7 7 4 9 0 2 DB DB4 DB DB2 DB V DD DB0 (LSB) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 functional block diagram Data Inputs DB0 4 2 0 9 Input Buffer Latch A 4 Î DACA 2 DB7 7 Logic Control Latch B Î 9 20 operating sequence tsu() th() tsu(dac) th(dac) tw() tsu(d) th(d) DB0 DB7 Data In Stable 2 POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V DD (to or ).................................... 0. V to. V Voltage between and......................................................... ±V DD Input voltage range, V I (to ).............................................. 0. V to V DD 0. eference voltage, V refa or V refb (to )................................................. ±2 V Feedback voltage V or V (to )............................................... ±2 V Output voltage, V OA or V OB (to )...................................................... ±2 V Peak input current........................................................................ 0 µa Operating free-air temperature range, T A : TLC72C................................... 0 C to 70 C TLC72I................................ 2 C to C TLC72E................................ 40 C to C Storage temperature range, T stg.................................................. C to 0 C Case temperature for 0 seconds, T C : FN package.......................................... 20 C Lead temperature, mm (/ inch) from case for 0 seconds: DW or N package............... 20 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VDD = 4.7 V to.2 V VDD = 4. V to. V MIN NOM MAX MIN NOM MAX eference voltage, VrefA or VrefB ± 0 ±0 V High-level input voltage, VIH 2.4. V Low-level input voltage, VIL 0.. V setup time, tsu() 0 0 ns hold time, th() 0 0 ns DAC select setup time, tsu(dac) 0 0 ns DAC select hold time, th(dac) 0 0 ns Data bus input setup time tsu(d) 2 2 ns Data bus input hold time th(d) 0 0 ns Pulse duration, low, tw() 0 0 ns TLC72C 0 70 0 70 Operating free-air temperature, TA TLC72I 2 2 C TLC72E 40 40 UNIT POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 electrical characteristics over recommended operating free-air temperature range, V refa = V refb = 0 V, V OA and V OB at 0 V (unless otherwise noted) PAAMETE TEST CONDITIONS VDD = V VDD = V MIN TYP MAX MIN TYP MAX IIH High-level input current VI = VDD 0 0 µa IIL Low-level input current VI = 0 2 0 2 0 µa IIkg IDD eference input impedance or to Output leakage current Input resistance match ( to ) DAC data latch loaded with 00000000, VrefA = ±0 V DAC data latch loaded with 00000000, VrefB = ±0 V UNIT 20 20 kω ±400 ±200 ±400 ±200 ±% ±% DC supply sensitivity, gain/ VDD VDD = ±0% 0.04 0.02 %/% Supply current (quiescent) All digital inputs at VIHmin or VILmax na 2 2 ma IDD Supply current (standby) All digital inputs at 0 V or VDD 0. 0. ma Ci Input capacitance,, Co Output capacitance (, ) All typical values are at TA = 2 C. DB0DB7 0 0 pf DAC data latches loaded with 00000000 DAC data latches loaded with pf 0 0 20 20 pf 4 POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 operating characteristics over recommended operating free-air temperature range, V refa = V refb = 0 V, V OA and V OB at 0 V (unless otherwise noted) PAAMETE TEST CONDITIONS VDD = V VDD = V MIN TYP MAX MIN TYP MAX Linearity error ±/2 ±/2 LSB Settling time (to /2 LSB) See Note 00 00 ns Gain error See Note 2 2. 2. LSB AC feedthrough to to See Note Temperature coefficient of gain See Note 4 0.007 0.00 %FS/ C Propagation delay (from digital input to 90% of final analog output current) See Note 0 0 ns Channel-to-channel to See Note 77 77 isolation to See Note 7 77 77 db Digital-to-analog glitch impulse area Measured for code transition from 00000000 to, TA = 2 C 0 440 nv s Digital crosstalk Measured for code transition from 00000000 to, TA = 2 C UNIT db 0 0 nv s Harmonic distortion Vi = V, f = khz, TA = 2 C db NOTES:., load = 00 Ω, Cext = pf; and at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V. 2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FS) = Vref LSB.. Vref = 20 V peak-to-peak, 00-kHz sine wave; DAC data latches loaded with 00000000. 4. Temperature coefficient of gain measured from 0 C to 2 C or from 2 C to 70 C.. VrefA = VrefB = 0 V; / load = 00 Ω, Cext = pf; and at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V.. Both DAC latches loaded with ; VrefA = 20 V peak-to-peak, 00-kHz sine wave; VrefB = 0; TA = 2 C. 7. Both DAC latches loaded with ; VrefB = 20 V peak-to-peak, 00-kHz sine wave; VrefA = 0; TA = 2 C. PINCIPLES OF OPEATION These devices contain two identical, -bit-multiplying D/A converters, DACA and. Each DAC consists of an inverted -2 ladder, analog switches, and input data latches. Binary-weighted currents are switched between DAC output and, thus maintaining a constant current in each ladder leg independent of the switch state. Most applications require only the addition of an external operational amplifier and voltage reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure. Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for. Both DACs share the analog ground terminal (). With all digital inputs high, the entire reference current flows to. A small leakage current (I Ikg ) flows across internal junctions, and as with most semiconductor devices, doubles every 0 C. C o is due to the parallel combination of the NMOS switches and has a value that depends on the number of switches connected to the output. The range of C o is 0 pf to 20 pf maximum. The equivalent output resistance (r o ) varies with the input code from 0. to where is the nominal value of the ladder resistor in the -2 network. These devices interface to a microprocessor through the data bus,,, and control signals. When and are both low, the TLC72 analog output, specified by the control line, responds to the activity on the DB0DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the signal or signal goes high, the data on the DB0DB7 inputs is latched until the and signals go low again. When is high, the data inputs are disabled regardless of the state of the signal. POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 PINCIPLES OF OPEATION The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of V. These devices can operate with any supply voltage in the range from V to V; however, input logic levels are not TTL compatible above V. 2 S 2 S2 2 S 2 S 2 FB DACA Data Latches and Drivers Figure. Simplified Functional Circuit for DACA FB I 2 IIkg COUT Figure 2. TLC72 Equivalent Circuit, DACA Latch Loaded With MODE SELECTION TABLE DACA L H X X L L H X L L X H Write Hold Hold Hold Hold Write Hold Hold L = low level, H = high level, X = don t care POST OFFICE BOX 0 DALLAS, TEXAS 72
APPLICATION INFOMATION TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant and 4-quadrant multiplication are shown in Figures and 4. Tables and 2 summarize input coding for unipolar and bipolar operation. VI(A) ±0 V (see Note A) 2 (see Note A) VDD 7 4 DB0 DB7 7 Input Buffer Latch DACA C (see Note B) VOA DACA / Control Logic Latch 4 (see Note A) C2 (see Note B) VOB ECOMMENDED TIM ESISTO VALUES, 2, 4 00 Ω 0 Ω VI(B) ±0 V (see Note A) NOTES: A., 2,, and 4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with digital input of 2. B. C and C2 phase compensation capacitors (0 pf to pf) are required when using high-speed amplifiers to prevent ringing or oscillation. Figure. Unipolar Operation (2-Quadrant Multiplication) POST OFFICE BOX 0 DALLAS, TEXAS 72 7
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 APPLICATION INFOMATION VI(A) ±0 V 20 kω (see Note B) (see Note A) 2 (see Note A) VDD 7 DB0 4 DB7 7 Input Buffer Latch DACA C (see Note C) A 7 0 kω (see Note B) 20 kω A2 VOA DACA/ Control Logic Latch (see Note A) 4 (see Note A) C2 (see Note C) A kω 9 0 kω (see Note B) 20 kω A4 kω VOB VI(B) ±0 V 0 20 kω (see Note B) NOTES: A., 2,, and 4 are used only if gain adjustment is required. See table in Figure for recommended values. Adjust for VOA = 0 V with code 0000000 in DACA latch. Adjust for VOB = 0 V with 0000000 in latch. B. Matching and tracking are essential for resistor pairs, 7, 9, and 0. C. C and C2 phase compensation capacitors (0 pf to pf) may be required if A and A are high-speed amplifiers. Figure 4. Bipolar Operation (4-Quadrant Operation) Table. Unipolar Binary Code DAC LATCH CONTENTS ANALOG OUTPUT MSB LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB = (2)VI VI (2/2) VI (29/2) VI (2/2) = Vi/2 VI (27/2) VI (/2) VI (0/2) = 0 Table 2. Bipolar (Offset Binary) Code DAC LATCH CONTENTS ANALOG OUTPUT MSB LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB = (27)VI VI (27/2) VI (/2) 0 V VI (/2) VI (27/2) VI (2/2) POST OFFICE BOX 0 DALLAS, TEXAS 72
microprocessor interface information APPLICATION INFOMATION TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 AA Address Bus CPU 0 Address Decode Logic A A TLC72 DB0 DB7 ALE Latch AD0 AD7 Data Bus NOTE A: A = decoded address for TLC72 DACA A = decoded address for TLC72 Figure. TLC72 Intel 0 Interface AA Address Bus CPU 00 VMA Address Decode Logic A A TLC72 DB0 φ2 DB7 AD0 AD7 Data Bus NOTE A: A = decoded address for TLC72 DACA A = decoded address for TLC72 Figure. TLC72 00 Interface POST OFFICE BOX 0 DALLAS, TEXAS 72 9
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 APPLICATION INFOMATION AA Address Bus CPU Z0-A IOQ Address Decode Logic A A TLC72 DB0 DB7 D0D7 Data Bus programmable window detector NOTE A: A = decoded address for TLC72 DACA A = decoded address for TLC72 Figure 7. TLC72 To Z-0A Interface The programmable window comparator shown in Figure determines if voltage applied to the DAC feedback resistors are within the limits programmed into the data latches of these devices. Input signal range depends on the reference and polarity, that is, the test input range is 0 to V ref. The DACA and data latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the output high. 0 POST OFFICE BOX 0 DALLAS, TEXAS 72
APPLICATION INFOMATION TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 Test Input 0 to Vref 4 DACA VDD 7 2 VCC kω Data Inputs 47 DB0 DB7 Vref TLC72 DACA / 20 PASS / FAIL Output 9 Figure. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester) digitally controlled signal attenuator Figure 9 shows a TLC72 configured as a two-channel programmable attenuator. Applications include stereo audio and telephone signal level control. Table shows input codes vs attenuation for a 0 to. db range. Attenuation db = 20 log0 D/2, D = digital input code VIA VDD 7 4 DACA 2 A Output DB0 DB7 47 Data Bus VOB A2 20 TLC72 DACA / 9 Figure 9. Digitally Controlled Dual Telephone Attenuator POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 APPLICATION INFOMATION ATTN (db) Table. Attenuation vs DACA, Code DAC INPUT CODE CODE IN DECIMAL ATTN (db) DAC INPUT CODE CODE IN DECIMAL 0 2.0 0 0 0 0 02 0. 0 0 0 242. 0 0 0 0 0 0 9.0 0 0 0 0 22 9.0 0 0 0 9. 0 0 2 9. 0 0 0 0 2.0 0 0 0 20 0.0 0 0 0 0 0 2. 0 0 0 0 0 0 92 0. 0 0 0 0 0 7.0 0 0 0.0 0 0 0 0 0 0 72. 0 0 0 7. 0 0 0 0 0 0 4.0 0 0 0 0 0 2 2.0 0 0 0 0 0 0 0 4 4. 0 0 0 0 0 2 2. 0 0 0.0 0 0 44.0 0 0 0 0 7. 0 0 0 0 0 0. 0 0 0 0 4.0 0 0 0 0 0 0 0 2 4.0 0 0 0 0. 0 0 0 2 4. 0 0 0 0 0 0 4 7.0 0 0 0 0 4.0 0 0 0 0 4 7. 0 0 0 0 0. 0 0 0 0 4 programmable state-variable filter This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass outputs, and is suitable for applications requiring microprocessor control of filter parameters. As shown in Figure 0, DACA and control the gain and Q of the filter while DACA2 and 2 control the cutoff frequency. Both halves of the DACA2 and 2 must track accurately in order for the cutoff-frequency equation to be true. With the TLC72, this is easy to achieve. f c 2 C The programmable range for the cutoff or center frequency is 0 to khz with a Q ranging from 0. to 4.. This defines the limits of the component values. 2 POST OFFICE BOX 0 DALLAS, TEXAS 72
APPLICATION INFOMATION TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 C 47 pf Data In VI 4 47 7 V DD DACA / DACA (S) DB0 DB7 TLC72 (F) DACA AND 2 20 9 A 0 kω Bandpass Out 0 kω 4 0 kω A2 High Pass Out C Data In 4 7 VDD DACA () 47 DB0 DB7 TLC72 DACA / (2) 2 20 9 000 pf A C2 000 pf A4 Low Pass Out DACA2 and 2 Circuit Equations: C = C2, = 2, 4 = Q F 4 fb() where: is the internal resistor connected between and fb G F S NOTES: A. Op-amps A, A2, A, and A4 are TL27. B. compensates for the op-amp gain-bandwidth limitations. C. DAC equivalent resistance equals 2 (DAC ladder resistance) DAC digital code Figure 0. Digitally Controlled State-Variable Filter POST OFFICE BOX 0 DALLAS, TEXAS 72
TLC72C, TLC72E, TLC72I DUAL -BIT MULTIPLYING SLAS02A JANUAY 97 EVISED MACH 99 voltage-mode operation APPLICATION INFOMATION It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure is an example of a current multiplying D/A, that operates in the voltage mode. EF (Analog Output Voltage) 2 2 2 2 0 Out (Fixed Input Voltage) Figure. Voltage-Mode Operation The following equation shows the relationship between the fixed input voltage and the analog output voltage: V O = V I (D/2) where V O = analog output voltage V I = fixed input voltage D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PAAMETE TEST CONDITIONS MIN MAX UNIT Linearity error at or VDD = V, or at 2. V, TA = 2 C LSB 4 POST OFFICE BOX 0 DALLAS, TEXAS 72
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