EVALUATION KIT AVAILABLE SUPER CHARGE PUMP DC-TO-DC FEATURES Oscillator boost from khz to khz Converts V Logic Supply to ±V System Wide Input Voltage Range....V to V Efficient Voltage Conversion... 99.9% Excellent Power Efficiency... 9% Low Power Supply... µa @ V IN Low Cost and Easy to Use Only Two External Capacitors Required Available in Small Outline (SOIC) Package Improved ESD Protection... Up to kv No External Diode Required for High Voltage Operation ORDERING INFORMATION Temperature Part No. Package Range COA -Pin SOIC C to C CPA -Pin Plastic DIP C to C EJA -Pin CerDIP C to C EOA -Pin SOIC C to C EPA -Pin Plastic DIP C to C MJA -Pin CerDIP C to C TCEV Evaluation Kit for Charge Pump Family GENERAL DESCRIPTION The is a pin-compatible upgrade to the Industry standard TC charge pump voltage converter. It converts a.v to V input to a corresponding -.V to -V output using only two low-cost capacitors, eliminating inductors and their associated cost, size and EMI. Added features include an extended supply range to V, and a frequency boost pin for higher operating frequency, allowing the use of smaller external capacitors. The on-board oscillator operates at a nominal frequency of khz. Frequency is increased to khz when pin is connected to V. Operation below khz (for lower supply current applications) is possible by connecting an external capacitor from OSC to ground (with pin open). The is available in both -pin DIP and -pin small outline (SOIC) packages in commercial and extended temperature ranges. PIN CONFIGURATION (DIP and SOIC) Boost CAP GND CAP CPA EJA EPA V OSC LOW VOLTAGE (LV) V OUT Boost CAP GND CAP COA EOA V OSC LOW VOLTAGE (LV) V OUT FUNCTIONAL BLOCK DIAGRAM V CAP BOOST OSC RC OSCILLATOR VOLTAGE LEVEL TRANSLATOR CAP LV V OUT INTERNAL VOLTAGE REGULATOR LOGIC NETWORK GND - 9//9 TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
ABSOLUTE MAXIMUM RATINGS* Supply Voltage... V LV, Boost, OSC Inputs Voltage (Note )....V to (V.V) for V <.V (V.V) to (V.V) for V >.V Current Into LV (Note )... µa for V >.V Output Short Duration (V SUPPLY.V)... Continuous Power Dissipation (T A C) (Note ) CerDIP...mW Plastic DIP...mW SOIC...mW Operating Temperature Range C Suffix... C to C E Suffix... C to C M Suffix... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: T A = C, V = V, C OSC =, Test Circuit (Figure ), unless otherwise indicated. Symbol Parameter Test Conditions Min Typ Max Unit I Supply Current R L = µa (Boost pin OPEN or GND) C T A C C T A C C T A C I Supply Current C T A C µa (Boost pin = V ) C T A C C T A C V Supply Voltage Range, High Min T H A Max, V R L = kω, LV Open V L Supply Voltage Range, Low Min T A Max,.. V R L = kω, LV to GND R OUT Output Source Resistance I OUT = ma Ω I OUT = ma, C T A C I OUT = ma, C T A C I OUT = ma, C T A C V = V, I OUT = ma, LV to GND C T A C Ω C T A C F OSC Oscillator Frequency Pin open; Pin open or GND khz Boost Pin = V P EFF Power Efficiency R L = kω; Boost Pin Open 9 9 % T MIN T A T MAX ; Boost Pin Open 9 9 Boost Pin = V V OUT E FF Voltage Conversion Efficiency R L = 99 99.9 % Z OSC Oscillator Impedance V = V MΩ V = V kω NOTES:. Connecting any input terminal to voltages greater than V or less than GND may cause destructive latch-up. It is recommended that no inputs from sources operating from external supplies be applied prior to "power up" of the.. Derate linearly above C by.mw/ C.
Detailed Description The contains all the necessary circuitry to implement a voltage inverter, with the exception of two external capacitors, which may be inexpensive µf polarized electrolytic capacitors. Operation is best understood by considering Figure, which shows an idealized voltage inverter. Capacitor C is charged to a voltage V for the half cycle when switches S and S are closed. (Note: Switches S and S are open during this half cycle.) During the second half cycle of operation, switches S and S are closed, with S and S open, thereby shifting capacitor C negatively by V volts. Charge is then transferred from C negatively by V volts. Charge is then transferred from C to C, such that the voltage on C is exactly V, assuming ideal switches and no load on C. The four switches in Figure are MOS power switches; S is a P-channel device, and S, S and S are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S and S must always remain reverse-biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit start-up, and under output short circuit conditions (V OUT = V ), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this will result in high power losses and probable device latch-up. This problem is eliminated in the by a logic network which senses the output voltage (V OUT ) together with the level translators, and switches the substrates of S and S to the correct level to maintain necessary reverse bias. C µf V Figure. Test Circuit C OSC * I L C µf R L NOTE: For large values of C OSC (>pf), the values of C and C should be increased to µf. I S V (V) V O V GND S S S C S C V OUT = V IN Figure. Idealized Charge Pump Inverter The voltage regulator portion of the is an integral part of the anti-latch-up circuitry. Its inherent voltage drop can, however, degrade operation at low voltages. To improve low-voltage operation, the LV pin should be connected to GND, disabling the regulator. For supply voltages greater than.v, the LV terminal must be left open to ensure latch-up-proof operation and prevent device damage. Theoretical Power Efficiency Considerations In theory, a capacitive charge pump can approach % efficiency if certain conditions are met: () The drive circuitry consumes minimal power. () The output switches have extremely low ON resistance and virtually no offset. () The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The approaches these conditions for negative voltage multiplication if large values of C and C are used. Energy is lost only in the transfer of charge between capacitors if a change in voltage occurs. The energy lost is defined by: E = / C (V V ) V and V are the voltages on C during the pump and transfer cycles. If the impedances of C and C are relatively high at the pump frequency (refer to Figure ) compared to the value of R L, there will be a substantial difference in voltages V and V. Therefore, it is desirable not only to make C as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C in order to achieve maximum efficiency of operation.
Dos and Don'ts Do not exceed maximum supply voltages. Do not connect the LV terminal to GND for supply voltages greater than.v. Do not short circuit the output to V supply for voltages above.v for extended periods; however, transient conditions including start-up are okay. When using polarized capacitors in the inverting mode, the terminal of C must be connected to pin of the and the terminal of C must be connected to GND. Simple Negative Voltage Converter Figure shows typical connections to provide a negative supply where a positive supply is available. A similar scheme may be employed for supply voltages anywhere in the operating range of.v to V, keeping in mind that pin (LV) is tied to the supply negative (GND) only for supply voltages below.v. V The output characteristics of the circuit in Figure are those of a nearly ideal voltage source in series with Ω. Thus, for a load current of ma and a supply voltage of V, the output voltage would be.v. The dynamic output impedance of the is due, primarily, to capacitive reactance of the charge transfer capacitor (C ). Since this capacitor is connected to the output for only / of the cycle, the equation is: X C = =.Ω, πf C where f = khz and C = µf. Paralleling Devices Any number of voltage converters may be paralleled to reduce output resistance (Figure ). The reservoir capacitor, C, serves all devices, while each device requires its own pump capacitor, C. The resultant output resistance would be approximately: R OUT = R OUT (of ) n (number of devices) V OUT * C C µf µf *NOTES: Figure. Simple Negative Converter V C "" C R L "n" C Figure. Paralleling Devices Lowers Output Impedance
V µf "" µf "n" V OUT * *NOTES:. V OUT = n(v ) for.v V V µf µf Figure. Increased Output Voltage by Cascading Devices Cascading Devices The may be cascaded as shown (Figure ) to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is devices for light loads. The output voltage is defined by: V OUT = n (V IN ) where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual R OUT values. Changing the Oscillator Frequency It may be desirable in some applications (due to noise or other considerations) to increase the oscillator frequency. Pin, frequency boost pin may be connected to V to increase oscillator frequency to khz from a nominal of khz for an input supply voltage of. volts. The oscillator may also be synchronized to an external clock as shown in Figure. In order to prevent possible device latch-up, a kω resistor must be used in series with the clock output. In a µf V kω V µf CMOS GATE V OUT situation where the designer has generated the external clock frequency using TTL logic, the addition of a kω pullup resistor to V supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be ¹ ₂ of the clock frequency. Output transitions occur on the positive-going edge of the clock. It is also possible to increase the conversion efficiency of the at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved by connecting an additional capacitor, C OSC, as shown in Figure. Lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C ) and the reservoir (C ) capacitors. To overcome this, increase the values of C and C by the same factor that the frequency has been reduced. For example, the addition of a pf capacitor between pin (OSC) and pin (V ) will lower the oscillator frequency to khz from its nominal frequency of khz (a multiple of ), and necessitate a corresponding increase in the values of C and C (from µf to µf). Positive Voltage Multiplication The may be employed to achieve positive voltage multiplication using the circuit shown in Figure. In this application, the pump inverter switches of the are used to charge C to a voltage level of V V F (where V is the supply voltage and V F is the forward voltage drop of diode D ). On the transfer cycle, the voltage on C plus the supply voltage (V ) is applied through diode D to capacitor C. The voltage thus created on C becomes (V ) (V F ), or twice the supply voltage minus the combined forward voltage drops of diodes D and D. The source impedance of the output (V OUT ) will depend on the output current, but for V = V and an output current of ma, it will be approximately Ω. Figure. External Clocking
C Figure. Lowering Oscillator Frequency Combined Negative Voltage Conversion and Positive Supply Multiplication Figure 9 combines the functions shown in Figures and to provide negative voltage conversion and positive voltage multiplication simultaneously. This approach would be, for example, suitable for generating 9V and V from an existing V supply. In this instance, capacitors C and C perform the pump and reservoir functions, respectively, for the generation of the negative voltage, while capacitors C and C are pump and reservoir, respectively, for the multiplied positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin of the device. Efficient Positive Voltage Multiplication/Conversion Since the switches that allow the charge pumping operation are bidirectional, the charge transfer can be performed backwards as easily as forwards. Figure shows a transforming V to V (or V to V, etc.). The only problem here is that the internal clock and switchdrive section will not operate until some positive voltage has been generated. An initial inefficient pump, as shown in Figure 9, could be used to start this circuit up, after which it C V C OSC V OUT will bypass the other (D and D in Figure 9 would never turn on), or else the diode and resistor shown dotted in Figure can be used to "force" the internal regulator on. Voltage Splitting The same bidirectional characteristics used in Figure can also be used to split a higher supply in half, as shown in Figure. The combined load will be evenly shared between the two sides. Once again, a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure, V can be converted (via.v and.v) to a nominal V, though with rather high series resistance (~Ω). C C V D V OUT = V V OUT = ( V ) ( V F ) Figure 9. Combined Negative Converter and Positive Multiplier Negative Voltage Generation for Display ADCs The TC is designed to work from a 9V battery. With a fixed power supply system, the TC will perform conversions with input signal referenced to power supply ground. D C C V D D C V OUT = ( V ) ( V F ) C Negative Supply Generation for ¹ ₂ Digit Data Acquisition System The TC is a ¹ ₂ digit ADC operating from ±V supplies. The provides an inexpensive V source. (See AN and AN for TC interface details and software routines.) Figure. Positive Voltage Multiplier
V OUT = V V C µf MΩ µf R L V = OUT V V R L µf µf kω MΩ V INPUT µf V Figure. Positive Voltage Multiplier Figure. Splitting a Supply in Half TYPICAL CHARACTERISTICS Unloaded Osc Freq vs. Temperature Unloaded Osc Freq vs. Temperature with Boost Pin = V IN I DD (µa) OSCILLATOR FREQUENCY (khz) V IN = V V IN = V - - Supply Current vs. Temperature (with Boost Pin = V IN ) V IN = V V IN = V - - VOLTAGE CONVERSION EFFICIENCY (%) OSCILLATOR FREQUENCY (khz) V IN = V V IN = V - -... 99. 99. 9. Voltage Conversion Without Load K Load T A = C 9. 9 INPUT VOLTAGE V IN (V)
TYPICAL CHARACTERISTICS (Cont.) Output Source Resistance vs. Supply Voltage Output Source Resistance vs. Temperature OUTPUT SOURCE RESISTANCE (Ω) I OUT = ma T A = C........ 9... SUPPLY VOLTAGE (V) OUTPUT SOURCE RESISTANCE (Ω) V IN =.V V IN =.V - - OUTPUT VOLTAGE VOUT (V) Output Voltage vs. Output Current - - - - - - 9 OUTPUT CURRENT (ma) POWER EFFICIENCY (%) 9 Power Conversion Efficiency vs. Load Boost Pin = Open Boost Pin = V....... 9........... LOAD CURRENT (ma) SUPPLY CURRENT I DD (µa) Supply Current vs. Temperature V IN =.V V IN =.V - -
TYPICAL CHARACTERISTICS (Cont.) Supply Current vs. Temperature SUPPLY CURRENT I DD (µa) V IN =.V V IN =.V - - PACKAGE DIMENSIONS -Pin Plastic DIP PIN. (.). (.). (.). (.). (.). (.). (.). (.). (.).9 (.). (.). (.). (.). (.9). (.). (.). (.). (.) MIN.. (.9).9 (.9). (.). (.). (.). (.) Dimensions: inches (mm) 9
PACKAGE DIMENSIONS (Cont.) -Pin CerDIP. (.9).9 (.9) PIN. (.). (.). (.) MAX.. (.) MIN.. (.). (9.). (.).9 (.). (.). (.). (.). (.). (.). (.). (.) MIN.. (.). (.) MIN.. (.). (.). (.). (.). (.). (.) -Pin Plastic SOIC PIN. (.99). (.). (.). (.9). (.) TYP..9 (.).9 (.). (.). (.). (.). (.).9 (.). (.) MAX.. (.). (.). (.). (.) Dimensions: inches (mm)
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