Bi-Dirctional N-Channl -V (D-S) MOSFET Si9EDB PRODUCT SUMMARY V SS (V) R SS(on) (Ω) I SS (A). at V GS =.5 V 7.6 at V GS = 3.7 V 6..3 at V GS =.5 V 5.. at V GS =. V 5.5 FEATURES TrnchFET Powr MOSFET Ultra-Low R SS(on) ESD Protctd: V MICRO FOOT Chipscal Packaging Rducs Footprint Ara Profil (.6 mm) and On-Rsistanc Pr Footprint Ara RoHS COMPLIANT Bump Sid Viw MICRO FOOT Backsid Viw APPLICATIONS Battry Protction Circuit - - Cll Li+/LiP Battry Pack for Portabl Dvics 7 6 Pin Idntifir S 5 G 9 G 9E xxx Dvic Marking: 9E = P/N Cod xxx = Dat/Lot Tracability Cod G kω kω S 3 S G S S Ordring Information: Si9EDB-T-E (Lad (Pb)-fr) N-Channl ABSOLUTE MAXIMUM RATINGS T A = 5 C, unlss othrwis notd Paramtr Symbol 5 s Stady Stat Unit Sourc- Sourc Voltag V SS V Gat-Sourc Voltag V GS ± Continuous Sourc- Sourc Currnt (T J = 5 C) a T A = 5 C 7 5. I SS T A = 5 C 5. 3.9 A Pulsd Sourc- Sourc Currnt I SM 5 T A = 5 C Maximum Powr Dissipation a. P D W T A = 5 C.9.5 Oprating Junction and Storag Tmpratur Rang T J, T stg - 55 to 5 C Packag Rflow Conditions c IR/Convction 6 THERMAL RESISTANCE RATINGS Paramtr Symbol Typical Maximum Unit Maximum Junction-to-Ambint a t 5 s 55 7 R thja Stady Stat 95 C/W Maximum Junction-to-Foot b Stady Stat R thjf 5 Nots: a. Surfac Mountd on " x " FR board. b. Th foot is dfind as th top surfac of th packag. c. Rfr to IPC/JEDEC (J-STD-C), no manual or hand soldring. S-9-Rv. G, -Sp-
Si9EDB SPECIFICATIONS T J = 5 C, unlss othrwis notd Paramtr Symbol Tst Conditions Min. Typ. Max. Unit Static Gat Thrshold Voltag V GS(th) V SS = V GS, I D =. ma.5. V V SS = V, V GS = ±.5 V ± µa Gat-Body Lakag I GSS V SS = V, V GS = ± V ± ma V SS = V, V GS = V Zro Gat Voltag Drain Currnt I SS V SS = V, V GS = V, T J = 5 C 5 µa On-Stat Drain Currnt a I S(on) V SS = 5 V, V GS =.5 V 5 A V GS =.5 V, I SS = A.. Sourc- Sourc On Stat Rsistanc a R SS(on) V GS = 3.7 V, I SS = A..6 V GS =.5 V, I SS = A.6.3 Ω V GS =. V, I SS = A.3. Forward Transconductanc a g fs V SS = V, I SS = A 3 S Dynamic b Turn-On Dlay Tim t d(on) 3 5 Ris Tim t r V SS = V, R L = Ω.5 7 Turn-Off Dlay Tim t d(off) I SS A, V GEN =.5 V, R g = 6 Ω 55 5 µs Fall Tim t f 5 5 Nots: a. Puls tst; puls width 3 µs, duty cycl %. b. Guarantd by dsign, not subjct to production tsting. Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of th spcifications is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. TYPICAL CHARACTERISTIC5 C, unlss othrwis notd - Gat Currnt (ma) I GSS 6 I GSS at 5 C (ma) I GSS - Gat Currnt ( µa) T J = 5 C T J = 5 C 3 6 9 5 Gat-Currnt vs. Gat-Sourc Voltag. 3 6 9 5 Gat Currnt vs. Gat-Sourc Voltag S-9-Rv. G, -Sp-
Si9EDB TYPICAL CHARACTERISTIC5 C, unlss othrwis notd V GS = 5 thru.5 V - Drain Currnt (A) I D 6 V - Drain Currnt (A) I D 6 T C = 5 C 5 C - 55 C 3 V DS - Drain-to-Sourc Voltag (V) Output Charactristics....6... Transfr Charactristics.5.6 - On-Rsistanc (Ω) R DS(on)..3.. V GS =. V V GS =.5 V V GS = 3.7 V V GS =.5 V R DS(on) - On-Rsistanc (Normalizd).... V GS =.5 V I SS = A. 6 I D - Drain Currnt (A) On-Rsistanc vs. Drain Currnt.6-5 - 5 5 5 75 5 5 T J - Junction Tmpratur ( C) On-Rsistanc vs. Junction Tmpratur. - On-Rsistanc (Ω) R DS(on)..6.. I SS = A I SS = 5 A Varianc (V) V GS(th). - -. -.3 I SS =. ma. 3 5 On-Rsistanc vs. Gat-to-Sourc Voltag -. - 5-5 5 5 75 5 5 T J - Tmpratur ( C) Thrshold Voltag S-9-Rv. G, -Sp- 3
Si9EDB TYPICAL CHARACTERISTIC5 C, unlss othrwis notd 3 5 Powr (W) 5 5. Tim (s) Singl Puls Powr, Junction-to-Ambint Normalizd Effctiv Transint Thrmal Impdanc Duty Cycl =.5. Nots: P DM.5 t t t.. Duty Cycl, D = t. Pr Unit Bas = R thja = 95 C/W 3. T JM - T A = P DM Z (t) thja Singl Puls. Surfac Mountd. - - 3 - - 6 Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Ambint Normalizd Effctiv Transint Thrmal Impdanc Duty Cycl =.5..5.. - Singl Puls - 3 - - Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Foot S-9-Rv. G, -Sp-
Si9EDB PACKAGE OUTLINE MICRO FOOT: -BUMP ( x 5,. mm PITCH) x.3 ~.3 Not 3 Soldr Mask ~. A A A Silicon Bump Not Rcommndd Land b Diamrtr 9E xxx E Mark on Backsid of Di S D Nots (Unlss Othrwis Spcifid):. Lasr mark on th silicon di back, coatd with a thin mtal.. Bumps ar 95.5Sn/3.Ag/.7Cu. 3. Non-soldr mask dfind coppr landing pad. Dim. Millimtrs a Inchs Min. Max. Min. Max. A.6.65.36.56 A.6.9. A.3.36.3. b.37..6.6 D.5.6 59 59 E.9..7.77.75.5.95.335 S.3.5.69.77.5.6..36 Nots: a. Us millimtrs as th primary masurmnt. maintains worldwid manufacturing capability. Products may b manufacturd at on of svral qualifid locations. Rliability data for Silicon Tchnology and Packag Rliability rprsnt a composit of all qualifid locations. For rlatd documnts such as packag/tap drawings, part marking, and rliability data, s http:///ppg?73. S-9-Rv. G, -Sp- 5
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