Study of Threshold Gate and CMOS Logic Style Based Full Adders Circuits

IEEE SPONSORED 3rd INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS 2016) Study of Threshold Gate and CMOS Logic Style Based Full Adders Circuits Raushan Kumar Department of ECE NIT Arunachal Pradesh Yupia, India raushan212640@gmail.com Sahadev Roy Department of ECE NIT Arunachal Pradesh Yupia, India sahadevroy@gmail.com Chandan Tilak Bhunia Department of CSE NIT Arunachal Pradesh Yupia, India Abstract In this review paper different design techniques of 1-bit full adder are deliberate using linear threshold logic gates (LTLG). The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Full adder circuits basically implemented using resonant tunneling diode (RTD) based threshold gates, SET based threshold gate and 180nm COMS transistors. Full adders may be realized in various ways like RTD, single electron tunneling (SET) TG, The Static Energy Recovery Full adder (SERF), 14T, pseudo-nmos, MULTIPLEXER-BASED FULL ADDER (MBA-12T), 8T, Inverter-based full-adder with pass transistors, Conventional CMOS (C-CMOS), 20T, 10Twith 4T-XNOR, 6T, 16T, 9T, Double gate MOSFET and hybrid 1-bit full adder full adders etc. Keywords LTLG, PDP, SET TG full adder, CMOS full adder, Power dissipation, low power, the logic circuit. I. INTRODUCTION The addition is a fundamental arithmetic operation largely used in processor and different VLSI systems. The arithmetic circuits are one of the important functional blocks for all types ALUs, comparator, parity encoder, code converter and digital signal processing (DSP). One bit full adder able to perform all types of arithmetic operations. There are several implementation techniques of full adder those covered all types applications specific systems. In modern years, low power circuit design has become one of the key research areas [1]. On the verge of the 21st century, power consumption in the electronic device is becoming a major challenge like optimization of several parameters like number of TG, a number of CMOS transistor, power dissipation, power delay product (PDP), average power, and time delay. Time delay depends on length and width of the transistor and power dissipation depend on size [2], node capacitance, wiring and circuit complexity and number of the transistor also depends on switching activity etc. [3]. The rest of paper is organized by flowing sections: (1) Basic operation of the full adder, (2) Different types of logic style of the full adder, (3) Review of 1-bit full adder circuits using statics CMOS logic styles and threshold logic style, (4) Comparison of delay, average power, and PDP. II. BASIC OPERATIONS The full adder consists of three input ports and two output port. That outputs are sum and carry-out, of the full adder being produced simultaneously. The first Process of addition is adding two binary digits and Carry is generated only when two bits are 1. Half adder is based on two binary inputs and give two binary output sum and carry. For addition of a number of bits that why required a number of input variable adder then May 2, 1967, Berlind Richard M design a three input variable full adder circuit. Full adder level design of full adder is shows in the Fig.1. Boolean expression of sum and carry can be written as below, III. S =A B C (1) C =AB+BC+AC (2) Figure 1. Gate level design of full adder. FULL ADDER CIRCUITS LOGIC STYLE There mainly two category of logic style first one is linear threshold gate based full adder and the second one is CMOS-based circuit diagram. 1. LINEAR THRESHOLD GATE BASED FULL ADDER 978-1-4673-7832-1/16/$31.00 2016 IEEE 173

A. SET Based LTGL Full Adder This type of adder is work in SET based TG logic. [4]. In this circuit TG is replacing as single electron transistor so that single SET can design a single TG.if design a full adder circuit that can require two SET. Working of linear threshold gate, TG it is a device which are able to compute the Boolean function it given that threshold gate, TG it is a device which are able to compute the Boolean function it given that, (3) Where Xi is then Boolean inputs and Wi are the corresponding n integer weights. The linear threshold gate performs a comparison between the weighted sum of the inputs and the threshold value T. If the weighted sum of inputs is greater than or equal to the threshold, the gate logic 1. Otherwise, the output is logic 0. Figure 2. Schematic diagram of many input LTG. LTG circuits are work on the basis of tunneling phenomena and critical voltage. If the critical voltages V C are tunneling and which also act as the intrinsic threshold level. If the voltage across the junction is larger than V C an electron will tunnel through the junction in the opposite direction, resulting output is logic 1.The biasing voltage V B, weighted by the capacitor C B, is used to adjust the gate threshold to the desired value T. The input signal V T and cross pounding weight sum CT is added to the voltage across the tunnel junction and another input signal V X and crosses pounding weight sum C X subtract from the voltage across tunnel junction as Fig. 2. Using this approach, we can design a threshold gate [5]. Full adder threshold gate shows below in Fig. 3 and output truth table sum and carry is written as Table 1. Advantage of the circuit is small in size and less power because less number of threshold gate are used. Input (A B C) Figure 3. Realization of TG full adder. TABLE I. Weight sum (A+B+C) FULL ADDER OUTPUT Carry (COUT) Weight sum (A+B+C-2COUT) Sum (S) 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 1 2 1 0 0 1 0 0 1 0 1 1 1 0 1 2 1 0 0 1 1 0 2 1 0 0 1 1 1 3 1 1 1 B. TLFA based on RTD Resonant tunneling diodes (RTDs) are very fast nonlinear circuit elements which exhibit a negative differential resistance (NDR). RTD working functions based on quantum transport phenomena [6]. Circuit applications of RTDs are mainly based on the monostable-bistable logic element. RTD tunneling phenomena or inverting phenomena exhibit based on load RTD and derive RTD. The two input RTD structures implementing Multi- Threshold Threshold Gates (MTTGs) show in Fig. 4. Figure 4. Structure of two input MTTG. In Fig. 5, W k is positive weight and W L is a negative weight that are written in vector form like that [Wk, W L; 174

T].The areas A 1 and A 2 are determinate by the threshold to be implemented, and the areas Au and B are selected according to the technology. The above circuit working principle is input variable X i; (i=1 n) one binary output y, and for which there is a set of (n + k) real numbers: thresholds Ti, (i= 1 n) and weights W 1, W 2 W n such that input out relation define as Y = 1 if f With TJ+1 > TJ, (J= 1 K/2) the output y equal to zero. The circuit diagram of RTD and threshold gate representation full adder has shown in Fig. 6. (4) Figure 7. Realization of Typical SERF Adder. Figure 5. Realization of RTD full adder. B. 14-Transistor (14t) Full Adder This full adder circuit is designed by 14-CMOS Transistor with 3T XOR that why 14T full-adder uses more than one logic style for their implementation called hybrid logic design style [8]. The advantage of this circuit less transistor count and small area and disadvantage of this full-adder suffer from the lack of driving capabilities in fan- out the situation and their performances degrade intensely when they are cascaded. It must be stated that this full-adder cannot work properly when the supply voltage is less than 1.8 V. The circuit diagram is shown in Fig. 8. Figure 6. Realization of TG full adders. 2. CMOS BASED ON FULL ADDER A. Static Energy Recovery Full Adder (SERF) This adder circuit is designed by 10 CMOS transistor with 4T XOR. In this design called low power adder because it does not contain a direct path to the ground and can re-apply the load charge to the control gate that why called Static energy recovery full adder [7]. The design procedure consists of three input and gives two output sum and carry. The advantage of this circuit is low power consumption small area and less PDP compare to pass transistor logic (PTL) circuit design show in Fig.7. Figure 8. 14T full adder circuit diagram. D. Pseudo NMOS Full Adders The pseudo n-mos full adders designed 18 transistors by radioed logic. In this logic the CMOS pull up circuit is replace by single p-mos transistor with its gate is grounded. So that p-mos is always on states because of Vdd power supply. When the nmos is turned on a direct path between supply and ground exists and static power will be drawn [9].The Advantage of the pseudo n-mos logic it perform high speed, small size and less delay compare to C-CMOS transistor and disadvantage is that it has reduced output swipe, increased power consumption of pull up transistor 175

and more disposed to noise [10]. The circuit diagram shows in Fig. 9. Figure 9. Realization of Pseudo nmos full adder. E. Multiplexer-Based Full Adder (MBA-12T) This full adder circuit is constructed by using 6 identical multiplexers and a total number of 12 CMOS transistors. MBA-12T adder shows charge recycling abilities and has very low short-circuited current [11]. This circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Advantage of MBA-12T consumes 26% less power than conventional 28-transistor CMOS added. In addition, MBA- 12T consumes 23% less power than the most power efficient 10-transistor. Circuit diagram shows in Fig. 10. Figure 11. Full adder realization using 8 transistors (8T). G. Inverter-Based Full-Adder With Transmission Gates In this full adders, the circuit is designed by the majority number of static CMOS inverter type. The circuit consists of 16 CMOS transistor according to this full adder. The carry output is implemented with a MAJORITY number of NOT gate and sum output is the reversed process of carry output [13]. Few transistor counts, the ability to work at ultra-lowpower supply voltages, and finally elimination of short circuit current and whole circuit is designed by 90nm technology [14]. The circuit diagram shows in Fig. 12. Figure 12. Inverter-based full-adder with transmission gates. Figure 10. Realization of MBA-12T 1 bit full adders. F. 8- Transiator (8-T) Full Adder In this full adder design by 8T CMOS with the 3T EXOR circuit. The design of full adder consist of three input and two output sum and carry outputs gives only two stage delays [12]. Performance has been considered using 0.15µm technology. Advantages of this circuit are less transistor count and small area compares to 10T full adder circuit. The circuit diagram shows in Fig. 11. H. Convenational CMOS Full Adder This adder s circuit is designed by 28 transistors based on systematic C-CMOS configuration with pmos pull-up and nmos pull-down transistors. The design procedure consists of three input and two output sum and carry. The advantage of this circuit it operates low power and high noise margin due to complementary transistor pair. Disadvantages of the MOS full adder circuit it takes large area due to a number of the transistor are used and large delay also take more power in output stage [15]. The circuit diagram shows in Fig.13. 176

Figure 15. Full adder realization using 10 transistors (10T). Figure 13. 28T CMOS full adder circuit diagrams. I. 20T Full Adder This full adder circuit is designed by 20 transistors and Buffering inverters are inserted before the sum and carry outputs to enhance the driving ability. Working function based on 20T full adders based on transmission/pass transistors logic [16].The advantage of this circuit to high driving ability and low power consumption. This circuit is simulated by 180um technology show in Fig.14. K. 6 CMOS Transitor Full Adder In this full adder circuit is implemented by 6 CMOS transistor based on two transistors XOR (2T-XOR) logic. Compare to other full adder circuit XOR logic is design by 3T and 4T CMOS XOR [18]. According to this design, the circuit is consists of three inputs and give two output sum and carry. The advantage of the circuit less transistor count, low power, high speed and small area compare to another circuit. Show in Fig. 16.. Figure 14. Full adder realization using 20 transistors (20T). J. 10T Full Adder This full adder circuit is designed by 10 CMOS transistors. It uses two XNOR gates and it will be gives two output sum and carry [17]. Advantages of this full adder circuit it consumes less power, less internal capacitance, and less area. There is very less static power loss or dynamic power loss. A disadvantage of it is more expensive show in Fig.15. Figure 16. Full adder realization using 6 transistors (6T). L. 9 Transistor (9T) Full Adder This full adder circuit is designed by 9 CMOS transistor with 3T XOR and 4T XOR, basically this full adder used in Wallace Tree multiplier full adders [19].The advantage of this full adder reducing the transistor count decreases the power consumption of a circuit and disadvantage of this full adder has stunned the voltage degradation occurring due to threshold drop. This problem has overcome by increasing the aspect ratio (W/L) by making the length as constant and increasing the width. The 9T Full Adder is designed using 0.12µm technology shown in Fig.17. [20]. 177

20T 0.18 21.617 0.25 5.4000 10T 0.18 14.345 0.133 1.9021 6T 0.35 0.2350 NA NA 9T 0.12 0.2950 NA NA Hybrid 0.18 1.1766 0.091 0.1074 a. Data not available/not applicable IV. CONCLUSION Figure 17. Realization of 9T full adder circuit diagram. M. Hybrid 1-bit Full Adder This full adder circuit is designed by 16 CMOS transistor all transistors are represented the separate block. The full adder is consisting of three blocks. Block 1 and block 2 are the XNOR modules that generate the sum signal (SUM) and Block 3 generates the output carry signal (CARRY) [21]. Each block is designed individually such that the entire adder circuit is optimized of power, delay, and area. The hybrid 1- bit full adder circuit is simulated by both 180nm and 90nm technology show in Fig.18. TABLE II. Figure 18. Typical sturucture of hybrid1-bit full adder. Design name COMPARISON OF DIFFERENT FULL ADDER DESIGN STYLE Technology (µm) Average power (µw) Delay (ns) PDP (f j) SET NA 0.0021 0.100 0.0021 SERF-10T 0.18 1.1826 1.057 1.2500 14T 0.18 3.3297 0.338 1.1284 Pseudo NMOS 0.18 0.2970 0.182 0.0540 MBA-12T 0.35 4.6132 0.217 0.9987 8T 0.15 0.3610 0.001 0.0009 IBFA 0.18 1.4739 0.200 0.2951 CMOS 0.18 1.5799 0.127 0.2005 The performance analysis of several full adders drawn in table-2 shows different adders with different parameter values and different technology, no single adder have less delay, power PDP and size. thus, there exist tradeoff between these parameters. the results are helpful in selection of an adder according to desired result and application. REFERENCE [1] S. Roy and C. T. Bhunia, On Synthesis of Combinational Logic Circuits, International Journal of Computer Applications, vol. 127, no 1, pp. 21-26, 2015. [2] S. Roy and C. T. Bhunia, Constraints Analysis for Minimization of Multiple Inputs Logic Programming, in Proc. of International Conference on Signal and Speech Processing (ICSSP-14), Elsevier, pp. 61-64, 2014. [3] S. Roy and C. T. Bhunia, Minimization algorithm for multiple input to two input variables, in Proc. Int. Conference on Control, Instrumentation Energy and Communication, (CIEC14), IEEE, pp. 555-557, 2014. [4] A. N. Korotkov, Single-Electron Logic and Memory Devices, International Journal of Electronics, vol. 86, pp. 511-547, May 1999. [5] P. Mazumdar, and S. Kulkarni, Digital Circuit Applications of Resonant Tunneling Devices, Proceedings of the IEEE, Vol. 86, April 1998. [6] D. R. Haring, Multi-Threshold Threshold Elements, IEEE Trans. on Electronic Computers, Vol. 15, pp. 45-65, February 1966. [7] Shalem, R. John, E. John, and L.K, A Novel Low Power Energy Recovery Full Adder Cell, Proc. 9th Great Lakes Symp. on VLSI, 1999, pp.380-383. [8] M. Vesterbacka, A 14-transistor CMOS full adder with full voltageswing nodes, in Proc. IEEE Workshop Signal Process. Syst. (SiPS),Taipei, Taiwan, 1999, pp. 713 722. [9] Shams, M. Ahmed and M. Bayoumi, A novel high-performance CMOS 1-bit full-adder cell, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on vol. 47, pp. 478-481, May 2000. [10] A. A. Khatibzadeh and K. Raahemifar, A study and comparision of full adder cells based on the standard CMOS logic, IEEE Trans.CCECE, Niagara Falls, 2004, pp. 2139-2142. [11] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha and J. G. Chung, A novel multiplexer-based low-power full adder. Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.51, pp.345-348, July 2004. [12] S. R. Chowdhury, A. Banerjee, A. Roy and H. Saha, A high speed 8 transistor full adder design using novel 3 transistor XOR gates, International Journal of Electronics, Circuits and Systems, vol. 4, pp. 217-223,October 2008. [13] K. Navi, V. Foroutan, M. R. Azghadi, M. Maeen, M. Ebrahimpour, M. Kaveh, and O. Kavehei, A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter, Microelectronics Journal, vol. 40, pp. 1441-1448, October 2009. [14] K. Navi, M. Maeen, V. Foroutan, S.Timarchi, and O. Kavehei, A novel low-power full-adder cell for low voltage, VLSI J. Integr., vol. 42, pp. 457 467, Septmber 2009. 178

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