9-047; Rev. 4; /05 Microprocessor and Nonvolatile General Description The microprocessor (µp) supervisory circuits provide the most functions for power-supply and watchdog monitoring in systems without battery backup. Built-in features include the following: µp reset: Assertion of and outputs during power-up, power-down, and brownout conditions. is guaranteed valid for down to. Manual-reset input. Two-stage power-fail warning: A separate low-line comparator compares to a preset threshold 20m above the reset threshold; the low-line and reset thresholds can be programmed externally. Watchdog fault output: Assertion of WDO if the watchdog input is not toggled within a preset timeout period. Pulsed watchdog output: Advance warning of impending WDO assertion from watchdog timeout that causes hardware shutdown. Write protection of CMOS RAM, EEPROM, or other memory devices. The and are identical, except the guarantees higher low-line and reset threshold accuracy (±2%). Computers Controllers Intelligent Instruments Critical µp Power Monitoring Applications Features Manual-Reset Input 200ms Power-OK/ Reset Time Delay Independent Watchdog Timer Preset or Adjustable On-Board Gating of Chip-Enable Signals Memory Write-Cycle Completion 0ns (max) Chip-Enable Gate Propagation Delay oltage Monitor for Overvoltage Warning ±2% Reset and Low-Line Threshold Accuracy (, external programming mode) PART** TEMP. RANGE PIN-PACKAGE _CPE 0 C to +70 C 6 Plastic DIP _CSE 0 C to +70 C 6 Narrow SO _C/D 0 C to +70 C Dice* Ordering Information continued at end of data sheet. * Dice are tested at T A = +25 C, DC parameters only. **These parts offer a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. Devices in PDIP, SO and µmax packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. SUFFIX L M TS R Ordering Information THRESHOLD () 4.62 4.7.06 2.9 2.6 Typical Operating Circuit 0.µF 4 IN/INT CE OUT 5 LLIN/ REFOUT CE IN OO 4 6 ADDRESS DECODER RAM A0-A5 µp 7 OI LOW LINE 0 NMI 8 9 SWT MR 2 Maxim Integrated Products For free samples and the latest literature, visit www.maxim-ic.com or phone -800-998-8800. For small orders, phone -800-85-8769.
ABSOLUTE MAXIMUM RATINGS Input oltage (with respect to )...-0. to +6 All Other Inputs...-0. to ( + 0.) Input Current...25mA All Other Outputs...25mA Continuous Power Dissipation (T A = +70 C) Plastic DIP (derate 0.5mW/ C above +70 C)...842mW Narrow SO (derate 9.52mW/ C above +70 C)...762mW CERDIP (derate 0.00mW/ C above +70 C)...800mW Operating Temperature Ranges: _C /_C...0 C to +70 C _E /_E...-40 C to +85 C _MJE /_MJE...-55 C to +25 C Storage Temperature Range...-65 C to +60 C Lead Temperature (soldering, 0s)...+00 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = 2.75 to 5.5, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER Operating oltage Range (Note ) CONDITIONS MIN TYP MAX UNITS 2.75 Supply Current 70 50 µa COMPARATOR L, L 4.50 4.62 4.75 M, M 4.25 4.7 4.50 R, R 2.55 2.6 2.70 S, S 2.85 2.9.00 Reset Threshold oltage T, T.00.06.5 Internal Threshold Mode ( TH ) L, T A = +25 C, falling 4.55 4.70 M, T A = +25 C, falling 4.0 4.45 R, T A = +25 C, falling 2.55 2.66 S, T A = +25 C, falling 2.85 2.96 T, T A = +25 C, falling.00. Reset Threshold oltage, = 5 or =.25.0.5 External Threshold Mode ( TH ), = 5 or =.274.0.26 IN/INT Mode Threshold (Note 2) Internal threshold mode 60 m IN/INT Leakage Current ±0.0 ±25 na Reset Threshold Hysteresis 0.06 x TH Reset Comparator Delay falling 70 µs Reset Active Timeout Period rising 40 200 280 ms Output oltage Output oltage I SINK = 50µA, =, falling 0.0 0. I SINK =.6mA 0. 0.4 I SOURCE = ma - I SOURCE = 00µA I SINK =.6mA - 0.5 I SOURCE = ma - I SOURCE = 00µA - 0.5 0. 0.4 2
ELECTRICAL CHARACTERISTICS (continued) ( = 2.75 to 5.5, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS LOW-LINE COMPARATOR Low-Line Threshold oltage L/M 50 20 20 (Internal Threshold Mode) TH R/S/T 40 00 20 m Low-Line Threshold oltage, = 5 OR =.25.0.5 (External Programming Mode), = 5 OR =.274.0.26 Low-Line Hysteresis (Internal Threshold Mode) 20 m LLIN/REFOUT Leakage Current External Programming Mode ±0.0 ±25 na Low-Line Comparator Delay falling 450 µs LOWLINE oltage I SINK =.2mA 0.4 ISOURCE = µa - LOWLINE Short-Circuit Current Output source current, = 5.5 0 50 µa WATCHDOG FUNCTION Watchdog Timeout Period Watchdog Input Pulse Width WDO Output oltage SWT connected to, = 5.00.60 2.25 SWT connected to, =.00.60 2.25 4.7nF capacitor connected from SWT to, = 70 4.7nF capacitor connected from SWT to, = 5 00 IL = 0, IH = = 5 00 = 00 I SINK = 50µA, =, falling 0.0 0.0 I SINK =.6mA 0. 0.4 I SOURCE = ma - I SOURCE = 00µA - 0.5 WDPO to WDO Delay 70 ns WDPO Duration 0.5.7 6.0 ms WDPO Output oltage I SINK = 50µA, =, falling 0.0 0. I SINK =.6mA 0. 0.4 I SOURCE = ma - I SOURCE = 00µA - 0.5 WDI Threshold oltage = 4.25 IH 0.75 x IL 0.8 = 2.55 IH 0.9 x IL 0.2 WDI Input Current ± µa sec ms ns
ELECTRICAL CHARACTERISTICS (continued) ( = +2.75 to +5.5, T A = T MIN to T MAX, unless otherwise noted.) PARAMETER OEROLTAGE COMPARATOR CONDITIONS MIN TYP MAX UNITS OI Input Threshold = 5 or =.25.0.5 OI Leakage Current ±0.0 ±25 na OO Output oltage I SINK =.2mA 0.4 I SOURCE = µa - OO Short-Circuit Current Output source current, = 5.5 0 50 µa OI to OO Delay OD = 00m, OI rising OD = 00m, OI falling 55 µs CHIP-ENABLE GATING CE IN Threshold oltage = 4.25 IH 0.75 x IL 0.8 = 2.55 IH 0.75 x IL 0.2 CE IN Leakage Current Disabled mode ±0.005 ± µa CE IN to CE OUT Resistance Enabled mode = 5 75 50 = 50 00 Ω CE OUT Short-Circuit Current Disabled mode, CE OUT = 0 = 5 0.5 2.5 = 0.05 0.2 0.4 ma Chip-Enable Propagation Delay 50Ω source impedance driver, = 5 6 0 (Note ) C LOAD = 50pF = 8 ns Chip-Enable Output oltage I OUT = -00µA - High (Reset Active) I OUT = 0µA - 0.5 Reset Active to CE OUT High falling 5 µs MANUAL MR Minimum Pulse Width 25 µs MR to Propagation Delay 2 µs MR Threshold Range...5 MR Pull-Up Current MR = 0 = 4.25 to = 5.5 = 2.5 5 2 80 Note : The minimum operating voltage is 2.75; however, the R and R are guaranteed to operate down to their preset reset thresholds. Note 2: Pulling IN/INT below 60m selects internal threshold mode and connects the internal voltage divider to the reset and low-line comparators. External programming mode allows an external resistor divider to set the low-line and reset thresholds (see Figure 4). Note : The Chip-Enable Propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT. µa 4
Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) SUPPLY CURRENT (µa) 00 90 80 70 60 50 40 0 20 0 0 SUPPLY CURRENT vs. TEMPERATURE = 5 = 4 = = 2-60 -0 0 0 60 90 20 50 TEMPERATURE ( C) SWT = CC ALL OUTPUTS UNLOADED - PROPAGATION DELAY (µs) 70 60 50 40 0 OEROLTAGE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE -60 IH TO OL IN = 20m OERDRIE = 5m -0 0 0 60 90 20 50 TEMPERATURE ( C) -2 PROPAGATION DELAY (µs) 80 70 60 50 40 COMPARATOR PROPAGATION DELAY vs. TEMPERATURE -60 FALLING 5m OERDRIE EXTERNAL PROGRAMMING MODE -0 0 0 60 90 20 50 TEMPERATURE ( C) - PROPAGATION DELAY (µs) 600 500 400 00 200 00 LOW-LINE COMPARATOR PROPAGATION DELAY vs. TEMPERATURE -60 = 5 = FALLING 5m OERDRIE EXTERNAL PROGRAMMING MODE -0 0 0 60 90 20 50 TEMPERATURE ( C) -a DELAY (ms) 00 250 200 50 00 50 0-60 POWER-UP DELAY vs. TEMPERATURE -0 0 0 60 90 20 50 TEMPERATURE ( C) -4 NOMINAL WATCHDOG TIMEOUT PERIOD (s).0 2.5 2.0.5.0 NOMINAL WATCHDOG TIMEOUT PERIOD vs. 2 4 5 () -5 5
(T A = +25 C, unless otherwise noted.) THRESHOLD.25.00.075.050.025.000 0.975 0.950 0.925 0.900-60 INTERNAL-MODE THRESHOLD vs. TEMPERATURE (NORMALIZED) THE THRESHOLD IS SHOWN NORMALIZED TO, REPRESENTING ALL AAILABLE -0 0 0 60 90 20 50 TEMPERATURE ( C) -6 REF OUT () Typical Operating Characteristics (continued)..2..0.29.28.27.26.25-60 -0 REF OUT OLTAGE vs. TEMPERATURE IN / INT = 0 0 0 60 90 20 TEMPERATURE ( C) -7 50 ON-RESISTANCE (Ω) 200 80 60 40 20 00 80 60 40 20 0-60 CHIP-ENABLE ON-RESISTANCE vs. TEMPERATURE -0 0 0 60 90 20 50 TEMPERATURE ( C) = CE IN =.5 = 5 CE IN = 2.5-8 WATCHDOG TIMEOUT PERIOD (ms) 00k 0k k 00 WATCHDOG TIMEOUT PERIOD vs. SWT LOAD CAPACITANCE = 5 = -0 PROPAGATION DELAY (ns) 20 5 0 5 CHIP-ENABLE PROPAGATION DELAY vs. CE OUT LOAD CAPACITANCE = +5 CE IN = 0 TO 5 DRIER SOURCE IMPEDANCE = 50Ω - 0 n 0n C SWT (F) 00n m 0 0 25 50 75 00 25 50 75 200 225 250 C LOAD (pf) 6
Pin Description PIN NAME FUNCTION 2 Reset is the inverse of. Input Supply oltage 4 IN/INT 5 LLIN/REF OUT Active-Low Reset Output goes low whenever falls below the reset threshold in internal threshold programming mode, or IN falls below.0 in external threshold programming mode. remains low for 200ms typ after the threshold is exceeded on power-up. Reset-Input/Internal-Mode Select. Connect this input to to select internal threshold mode. Select external programming mode by pulling this input 600m or higher through an external voltage divider. Low-Line Input/Reference Output connects directly to the low-line comparator in external programming mode ( IN/INT 600m). Connects directly to the internal.0 reference in internal threshold mode ( IN/INT 60m). 6 OO 7 OI 8 SWT 9 MR 0 LOW LINE WDI Overvoltage Comparator Output goes low when OI is greater than.0. This is an uncommitted comparator and has no effect on any other internal circuitry. Inverting Input to the Overvoltage Comparator. When OI is greater than.0, OO goes low. Connect OI to or when not used. Set Watchdog-Timeout Input. Connect this input to to select the default.6sec watchdog timeout period. Connect a capacitor between this input and to select another watchdogtimeout period. Watchdog timeout period = k x (capacitor value in nf)m, where k = 27 for = 5 and k = 6.2 for =. If the watchdog function is unused, connect SWT to. Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a logic gate output. Internally pulled up to. Low-Line Output. LOW LINE goes low 20m above the reset threshold in internal threshold mode, or when LLIN/REFOUT goes below.0 in external programming mode. Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period, WDPO pulses low and WDO goes low. WDO remains low until the next transition at WDI. Connect to or if unused. 2 Ground CE OUT 4 CE IN 5 WDO 6 WDPO Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is low when reset is asserted, CE OUT will stay low for 5µs or until CE IN goes high, whichever occurs first. Chip-Enable Input the input to the chip-enable transmission gate. Connect to or if not used. Watchdog Output. WDO goes low if WDI remains either high or low longer than the watchdog timeout period. WDO returns high on the next transition at WDI. Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPO will pulse low for a minimum of 500µs. WDPO precedes WDO by typically 70ns. 7
Detailed Description Manual-Reset Input Many µp-based products require manual-reset capability, allowing the operator to initiate a reset. The manual/external-reset input (MR) can connect directly to a switch without an external pull-up resistor or debouncing network. MR internally connects to a.0 comparator, and has a high-impedance pull-up to, as shown in Figure. The propagation delay from asserting MR to reset asserted is typically 2µs. Pulsing MR low for a minimum of 25µs asserts the reset function (see Reset Function section). The reset output remains active as long as MR is held low, and the reset timeout period begins after MR returns high (Figure 2). To provide extra noise immunity in high-noise environments, pull MR up to with a 00kΩ resistor. Use MR as either a digital logic input or as a second lowline comparator. Normal TTL/CMOS levels can be wire-or connected via pull-down diodes (Figure ), and open-drain/collector outputs can be wire-ored directly. Monitoring the Regulated Supply The offer two modes for monitoring the regulated supply and providing reset and nonmaskable interrupt (NMI) signals to the µp: internal threshold mode uses the factory preset low-line and reset thresholds, and external programming mode allows the low-line and reset thresholds to be programmed externally using a resistor voltage divider (Figure 4). Internal Threshold Mode Connecting the reset-input/internal-mode select pin ( IN/INT) to ground selects internal threshold mode (Figure 4a). In this mode, the low-line and reset thresholds are factory preset by an internal voltage divider (Figure ) to the threshold voltages specified in the Electrical Characteristics (Reset Threshold oltage and Low-Line Threshold oltage). Connect the low-line output (LOWLINE) to the µp NMI pin, and connect the active-high reset output () or active-low reset output () to the µp reset input pin. Additionally, the low-line input/reference-output pin (LLIN/REFOUT) connects to the internal.0 reference in internal threshold mode. Buffer LLIN/REFOUT with a high-impedance buffer to use it with external circuitry. In this mode, when is falling, LOWLINE is guaranteed to be asserted prior to reset assertion. External Programming Mode Connecting IN/INT to a voltage above 600m selects external programming mode. In this mode, the low-line and reset comparators disconnect from the internal voltage divider and connect to LLIN/REFOUT and IN/INT, respectively (Figure ). This mode allows flexibility in determining where in the operating voltage range the NMI and reset are generated. Set the low-line and reset thresholds with an external resistor divider, as in Figure 4b or Figure 4c. typically remains valid for down to 2.5; is guaranteed to be valid with down to. Calculate the values for the resistor voltage divider in Figure 4b using the following equations: ) R = (.0 x MAX)/( LOW LINE x I MAX ) 2) R2 = [(.0 x MAX)/( x I MAX )] - R ) R = ( MAX/I MAX ) - (R2 + R). First choose the desired maximum current through the voltage divider (I MAX ) when is at its highest ( MAX). There are two things to consider here. First, I MAX contributes to the overall supply current for the circuit, so you would generally make it as small as possible. Second, I MAX cannot be too small or leakage currents will adversely affect the programmed threshold voltages; 5µA is often appropriate. Determine R after you have chosen I MAX. Use the value for R to determine R2, then use both R2 and R to determine R. For example, to program a 4.75 low-line threshold and a 4.4 reset threshold, first choose I MAX to be 5µA when = 5.5 and substitute into equation. R = (.0 x 5.5)/(4.75 x 5E-6) = 0.05kΩ. 0kΩ is the nearest standard 0.% value. Substitute into equation 2: R2 = [(.0 x 5.5)/(4.4 x 5E-6)] - 0kΩ = 2.95kΩ. The nearest 0.% resistor value is 2.7kΩ. Finally, substitute into equation : R = (5.5/5E-6) - (2.7kΩ + 0kΩ) = 775kΩ. The nearest 0.% value resistor is 787kΩ. Determine the actual low-line threshold by rearranging equation and plugging in the standard resistor values. The actual lowline threshold is 4.75 and the actual reset threshold is 4.40. An additional resistor allows the to monitor the unregulated supply and provide an NMI before the regulated supply begins to fall (Figure 4c). Both of these thresholds will vary from circuit to circuit with resistor tolerance, reference variation, and comparator offset variation. The initial thresholds for each circuit will also vary with temperature due to reference and offset drift. For highest accuracy, use the. 8
IN/ INT LLIN/ REFOUT MR 4 5 9 * COMPARATOR LOW-LINE COMPARATOR GENERATOR CHIP-ENABLE OUTPUT CONTROL P 2 0 LOW LINE MANUAL COMPARATOR.0 INTERNAL/ EXTERNAL MODE CONTROL 60m CE IN 4 INTERNAL EXTERNAL P CE OUT TIMEBASE FOR AND WATCHDOG N SWT 8 WATCHDOG TIMER 6 5 WDPO WDO WDI OI 7 OEROLTAGE COMPARATOR WATCHDOG TRANSITION DETECTOR 6 OO 2 * SWITCHES ARE SHOWN IN INTERNAL THRESHOLD MODE POSITION Figure. Block Diagram 9
MR CE IN O CE OUT Figure 2. Manual-Reset Timing Diagram MANUAL 25µs MIN 2µs TYP 5µs TYP 4 5 IN/INT IN LLIN/REFOUT 2 LOW LINE 2 0 TO µp TO µp TO µp NMI OTHER SOURCES * * 9 MR * DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS Figure. Diode "OR" connections allow multiple reset sources to connect to MR. Low-Line Output In internal threshold mode, the low-line comparator monitors with a threshold voltage typically 20m above the reset threshold, and with 5m of hysteresis. For normal operation ( above the reset threshold), LOWLINE is pulled to. Use LOWLINE to provide an NMI to the µp, as described in the previous section, when begins to fall (Figure 4). Reset Function The provide both and outputs. The and outputs ensure that the µp powers up in a known state, and prevent code-execution errors during power-up, power-down, or brownout conditions. The reset function will be asserted during the following conditions: ) less than the programmed reset threshold. 2) MR less than.0 typ. ) Reset remains asserted for 200ms typ after rises above the reset threshold or after MR has exceeded.0 typ.. Figure 4a. Connection for Internal Threshold Mode R R2 R R =.0 x MAX LOW LINE x I MAX R2 =.0 x MAX R x I MAX R = MAX (R2 + R) I MAX IN/INT LLIN/REFOUT IN 2 LOW LINE TO µp TO µp TO µp NMI When reset is asserted, all the internal counters are reset, the watchdog output (WDO) and watchdog-pulse output (WDPO) are set high, and the set watchdog-timeout input (SWT) is set to ( - 0.6) if it is not already connected to (for internal timeouts). The chipenable transmission gate is also disabled while reset is asserted; the chip-enable input (CE IN) becomes high impedance and the chip-enable output (CE OUT) is pulled up to. 2 0 I MAX = THE MAXIMUM DESIRED CURRENT THROUGH THE OLTAGE DIIDED. Figure 4b. Connection for External Threshold Programming Mode 0
R R2 REGULATOR R R4 LOW LINE =. R + R2 ( R2 ) =. R + R4 ( R4 ) IN/INT LLIN/REFOUT Reset Outputs ( and ) The output is active low and typically sinks.6ma at 0.. When deasserted, sources.6ma at typically -.5. The output is the inverse of. is guaranteed to be valid down to =, and an external 0kΩ pull-down resistor on ensures that it will be valid with down to (Figure 5). As goes below, the gate drive to the output switch reduces accordingly, increasing the r DS(ON) and the saturation voltage. The 0kΩ pull-down resistor ensures that the parallel combination of switch plus resistor will be around 0kΩ and the saturation voltage will be below 0.4 while sinking 40µA. When using an external pull-down resistor of 0kΩ, the high state for the output with = 4.75 is typically 4.60. Overvoltage Comparator The overvoltage comparator is an uncommitted comparator that has no effect on the operation of other chip functions. Use this input to provide overvoltage indication by connecting a voltage divider from the input supply, as in Figure 6. Connect OI to ground if the overvoltage function is not used. OO goes low when OI goes above.0. With OI below.0, OO is actively pulled to and can sourceµa. LOW LINE 2 0 TO µp TO µp TO µp NMI Figure 4c. Alternative Connection for External Programming Mode TO µp Figure 5. Adding an external pull-down resistor ensures is valid with down to. OLTAGE REGULATOR 7 OI.0 2 Watchdog Function The watchdog monitors µp activity via the watchdog input (WDI). If the µp becomes inactive, WDO and WDPO are asserted. To use the watchdog function, connect WDI to a µp bus line or I/O line. If WDI remains high or low for longer than the watchdog timeout period (.6s nominal), WDPO and WDO are asserted, indicating a software fault condition (see Watchdog-Pulse Output and Watchdog Output sections). Watchdog Input If the watchdog function is unused, connect WDI to or. A change of state (high-to-low, low-to-high, or a minimum 00ns pulse) at WDI during the watchdog period resets the watchdog timer. The watchdog timer 0k OO Figure 6. Detecting an Overvoltage Condition 6 OEROLTAGE
WDI WDPO WDO = 5.6s 70ns Figure 7. WDI, WDO, and WDPO Timing Diagram MIN 00ns ( = 5) MIN 00ns ( = ) default is.6s. Select alternative timeout periods by connecting an external capacitor from SWT to (see Selecting an Alternative Watchdog Timeout section). When is below the reset threshold, the watchdog function is disabled. Watchdog Output WDO remains high if there is a transition or pulse at WDI during the watchdog timeout period. The watchdog function is disabled and WDO is a logic high when is below the reset threshold. If a system reset is desired on every watchdog fault, simply diode-or connect WDO to MR (Figure 8). When a watchdog fault occurs in this mode, WDO goes low, pulling MR low and causing a reset pulse to be issued. As soon as reset is asserted, the watchdog timer clears and WDO goes high. With WDO connected to MR, a continuous high or low on WDI will cause 200ms reset pulses to be issued every.6sec (SWT connected to ). When reset is not asserted, if no transition occurs at WDI during the watchdog timeout period, WDO goes low 70ns after the falling edge of WDPO and remains low until the next transition at WDI (Figure 7). A single additional flip-flop can force the system into a hardware shutdown if there are two successive watchdog faults (Figure 8). When the are operated from a 5 supply, WDO has a 2 x TTL output characteristic. Watchdog-Pulse Output As described in the preceding section, WDPO can be used as the clock input to an external D flip-flop. Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog timeout period, WDPO will pulse low for.7ms. The falling edge of WDPO precedes WDO by 70ns. Since WDO is high when WDPO goes low, the flipflop s Q output remains high after WDO goes low (Figure 8). If the watchdog timer is not reset by a transition at +5 REACTIATE 0.µF 4.7k 0.µF WDI WDPO 6 9 MR 5 WDO D CLOCK Q CLEAR Q 2 * * FOR SYSTEM ON EERY WATCHDOG FAULT, OMIT THE FLIP-FLOP, AND DIODE OR CONNECT WDO TO MR. µp POWER WDI, WDO remains low and the next WDPO following a second watchdog timeout period clocks a logic low to the Q output, pulling MR low and causing the latch in reset. If the watchdog timer is reset by a transition at WDI, WDO will go high and the flip-flop s Q output will remain high. Thus a system shutdown is only caused by two successive watchdog faults. Selecting an Alternative Watchdog Timeout Period The SWT input controls the watchdog timeout period. Connecting SWT to selects the internal.6sec watchdog timeout period. Select an alternative watchdog timeout period by connecting a capacitor between SWT and. Do not leave SWT floating and do not connect it to ground. The following formula determines the watchdog timeout period: Watchdog Timeout Period = k x (capacitor value in nf)ms where k = 27 for =, and k = 6.2 for = 5. This applies for capacitor values in excess of 4.7nF. If the watchdog function is unused, connect SWT to. I/O TWO CONSECUTIE WATCHDOG FAULT INDICATION Figure 8. Two consecutive watchdog faults latch the system in reset. 2
Chip-Enable Signal Gating The provide internal gating of chipenable (CE) signals, which prevents erroneous data from corrupting CMOS RAM in the event of an undervoltage condition. The use a series transmission gate from CE IN to CE OUT (Figure ). During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The 0ns max CE propagation delay from CE IN to CE OUT enables the to be used with most µps. If CE IN is low when reset asserts, CE OUT remains low for a short period to permit completion of the current write cycle. Chip-Enable Input The CE transmission gate is disabled and CE IN is high impedance (disabled mode) while reset is asserted. During a power-down sequence when passes the reset threshold, the CE transmission gate disables and CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset is asserted, the CE transmission gate will disable at the moment CE IN goes high or 5µs after reset is asserted, whichever occurs first (Figure 9). This permits the current write cycle to complete during power-down. During a power-up sequence, the CE transmission gate remains disabled and CE IN remains high impedance regardless of CE IN activity, until reset is deasserted following the reset timeout period. While disabled, CE IN is high impedance. When the CE transmission gate is enabled, the impedance of CE IN will appear as a 75Ω ( = 5) resistor in series with the load at CE OUT. The propagation delay through the CE transmission gate depends on, the source impedance of the drive connected to CE IN, and the loading on CE OUT (see the Chip-Enable Propagation Delay vs. CE OUT Load Capacitance graph in the Typical Operating Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50% point on CE OUT using a 50Ω driver and 50pF of load capacitance (Figure 0). For minimum propagation delay, minimize the capacitive load at CE OUT, and use a low-output-impedance driver. THRESHOLD CE IN CE OUT 5µs 70µs Figure 9. Reset and Chip-Enable Timing 50Ω DRIER +5 4 CE IN CE OUT 2 Figure 0. CE Propagation Delay Test Circuit C LOAD 70µs Chip-Enable Output When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to 75Ω in series with the source driving CE IN. In the disabled mode, the 75Ω transmission gate is off and an active pull-up connects from CE OUT to. This source turns off when the transmission gate is enabled. Applications Information Connect a 0.µF ceramic capacitor from to, as close to the device pins as possible. This reduces the probability of resets due to high-frequency powersupply transients. In a high-noise environment, additional bypass capacitance from to ground may be required. If long leads connect to the chip inputs, ensure that these lines are free from ringing, etc., which would forward bias the chip s protection diodes.
4 +5 CE IN CE OUT 2 R P * * MAXIMUM R P ALUE DEPENDS ON THE NUMBER OF RAMS. MINIMUM R P ALUE IS kω CE CE CE CE CE CE CE CE ACTIE-HIGH CE LINES FROM LOGIC RAM RAM 2 RAM RAM 4 2 4.7k BUFFER µp TO OTHER SYSTEM INPUTS Figure. Alternate CE Gating Alternative Chip-Enable Gating Using memory devices with both CE and CE inputs allows the CE propagation delay to be bypassed. To do this, connect CE IN to ground, pull up CE OUT to, and connect CE OUT to the CE input of each memory device (Figure ). The CE input of each memory device then connects directly to the chip-select logic, which does not have to be gated by the. Interfacing to µps with Bidirectional Reset Inputs µps with bidirectional reset pins, such as the Motorola 68HC series, can contend with the output. If, for example, the output is asserted high and the µp wants to pull it low, indeterminate logic levels may result. To avoid this, connect a 4.7kΩ resistor between the output and the µp reset I/O, as in Figure 2. Buffer the output to other system components. Figure 2. Interfacing to µps with Bidirectional Pins Negative-Going Transients While issuing resets to the µp during power-up, powerdown, and brownout conditions, these supervisors are relatively immune to short-duration negative-going transients (glitches). It is usually undesirable to reset the µp when experiences only small glitches. Figure shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not generated. The graph was produced using negativegoing pulses, starting at 5 and ending below the reset threshold by the magnitude indicated (resetcomparator overdrive). The graph shows the maximum pulse width a negative-going transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a transient that goes 00m below the reset threshold and lasts for 0µs or less will not cause a reset pulse to be issued. A 00nF bypass capacitor mounted close to the pin provides additional transient immunity. MAXIMUM TRANSIENT DURATION (µs) 00 80 60 40 20 0 = 5 T A = +25 C 0 00 000 0,000 COMPARATOR OERDRIE, ( TH - CC) (m) Figure. Maximum Transient Duration Without Causing a Reset Pulse vs. Reset-Comparator Overdrive MAX79-4
_Ordering Information (continued) PART** TEMP. RANGE PIN-PACKAGE _EPE -40 C to +85 C 6 Plastic DIP _ESE -40 C to +85 C 6 Narrow SO _EJE -40 C to +85 C 6 CERDIP _MJE -55 C to +25 C 6 CERDIP _CPE -0 C to +70 C 6 Plastic DIP _CSE -0 C to +70 C 6 Narrow SO _EPE -40 C to +85 C 6 Plastic DIP _ESE -40 C to +85 C 6 Narrow SO _EJE -40 C to +85 C 6 CERDIP _MJE -55 C to +25 C 6 CERDIP * Dice are tested at T A = +25 C, DC parameters only. **These parts offer a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal reset threshold voltage and insert it into the blank to complete the part number. Devices in PDIP, SO and µmax packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package. TOP IEW 2 IN/INT 4 LLIN/REFOUT 5 OO 6 OI 7 SWT 8 DIP/SO Pin Configuration 6 5 4 2 0 9 WDPO WDO CE IN CE OUT WDI LOW LINE Chip Topography WDPO WDO CE IN MR SUFFIX L M TS R THRESHOLD () 4.62 4.7.06 2.9 2.6 IN/ INT LLIN/ REF OUT CE OUT 0.078" (.98mm) OO WDI OI SWT MR LOW LINE 0.070" (.778mm) TRANSISTOR COUNT: 950 SUBSTRATE CONNECTED TO 5
Package Information N TOP IEW D E H INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.09 0.04 2.5 2.65 A 0.004 0.02 0.0 0.0 B 0.04 0.09 0.5 0.49 C 0.009 0.0 0.2 0.2 e 0.050.27 E 0.29 0.299 7.40 7.60 H 0.94 0.49 0.00 0.65 L 0.06 0.050 0.40.27 ARIATIONS: DIM D D D INCHES MILLIMETERS MIN MAX MIN MAX N MS0 0.98 0.4 0.0 0.50 6 AA 0.447 0.46.5.75 8 AB 0.496 0.52 2.60.00 20 AC D 0.598 0.64 5.20 5.60 24 AD D 0.697 0.7 7.70 8.0 28 AE SOICW.EPS A C e B A 0-8 FRONT IEW L SIDE IEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE,.00" SOIC APPROAL DOCUMENT CONTROL NO. RE. 2-0042 B N DIM A A B INCHES MAX 0.069 0.00 0.09 MIN 0.05 0.004 0.04 MILLIMETERS MIN.5 0.0 0.5 MAX.75 0.25 0.49 SOICN.EPS C 0.007 0.00 0.9 0.25 e 0.050 BSC.27 BSC E H E 0.50 0.57.80 4.00 H 0.228 0.244 5.80 6.20 L 0.06 0.050 0.40.27 TOP IEW ARIATIONS: DIM D D D INCHES MILLIMETERS MIN MAX MIN MAX N MS02 0.89 0.97 4.80 5.00 8 AA 0.7 0.44 8.55 8.75 4 AB 0.86 0.94 9.80 0.00 6 AC D A C e B A FRONT IEW L SIDE IEW 0-8 PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE,.50" SOIC APPROAL DOCUMENT CONTROL NO. RE. 2-004 B Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA 94086 408-77-7600 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.