COMPARISON OF DIFFERENT DESIGNS OF MANCHES STER ENCODER DESIGNED D WITH CMOS INVERTERS USING 32NM UMC CMOS TECHNOLOGY AT 1GHz, 2.5GHz AND 5GHz M. Tech student, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India 1 M 1DEEPENDRA SINGH BHATI, 2 GHANSHYAM Email: deependra.bhati8300@gmail.com 2 Assistant Professor, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India Email: ghanu.4us@gmail.com ABSTRACTT Developments in large scale integration resulted in millions of transistors placed on a single chip for execution of intricate circuitry. Due to this placing of large no of transistors within a small area resulted in more heat dissipation and power consumption. To solve these problems many research were carried on and solutions were proposed such as by decreasing the power supply voltage, switching frequency and capacitance of transistor. Different designs of Manchester Encoder has been designed using CMOS inverters, Transmission Gates, NMOS switches, Pass Transistors & GDI (Gate Diffusion Input) celll that can be operated at higher frequencies. All designs have been designed using 32nm UMC CMOS technology and compared at 1GHz, 2.5GHz & 5GHz clock frequency and experimental results show a correct behaviour up to 5 GHz. 1. INTRODUCTION Today, all data transmission systems, magnetic recording and fiber optic data links use modulation codes for efficient transmission of the signal. The Manchester code is a very efficient code as it is level insensitive, selfclocking and the absence of signal can be easily detected as the coded signal has always at least one transition per bit. Manchester Encoding consumes less power and gives desired output at higher frequencies. Manchester coding technique is a digital coding technique in which all the bits of the binary data are arranged in a particular sequence. Heree a bit 1 is represented by transmitting a high voltage for half duration of the input signal and for the next halftime period an inverted signal will be send. When Transmitting 0 in Manchester format, for the first half cycle a low voltage will send, and for the next half cycle a highh voltage is send. Manchester encoding schemee always show the transition in the data signal at the mid point of the data bit frame. Repetition of logic 1 or 0 in NRZ data produces low to highh transition or high to low transitionn respectively at the edge of the data bit frame in Manchester encoded data. Manchester encoded data does not show any change at the edge of the data bit frame if there is change in binary data. Manchester encoder also acts as an XNOR gate. Figure1.1: Waveforms of NRZ Data & Manchester Data 1.11 Advantages of Manchester Encoding In this scheme a single connection can give clock and data information simultaneously. It does not require a separate clock, Digital phase locked loop is used to extract the clock at the receiving data terminal equipment. It does not produce long strings of logic 1 or logic 0 levels. There is a provision of AC coupling of encoded signal as this scheme does not require transmission of DC component. Logic 0 followed by a logic 0 represents the absence of the signal and Logic 1 followed by a logic 1 represents the conflict in signal. The signal power is independent from the data pattern. Reset signal is not required in this scheme. It is very efficient method for use on single core systems such as optical fiber, coaxial cable, Ethernett and Local area networks (LANs). It also acts as an edge triggered D flip flop. 1.2 Disadvantage of Manchester Encoding INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 314
This encoding scheme is disadvantageous only because its null bandwidth is twice that of the polar NRZ, Unipolar NRZ. In this paper we will discuss two sections, first we will discuss about the previous work (Literature Review) in section 2, and then we will discuss the proposed work under section 3 in which we will use different designs of Manchester encoder. 2. LITERATURE REVIEW The previous work done A 90nm Manchester Code Generator with CMOS switches running at 2.4Ghz and 5Ghz of 2009 @ IEEE. It was the Manchester code generator which was designed at transistor level and it consisted of NMOS switches. The circuit has the same complexity as standard D flip flop and has 26 transistor and 6 NMOS switches. Figure 2.1 shows Manchester encoder circuit. 3.2 Manchester Encoder Design I Figure3.1: Manchester Encoder Design I This Manchester Encoder design has been constructed by using CMOS inverters and NMOS digital switches. It consists of 26 transistors. In this circuit an inverting latch (I 8, I 9 ) is following a non inverting latch (I 3, I 4, I 5 ). When phase f 1 occurs, input signal is passed through inverter I 4. When phase f 2 occurs, inverters I 4 and I 5 latch the input signal and pass it to output node (Out) via inverters I 6 and I 10, at this stage inverter I 9 produces the inverse value of Out. When the next f 1 phase occurs, inverters I 8 and I 9 latch the previously inverted output and pass it to the inverters I 6 and I 10 and then to output node. Therefore we can conclude that rising edge of the clock signal, produces the same input and falling edge of the clock signal produces the inverted input at the output node. Figure2.1 Encoder Block Diagram 3. PROPOSED WORK In this section we will use different circuit to design Manchester Encoder and then check there waveforms, delays and average powers at 32nm at frequency 1 GHz, 2.5 GHz & 5 GHz, but before that we will discuss my work in literature review. 3.1 Literature Review (Proposed Work) I have proposed the previously proposed work on A 90nm Manchester Code Generator with CMOS switches running at 2.4Ghz and 5Ghz. The circuit was designed in 90nm UMC CMOS technology to evaluate the efficiency and experimental results showed correct behaviour up to 5GHz. This encoder was run at V dd =1.2 volt and simulated at typical, fast and slow transistor s corners with clock frequency of 2.4 & 5 GHz. The new simulation was checked on HSPICE simulation tool and found that the work could have been better and better results could be achieved. The average power consumption is more than thousand micro watts i.e. 1168uw at 2.4GHz & 1522uw at 5GHz frequency. The propagation time of both the frequency was improved to 41ps & 56ps from 61ps & 128ps of 2.4 GHz and 5 GHz respectively. 3.3 Manchester Encoder Design II Manchester Encoder is constructed with CMOS inverters and Transmission Gates. In this design when the clock signal is low (logic 0 ), TG (T1) becomes on, T2 & inverter S goes in off condition therefore we get inverted data through inverter I2; when the clock signal is high transmission gate T1 gets off, T2 & S goes in on condition therefore same data is obtained at the output node. At this stage when clock signal is high switch S restricts the fading of the signal through that path where it is connected by making value logic 0. Therefore we can conclude that on the rising edge of the clock signal, the same input gets transmitted to the output, while on the falling edge of the clock signal, we get the inverted input at the output node. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 315
Figure3..2: Manchester Encoder Design II 3.4 Manchester Encoder Design III Figure3.4: Manchester Encoder Design IV It consists of two GDI D Latches called Master Slave connection. Each latch is composed of four basic GDI cells and each cell contains 2 transistors therefore it is a eight transistor structure. The parts of the circuit can be divided into two main categories: (a) Body gates These are responsible for the two different statess of the circuit. When clk signal is low, signals pass through PMOS transistors; it is called transparent state of the latch. When clk signal is high, signals pass through NMOS transistors and internal values are stored, it is called holding state of the latch. Figure3.3: Manchester Encoder Design III This circuit is constructed with GDI cells. In this circuit inverter I3 is a GDI cell acting as a multiplexer. Two pass transistors T1 & T2 are operating as digital switches. When clock signal is low, T1 switches ON and T2 switches OFF, due to this data signal gets inverted by inverter I2 and passes through source terminal of PMOS of inverter I3. At this stage when clock signal is low PMOS of inverter I3 switches ON and NMOS switches OFF. Therefore we get the inverted data at the output node. When clock signal is high pass transistor T1 switches OFF and T2 switches ON, data signal passes directly through the source terminal of NMOS of inverter I3. At this stage PMOS of inverter I3 switches OFF and NMOS switches ON. Therefore we get the original data at the output node. (b) Inverters (marked by ) This device maintains the complementary values of the internal signals and device outputs. It also acts as a buffer for the internal signals to restore voltage swing and to improve driving abilities of the outputs. This classification helps in understanding device operation and working. It is noticed that transmission of the signal in body gates is done through the diffusion nodes of the GDI cells. It may result in swing drop of V TH in the output signals. Internal inverters are used as buffer to solve this problem. Size of each transistor in the circuit is adjusted to optimize the circuit performance and to minimize the power delay product. It is the efficient design of Manchester Encoder which contains 18 transistors (16 are shown in diagram and 2 are used to complement the value of D) used to obtain low area and high performance circuits. 3.6 Manchester Encoder Design V 3.5 Manchester Encoder Design IV INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 316
Figure3.5: Manchester Encoder Design V When clock(clk) signal is low, pass transistors T1 and T4 switches ON and transistors T2 and T3 gets OFF. At this stage slave section acts as a loop containing two inverters and one pass transistor I3, I4 and T4 respectively. This loop stores the previous triggered value of Din. At the same time master section takes new value of Din but does not pass it to the slave section because T3 is OFF. When clock signal is high, pass transistors T2 and T3 becomes ON and new stored value in master section gets passed to the slave section and to the output through the loop of two inverters and one pass transistor I1, I2 and T2 respectively. Both master and slave sections are connected to ground whenever we want to reset the circuit. Figure 4.2: Output at 90nm of f=5 GHz 4.2 Waveform for Design I V (1): Data Signal, V (4): Clock signal, V (16): Output 4. SIMULATION RESULTS In this section waveform of all proposed work has been shown 4.1 Literature Review V (4): Clock signal, V (1): Data signal, V (16): Output Figure 4.3: Output at 32nm for f = 1GHz (Design I) Figure4.1: Output at 90nm for f=2.4 GHz Figure 4.4: Output at 32nm for f = 2.5GHz (Design I) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 317
Figure 4.5: Output at 32nm for f = 5GHz (Design I) 4.3 Waveform for Design II V (1): Clock signal, V (3): Data signal, V (7): Output Figure 4.8: Output at 32nm for f = 5GHz (Design II) 4.4 Waveform for Design III V (2): Clock signal, V (1): Data signal, V (9): Output Figure 4.6: Output at 32nm for f = 1GHz (Design II) Figure 4.9: Output at 32nm for f = 1GHz (Design III) Figure 4.7: Output at 32nm for f = 2.5GHz (Design II) Figure 4.10: Output at 32nm for f = 2.5GHz (Design III) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 318
Figure 4.11: Output at 32nm for f = 5GHz (Design III) 4.5 Waveform for Design IV V (1): Clock signal, V (4): Data signal, V (12): Output Figure 4.14: Output at 32nm for f = 5GHz (Design IV) 4.6 Waveform for Design V V (1): Clock signal, V (2): Data signal, V (13): Output Figure 4.12: Output at 32nm for f = 1GHz (Design IV) Figure 4.15: Output at 32nm for f = 1GHz (Design V) Figure 4.13: Output at 32nm for f = 2.5GHz (Design IV) Figure 4.16: Output at 32nm for f = 2.5GHz (Design V) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 319
Table 5.3: Comparison between different designs Clock Frequency(2.5GHz)& L=32nm Des ign No. No. of Transistor s used Propagation (ps) Average Power (µw) PDP (fj) 1 26 72.18 379.26 27.37 2 9 60.72 155.10 9.417 3 10 64.59 158.82 10.25 4 18 66.85 235.46 15.74 5 18 67.43 265.34 17.89 Figure 4.17: Output at 32nm for f = 5GHz (Design V) 5. RESULT AND COMPARISON Table 5.4: Comparison between different designs Clock Frequency(5GHz)& L=32nm Here Comparison table from Literature review and proposed work is shown. Table 5.2, 5.3 & 5.4 demonstrates the comparison between different designs at 32nm working at 1GHz, 2.5GHz & 5GHz. Desi gn No. No. Of Transisto rs used Propagat ion Average Power PDP (fj) Table 5.1: Comparison from Literature Review (ps) (µw) Clock Frequency (GHz) Previous Work Proposed work 1 26 71.45 370.78 26.492 2 9 59.16 151.57 8.966 2.4 Propagation 5 Propagation 61ps 128ps 41ps 56ps 3 10 63.64 153.43 9.764 4 18 65.27 240.52 15.698 5 18 66.78 256.43 17.124 Table 5.2: Comparison between different designs Clock Frequency(1GHz)& L=32nm De sig n No. No. of Transisto rs used Propagat ion (ps) Average Power (µw) PDP (fj) 1 26 172.70 151 26.07 7 2 9 437.695 544.37 238.2 6 3 10 97.727 98.199 9.596 4 18 35.210 163.81 5.767 5 18 358.6 709.10 254.2 8 6. CONCLUSION AND FUTURE SCOPE In this thesis, I have designed different forms of Manchester Encoder using CMOS inverters, NMOS digital switches, pass transistors and GDI cell. Each circuit structure has been designed using 32nm UMC CMOS technology. All the designs have been simulated in HSPICE and correct results have been obtained at different clock frequencies (1GHz, 2.5GHz and 5GHz) with supply voltage V dd = 1V and 25 degree centigrade. Design II is considered to be the best optimized design of Manchester Encoder at 5GHz with average power = 151.57µW and power delay product (PDP) = 8.966fJ. Thus for high speed communication systems this best optimized design can be used. In future Manchester encoder can be designed at above 5GHz. As technology is getting advanced, 22nm & 16nm UMC CMOS libraries are also available, therefore this encoder can be designed in different forms by using different components to reduce the chip size, average power consumed and total cost of the system by optimizing transistors sizes. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 320
REFERENCES 1. P. Benabes, A. Gauthier, J. Oksman, A Manchester code generator running at 1GHz, ICECS, July 2003. 2. A. Karagounis, A. Polyzos, B. Kotsos, N. Assimakis, A 90nm Manchester Code Generator with CMOS switches running at 2.4GHz and 5GHz, Systems, Signals and Image Processing, 16th International Conference, June 2009, pp. 1 4. 3. Yu Cherng Hung, Min Ming Kuo, Chiou Kou Tung, and Shao HuiShieh, High Speed CMOS Chip Design for Manchester and Miller Encoder, 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IEEE 2009. 4. ArkadiyMorgenshtein, Alexander Fish and Israel A. Wagner, Gate Diffusion Input (Gdi) A Technique For Low Power Design Of Digital Circuits: Analysis And Characterization, IEEE 2002. 5. ArkadiyMorgenshtein, Alexander Fish and Israel A. Wagner, An Efficient Implementation of D Flip Flop Using the GDI Technique, IEEE 2004. 6. Gogireddy Sravanthi and Avireni Srinivasulu, Member, IEEE, Performance Analysis of two Manchester Encoders based on TLG s, Modified Current Sink Inverter Multiplexer and Active N MOS Load Inverter Multiplexer, 2013. 7. Shi Jingzhuo, Xu Yingxi, Shi Jing Henan University of Science & technology Luoyang, P. R. China Manchester Encoder and Decoder Based on CPLD IEEE 2008. BIOGRAPHIES Deependra Singh Bhati is a M.Tech student (V.L.S.I) at Gyan Vihar School of Engineering and Technology, Jaipur, Rajasthan. He has completed his B.Tech (Electronics and Communication) in 2013 under dual Degree Program at Gyan Vihar School of Engineering and Technology, Jaipur. His main research interests are in reducing the size of transistors by reducing W/L ratio & operate them on high frequency. Ghanshyam is an Assistant Professor at Gyan Vihar School of Engineering and Technology. He has completed his M.Tech (V.L.S.I) from Malviya National Institute of Technology in 2013 He has completed his B.Tech in Electronics and Communication from Rajasthan University in 2008. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY- www.ijset.in 321