5V 256K 16 CMOS DRAM (EDO) Features Organization: 262,144 words 16 bits High speed - 30/35/50 ns access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time Low power consumption - Active: 500 mw max (AS4C256K16E0-25) - Standby: 3.6 mw max, CMOS (AS4C256K16E0-25) EDO page mode Refresh - 512 refresh cycles, 8 ms refresh interval --only or CAS-before- refresh or self-refresh - Self-refresh option is available for new generation device only. Contact Alliance for more information. Read-modify-write TTL-compatible, three-state JEDEC standard packages - 400 mil, 40-pin SOJ - 400 mil, 40/44-pin TSOP II 5V power supply Latch-up current > 200 ma Pin arrangement Vcc 0 1 2 3 Vcc 4 5 6 7 NC NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SOJ AS4C256K16E0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND 15 14 13 12 GND 11 10 9 8 NC A8 A7 A6 A5 A4 GND V CC 0 1 2 3 V CC 4 5 6 7 NC NC NC A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 TSOP II AS4C256K16E0 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 GND 15 14 13 12 GND 11 10 9 8 NC A8 A7 A6 A5 A4 GND Pin designation Pin(s) Description A0 to A8 inputs Row address strobe 0 to 15 Input/output Output enable Column address strobe, upper byte Column address strobe, lower byte Read/write control V CC GND Power (5V ± 0.5V) Ground Selection guide Symbol AS4C256K16E0-30 AS4C256K16E0-35 AS4C256K16E0-50 Unit Maximum access time t RAC 30 35 50 ns Maximum column address access time t CAA 16 18 25 ns Maximum CAS access time 10 10 10 ns Maximum output enable () access time t A 10 10 10 ns Minimum read or write cycle time 65 70 85 ns Minimum EDO page mode cycle time t PC 12 14 25 ns Maximum operating current I CC1 180 160 140 ma Maximum CMOS standby current I CC2 2.0 2.0 2.0 ma Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 1 of 24 Copyright Alliance Semiconductor. All rights reserved.
Functional description The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16 bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the 512 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Very fas to output access time eases system design. Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following: -only refresh cycles Hidden refresh cycles CAS-before- refresh cycles Normal read or write cycles Self-refresh cycles* The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated testing and insertion equipment. System level features include single power supply of 5V ± 0.5V tolerance and direct interface with TTL logic families. Logic block diagram V CC GND REFRESH CONTROLLER COLUMN DECODER SENSE AMP DATA BUFFER 0 to 15 CLOCK GENERATOR CAS CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 A8 ADDRESS BUFFERS ROW DECODER 512 512 16 ARRAY (4,194,304) SUBSTRATE BIAS GENERATOR CLOCK GENERATOR Recommended operating conditions (T a = 0 C to +70 C) Parameter Symbol Min Typ Max Unit Supply voltage V CC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V Input voltage V IH 2.4 V CC + 1 V V IL 1.0 0.8 V *Self-refresh option is available for new generation device only. Contact Alliance for more information. 4/11/01; v.1.1 Alliance Semiconductor 2 of 24
Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage V in -1.0 +7.0 V Output voltage V out -1.0 +7.0 V Power supply voltage V CC -1.0 +7.0 V Operating temperature T OPR 0 +70 C Storage temperature (plastic) T STG -55 +150 C Soldering temperature time T SOLDER 260 10 o C sec Power dissipation P D 1 W Short circuit output current I out 50 ma Latch-up current 200 ma NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC electrical characteristics Parameter Symbol Test conditions Input leakage current Output leakage current Operating power supply current TTL standby power supply current Average power supply current, refresh mode EDO page mode average power supply current CMOS standby power supply current CAS-before- refresh power supply current Output Voltage Self refresh current I IL I OL I CC1 Shaded areas contain advance information. 0V V in +5.5V pins not under test = 0V D OUT disabled, 0V V out +5.5V,,, address cycling; =min -30-35 -50 Min Max Min Max Min Max Unit -10 10-10 10-10 10 µa -10 10-10 10-10 10 µa Note 180 160 140 ma 1,2 I CC2 = = = V IH 2.0 2.0 2.0 ma I CC3 cycling, = = V IH, = min I CC4 ===V IL, address cycling: t SC = min 200 190 140 ma 1 190 180 70 ma 1,2 I CC5 === V CC - 0.2V 1.0 1.0 1.0 ma I CC6,,, cycling; = min 200 190 140 ma 1 V OH I OUT = -5.0 ma 2.4 2.4 2.4 V V OL I OUT = 4.2 ma 0.4 0.4 0.4 V = = =V IL, = = A0-A8 = V I CC -0.2V, CC7 DQ0-DQ15 = V CC -0.2V, 0.2V are open 2.0 2.0 2.0 ma 4/11/01; v.1.1 Alliance Semiconductor 3 of 24
AC parameters common to all waveforms Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes Random read or write cycle time 65 70 85 ns precharge time 25 25 25 ns t pulse width 30 75K 35 75K 50 75K ns CAS pulse width 5 6 10 ns to CAS delay time 15 20 16 24 15 35 ns 6 to column address delay time 10 14 11 17 15 25 ns 7 (R) CAS to hold time (read cycle) 10 10 10 ns to CAS hold time 30 35 50 ns CAS to precharge time 5 5 5 ns Row address setup time 0 0 0 ns Row address hold time 5 6 9 ns t T Transition time (rise and fall) 1.5 50 1.5 50 3 50 ns 4,5 t REF Refresh period 8 8 8 ms 3 CAS to output in low Z 0 0 3 ns 8 Shaded areas contain advance information. Read cycle Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes t RAC Access time from 30 35 50 ns 6 Access time from CAS 10 10 10 ns 6,13 Access time from address 16 18 25 ns 7,13 t AR(R) Column add hold from 26 28 30 ns Read command setup time 0 0 0 ns H Read command hold time to CAS 0 0 0 ns 9 trrh Read command hold time to 0 0 0 ns 9 Column address to Lead time 16 18 25 ns t CPN CAS precharge time 3 4 5 ns t OFF Output buffer turn-off time 0 8 0 8 0 8 ns 8,10 Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 4 of 24
Write cycle Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes Column address setup time 0 0 0 ns Column address hold time 5 5 9 ns t AWR Column address hold time to 26 28 30 ns t WCS Write command setup time 0 0 0 ns 11 t WCH Write command hold time 5 5 9 ns 11 t WCR Write command hold time to 26 28 30 ns Write command pulse width 5 5 9 ns Write command to lead time 10 11 12 ns Write command to CAS lead time 10 11 12 ns Data-in setup time 0 0 0 ns 12 Data-in hold time 5 5 9 ns 12 R Data-in hold time to 26 28 30 ns Shaded areas contain advance information. Read-modify-write cycle Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes t RWC Read-write cycle time 100 105 120 ns t RWD to delay time 50 54 60 ns 11 t CWD CAS to delay time 26 28 30 ns 11 t AWD Column address to delay time 32 35 40 ns 11 (W) CAS to hold time (write) 10 10 12 ns (W) CAS pulse width (write) 15 15 15 ns Shaded areas contain advance information. 4/11/01; v.1.1 Alliance Semiconductor 5 of 24
EDO page mode cycle Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes t PC Read or write cycle time 12 14 25 ns 14 t CAP Access time from CAS precharge 19 21 23 ns 13 t CP CAS precharge time 3 4 5 ns t PCM EDO page mode RMW cycle 56 58 60 ns t CRW Page mode CAS pulse width (RMW) 44 46 50 ns t P pulse width 30 75K 35 75K 50 75K ns Shaded areas contain advance information. Refresh cycle Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes t CSR CAS setup time (CAS-before-) 10 10 10 ns 3 t CHR CAS hold time (CAS-before-) 7 8 10 ns 3 C precharge to CAS hold time 0 0 0 ns t CPT CAS precharge time (CAS-before- counter test) 8 8 8 ns Shaded areas contain advance information. Output enable Std -30-35 -50 Symbol Parameter Min Max Min Max Min Max Unit Notes t ROH hold time referenced to 5 5 5 ns t A access time 10 10 10 ns t D to data delay 5 5 8 ns t Z Output buffer turnoff delay from 8 8 8 ns 8 t H command hold time 8 8 8 ns Shaded areas contain advance information. Self refresh cycle Std Symbol t S S t CHS Parameter pulse width (CBR self refresh) precharge time (CBR self refresh) CAS hold time (CBR self refresh) Shaded areas contain advance information. -30-35 -50 Min Max Min Max Min Max Unit 100K 100K 100K ns 85 85 85 ns 30 30 30 ns Notes 4/11/01; v.1.1 Alliance Semiconductor 6 of 24
Notes 1 I CC1, I CC3, I CC4, and I CC6 depend on cycle rate. 2 I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open. 3 An initial pause of 200 µs is required after power-up followed by any 8 cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before- initialization cycles instead of 8 cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). 4 AC Characteristics assume t T = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pf, V IL (min) GND and V IH (max) V CC. 5 V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH and V IL. 6 Operation within the (max) limit insures that t RAC (max) can be met. (max) is specified as a reference point only. If is greater than the specified (max) limit, then access time is controlled exclusively by. 7 Operation within the (max) limit insures that t RAC (max) can be met. (max) is specified as a reference point only. If is greater than the specified (max) limit, then access time is controlled exclusively by. 8 Assumes three state test load (5 pf and a 380 Ω Thevenin equivalent). 9 Either H or t RRH must be satisfied for a read cycle. 10 t OFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11 t WCS, t WCH, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t WS t WS (min) and t WH t WH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t RWD t RWD (min), t CWD t CWD (min) and t AWD t AWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12 These parameters are referenced to CAS leading edge in early write cycles and to leading edge in read-write cycles. 13 Access time is determined by the longest of t CAA or or t CAṖ 14 t CP to achieve t PC (min) and t CAP (max) values. 15 These parameters are sampled and not 100% tested. Key to switching waveform Undefined/don t care Rising input Falling input Read cycle waveform t, t AR Row Col t RRH H t ROH t RAC t Z t A t OFF 4/11/01; v.1.1 Alliance Semiconductor 7 of 24
Upper byte read cycle waveform t trsh Row Column t RRH H t ROH t A t RAC t Z Upper t OFF Lower Lower byte read cycle waveform t Row Column H t RRH t ROH Upper t A t RAC tz Lower t OFF 4/11/01; v.1.1 Alliance Semiconductor 8 of 24
Early write cycle waveform t, t AWR Row Col t WCR t WCS t WCH R Upper byte early write cycle waveform Row t AWR t Column C t WCS t WCH Upper Lower R t WCR 4/11/01; v.1.1 Alliance Semiconductor 9 of 24
Lower byte early write cycle waveform t t AWR Row Column C t WCR t WCS t WCH Upper R Lower Write cycle waveform ( controlled) t, t AWR Row Col t WCR t H R t D tdh 4/11/01; v.1.1 Alliance Semiconductor 10 of 24
Upper byte write cycle waveform ( controlled) t t AWR Row Column C t H Upper Lower t D Lower byte write cycle waveform ( controlled) t t AWR Row Column t ACS C Upper t H Lower 4/11/01; v.1.1 Alliance Semiconductor 11 of 24
Read-modify-write cycle waveform t t RWC, t AR Row Col t RWD t AWD t RAC t A t CWD t D t Z 4/11/01; v.1.1 Alliance Semiconductor 12 of 24
Upper byte read-modify-write cycle waveform t RWC t t ACS C Row Column t RWD t AWD t CWD t A Upper Input t D Upper Output Lower Input Lower Output t RAC t Z t D 4/11/01; v.1.1 Alliance Semiconductor 13 of 24
Lower byte read-modify-write cycle waveform t RWC t C t ACS tcah Row Column t RWD t AWD t CWD t A Upper Input Upper Output Lower Input t RAC t D Lower Output t Z 4/11/01; v.1.1 Alliance Semiconductor 14 of 24
EDO page mode read cycle waveform t P, t AR t CP t PC Row t RAC Col Col Col t A H t RRH H t CAP t A EDO page mode byte read cycle waveform t P t CP t PC t PC tcp C Row Column 1 Column 2 Column n trch H t A t A t A Lower Upper t RAC t OFF t Z 1 t CAP 2 t CAP t OFF t Z t Z n t OFF 4/11/01; v.1.1 Alliance Semiconductor 15 of 24
EDO page mode early write cycle waveform t P t PC, t WCS t CP t AR Row address Col address Col Col t WCH t H t HDR EDO page mode byte early write cycle waveform t P t CP t CP t PC t PC C Row Column 1 Column 2 Column n t WCH t WCH t WCH t WCS t WCS t WCS Lower 2 Upper 1 n 4/11/01; v.1.1 Alliance Semiconductor 16 of 24
EDO page mode read-modify-write cycle waveform t P t PCM, t CP Row Ad Col Ad Col Ad Col t RWD t CWD t AWD t CWD t CWD t AWD t A t Z t D t A t CAP t RAC CAS-before- refresh cycle waveform ( = V IH ) t C t CPN t CHR, t OFF t CSR only refresh cycle waveform ( = = V IH or V IL ) t, t ARS Row C 4/11/01; v.1.1 Alliance Semiconductor 17 of 24
EDO page mode byte read-modify-write cycle t P t PCM t CP t CP t AWD R C 1 C 2 C n t AWD t AWD t CWD t CWD t CWD t RWD t D t A t A t A Upper Input Upper Output t RAC 1 1 t Z t D t CAP t D t Z n n Lower Input 2 t Z Lower Output 2 4/11/01; v.1.1 Alliance Semiconductor 18 of 24
Hidden refresh cycle (read) waveform t t PR t t PR t CHR CAS t AR Row Col t RRH t A t RAC t OFF t Z Hidden refresh cycle (write) waveform, t t AR Row Col t WCR t WCS t WCH R 4/11/01; v.1.1 Alliance Semiconductor 19 of 24
CAS-before- refresh counter test cycle waveform t t CSR t CHR t CPT, Col t OFF Read Cycle t A t ROH t RRH H t WCH Write Cycle t WCS t CWD t AWD Read-Write Cycle t A t Z t D 4/11/01; v.1.1 Alliance Semiconductor 20 of 24
CAS-before- self refresh cycle t S S C C t CP, DQ t CEZ t CSR t CHS Typical DC and AC characteristics 1.5 Normalized access time t RAC vs. supply voltage V CC 1.5 Normalized access time t RAC vs. ambient temperature T a 100 Typical access time t RAC vs. load capacitance C L Normalized access time 1.4 1.3 1.2 1.1 1.0 0.9 T a = 25 C Normalized access time 1.4 1.3 1.2 1.1 1.0 0.9 Typical access time 90 80 70 60 50 40 0.8 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) 0.8 55 10 35 80 125 Ambient temperature ( C) 30 50 100 150 200 250 Load capacitance (pf) 70 Typical supply current I CC vs. supply voltage V CC 70 Typical supply current I CC vs. ambient temperature T a 35 Typical power-on current I PO vs. cycle rate 1/ 60 60 30 Supply current (ma) 50 40 30 20 10 Supply current (ma) 50 40 30 20 10 Power-on current (ma) 25 20 15 10 5 0.0 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) 0.0 55 10 35 80 125 Ambient temperature ( C) 0.0 2 4 6 8 10 Cycle rate (MHz) 4/11/01; v.1.1 Alliance Semiconductor 21 of 24
35 Typical refresh current I CC3 vs. supply voltage V CC 35 Typical refresh current I CC3 vs. Ambient temperature Ta 3.5 Typical TTL stand-by current I CC2 vs. supply voltage V CC 30 30 3.0 Refresh current (ma) 25 20 15 10 5 Refresh current (ma) 25 20 15 10 5 Stand-by current (ma) 2.5 2.0 1.5 1.0 0.5 0 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) 0 0.0 20 40 60 80 Ambient temperature ( C) 0 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) Typical TTL stand-by current I CC2 vs. ambient temperature T a 3.5 70 Typical output sink current I OL vs. output voltage V OL Typical output source current I OH vs. output voltage V OH 70 Stand-by current (ma) 3.0 2.5 2.0 1.5 1.0 0.5 Output sink current (ma) 60 50 40 30 20 10 Output source current (ma) 60 50 40 30 20 10 0.0 0 20 40 60 80 Ambient temperature ( C) 0.0 0.0 0.5 1.0 1.5 2.0 Output voltage (V) 0.0 0.0 1.0 2.0 3.0 4.0 Output voltage (V) EDO page mode current (ma) Typical EDO page mode current I CC4 vs. ambient temperature T a 35 30 25 20 15 10 5 0.0 0 20 40 60 80 Ambient temperature ( C) EDO page mode current (ma) Typical EDO page mode current I CC4 vs. supply voltage V CC 35 30 25 20 15 10 5 0.0 4.0 4.5 5.0 5.5 6.0 Supply voltage (V) 4/11/01; v.1.1 Alliance Semiconductor 22 of 24
Package dimensions 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 c A 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 A 1 Pin 1 A1 b 44-pin TSOP II e d 40-pin SOJ B b e D Seating Plane A 2 E1 E2 A A2 E 0 5 H e E l c 44-pin TSOP II Min (mm) Max (mm) A 1.2 A 1 0.05 A 2 0.95 1.05 b 0.30 0.45 c 0.127 (typical) d 18.28 18.54 E 10.03 10.29 H e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 40-pin SOJ 400 mil Min Max A 0.128 0.148 A1 0.025 - A2 1.105 1.115 B 0.026 0.032 b 0.015 0.020 c 0.007 0.013 D 1.020 1.035 E 0.370 (typical) E1 0.390 0.410 E2 0.435 0.445 e 0.050 (typical) Capacitance ƒ = 1 MHz, T a = room temperature, V CC = 5V ± 0.5V Parameter Symbol Signals Test conditions Max Unit C IN1 A0 to A8 V in = 0V 5 pf Input capacitance C IN2,,,, V in = 0V 7 pf capacitance C 0 to 15 V in = V out = 0V 7 pf Ordering codes Package \ Access time 30 ns 35 ns 50 ns Plastic SOJ, 400 mil, 40-pin AS4C256K16E0-30JC AS4C256K16E0-35JC AS4C256K16E0-50JC TSOP II, 400 mil, 40/44-pin AS4C256K16E0-50TC Shaded areas contain advance information. Part numbering system AS4C 256K16E0 XX X C DRAM prefix Device number access time Package: J = SOJ T = TSOP II Commercial temperature range, 0 C to 70 C 4/11/01; v.1.1 Alliance Semiconductor 23 of 24
4/11/01; v.1.1 Alliance Semiconductor 24 of 24 Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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