32C48B 4 Megabit (12K x 8-Bit) SRAM A13 A A1 A2 A3 A4 CS 1 36 NC A18 A17 A16 A1 OE A12 A11 A1 A9 A8 A7 A6 A A4 ROW DECODER MEMORY MATRIX 124 ROWS x 496 COLUMNS I/O1 I/O8 I/O2 Vcc Vss I/O3 32C48B I/O7 Vss Vcc I/O6 DQ INPUT DATA CONTROL COLUMN I/O COLUMN DECODER I/O4 WE I/O A14 DQ7 A18 A17 A16 A1 A14 A3 A2 A1 A A A13 DQ A6 A7 A8 A9 18 19 FEATURES: A12 A11 A1 NC CS WE OE DESCRIPTION: Logic Diagram DQ7 12k x 8-bit CMOS architecture RAD-PAK technology hardened agait natural space radiation Total dose hardness: - > 1 krad (Si), depending upon space mission Single event effect: - SEL TH : > 68 MeV/mg/cm 2 - SEU TH : < 3MeV/mg/cm 2 - SEU saturated cross section: 6E-9 cm 2 /bit Package: -36 pin RAD-PAK flat pack Fast propagation time:, 2, 3 maximum access time Single V + 1% power supply Low power dissipation: - Standby: 6mA (TTL); 1mA (CMOS) - Operating: 18 ma (2 ); 17 ma (2 ); 16 ma (3 ) TTL compatible inputs and outputs Fully static operation - No clock or refresh required Three state outputs DDC s 32C48B high-speed 4 Megabit SRAM microcircuit features a greater than 1 krad (Si) total dose tolerance, depending upon space mission. Using RAD-PAK packaging technology, the 32C48B realizes higher deity, higher performance and lower power coumption, and is well suited for high-speed system application. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power coumption and provides higher reliability. The 32C48B is equipped with eight common input/ output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. DDC's patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. In a GEO orbit, RAD-PAK can provides true greater than 1 krad (Si) total radiation dose tolerance; dependent upon space mission. The patented radiation-hardened RAD-PAK technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with packaging and screening up to Class S..2.2 Rev 7 1 (631) 67-6 - www.ddc-web.com 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B TABLE 1. 32C48B ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Voltage on any pin relative to V SS V IN, V OUT -. V CC +. V Voltage on V CC supply relative to V SS V CC -. 7. V Power Dissipation P D 1. W Storage Temperature T S -6 +1 C Operating Temperature T A - +12 C TABLE 2. 32C48B RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNIT Supply Voltage V CC 4.. V Ground V SS V Input High Voltage 1 V IH 2.2 V CC +. V Input Low Voltage 2 V IL -..8 V Thermal Impedance Θ JC.63 C/W 1. V IH (max) = V CC + 2.V ac(pulse width < 1) for I < 2mA. 2. V IL (min) = -2.V ac(pulse width < 1) for I < 2mA. TABLE 3. 32C48B DC ELECTRICAL CHARACTERISTICS (V CC =V +/- 1%, T A = - TO +1 2C, UNLESS OTERWISE SPECIFIED PARAMETER CONDITION SYMBOL SUBGROUPS MIN TYP MAX UNIT Input Leakage Current V IN = V SS to V CC I LI 1, 2, 3-2 2 µ A Output Leakage Current CS=V IH or OE=V IH or WE=V IL, V OUT =V SS to V CC I LO 1, 2, 3-2 2 µ A Output Low Voltage I OL = 8mA V OL 1, 2, 3.4 V Output High Voltage I OH = -4mA V OH 1, 2, 3 2.4 V Average Operating Current Standby Power Supply Current Input Capacitance 1 Min cycle, 1% Duty, CS=V IL, I CC 1, 2, 3 I OUT =ma, V IN = V IH or V IL CS = V IH I SB 1, 2, 3 6 ma f = MHz, CS > V CC - 2V, V IN > V CC -.2V or V IN <.2V 18 17 16 I SB1 1, 2, 3 1 V IN = V, f = 1MHz, T A = 2 C. C IN 1, 2, 3 7 pf Output Capacitance 1 V I/O = V C I/O 1, 2, 3 8 pf 1. Guaranteed by Design ma.2.2 Rev 7 2 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B TABLE 4. 32C48B AC CHARACTERISTICS FOR READ CYCLE (V CC =V +/- 1%, T A = - TO +1 2C, UNLESS OTERWISE SPECIFIED PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT Read Cycle Time t RC 2 2 3 Address Access Time t AA 2 2 3 Chip Select Access Time t CO 2 2 3 Output Enable to Output Valid Chip Select to Output in Low-Z Output Enable to Output in Low-Z t OE t LZ t OLZ 3 3 3 1 12 14 Chip Deselect to Output in High-Z t HZ 6 8 Output Disable to Output in High-Z t OHZ 6 8 Output Hold from Address Change t OH 3 Chip Select to Power Up Time t PU Chip Select to Power Down Time t PD 1 1 2.2.2 Rev 7 3 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B TABLE. 3248B FUNCTIONAL DESCRIPTION 1 CS WE OE MODE I/O PIN SUPPLY CURRENT H X X Not Select High-Z I SB, I SB1 L H H Output Disable High-Z I CC L H L Read D OUT I CC L L X Write D IN I CC 1. X = don t care. TABLE 6. 32C48B AC CHARACTERISTICS FOR WRITE CYCLE (V CC =V +/- 1%, T A = - TO +1 2C, UNLESS OTERWISE SPECIFIED PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT Write Cycle Time Chip Select to End of Write t WC t CW 2 2 3 14 1 17 Address Setup Time t AS Address Valid to End of Write t AW 14 1 17 Write Pulse Width (OE High) t WP 14 1 17 Write Recovery Time t WR Write to Output in High-Z t WHZ 6.2.2 Rev 7 4 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B TABLE 6. 32C48B AC CHARACTERISTICS FOR WRITE CYCLE (V CC =V +/- 1%, T A = - TO +1 2C, UNLESS OTERWISE SPECIFIED PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT Write Pulse Width(OE Low) t WP1 2 2 3 Data to Write Time Overlap t DW 9 1 11 End Write to Output Low-Z 1 tow 6 7 8 Data Hold from Write Time t DH FIGURE 1. TIMING WAVEFORM OF WRITE CYCLE(1) (OE CLOCK).2.2 Rev 7 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED) 1. All write cycle timing is referenced from the last valid address to the first traition address. 2. A write occurs during the overlap of a low CS and a low WE. A write begi at the latest traition among CS going low and WE going low: A write ends at the earliest traition among CS going high or WE going high. t WP is measured from beginning of write to end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write.. t WR is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pi are in the output low-z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applicatio, minimization or elimination of bus contention conditio is necessary during read and write cycle. 8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. D OUT is the read data of the new address. 1.When CS is low: I/O pi are in the output state. The input signals in the opposite phase leading to the output should not be applied. FIGURE 3. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED, CS = OE = V IL, WE = V IH ).2.2 Rev 7 6 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B FIGURE 4. TIMING WAVEFORM OF READ CYCLE (2) (WE = V IH ) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first traition address. 3. t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or V OL levels. 4. At any given temperature and voltage condition, t HZ(max) is less than t LZ(min) both for a given device and from device to device.. Traition is measured +2mV from steady state voltage with Load(B). This parameter is sampled and not 1% tested. 6. Device is continuously selected with CS = V IL. 7. Address valid prior to coincident with CS traition low. 8. For common I/O applicatio, minimization or elimination of bus contention is necessary during read and write cycle. FIGURE. SRAM HEAVY ION CROSS SECTION.2.2 Rev 7 7 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B FIGURE 6. SRAM PROTON SEU CROSS SECTION STATIC.2.2 Rev 7 8 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B 36 PIN FLAT RAD-PAK PACKAGE SYMBOL DIMENSION MIN NOM MAX A.122.13.148 b.1.17.19 c.8.1.12 D.93.94 E.638.64.62 E1.69 E2.6.6 E3..4 e. BSC L.39.4.41 Q.88.98.18 S1..32 N 36 F36-1 Note: All dimeio in inches.2.2 Rev 7 9 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B Important Notice: These data sheets are created using the chip manufacturers published specificatio. DDC verifies functionality by testing key parameters either by 1% testing, sample testing or characterization. The specificatio presented within these data sheets represent the latest and most accurate information available to date. However, these specificatio are subject to change without notice and DDC assumes no respoibility for the use of this information. DDC s products are not authorized for use as critical components in life support devices or systems without express written approval from DDC. Any claim agait DDC must be made within 9 days from the date of shipment from DDC. DDC's liability shall be limited to replacement of defective parts..2.2 Rev 7 1 216 Data Device Corporation
4 Megabit (12K x 8-Bit) SRAM 32C48B Product Ordering Optio Model Number 32C48B XX F X -XX Feature Access Time Option Details 2 = 2 2 = 2 3 = 3 Screening Flow Monolithic S = DDC Class S B = DDC Class B E = Engineering (testing @ +2 C) I = Industrial (testing @ - C, +2 C, +12 C) Package F = Flat Pack Radiation Feature RP = RAD-PAK package Base Product Nomenclature CMOS 12kword x 8-bit Static RAM.2.2 Rev 7 11 216 Data Device Corporation