Int. Journal of Applied Sciences and Engineering Research, Vol. 3, Issue 4, 2014 www.ijaser.com 2014 by the authors Licensee IJASER- Under Creative Commons License 3.0 editorial@ijaser.com Research article ISSN 2277 9442 Department of ECE, Dibrugarh University, India. DOI: 10.6088/ijaser.030400014 Abstract: In this paper, implementations of the flip-flops are presented which are level triggered and negative edge triggered using CMOS 180nm Technology. The gate sizes are optimized precisely for low delay propagation and low power dissipation without affecting the basic operation of the flip flops with a supply voltage of 1V. The designed D flip flop and SR flip flop dissipates power of 41.29nW and 24.9nW respectively whereas JK and T flip flops dissipates higher power of 6.51uW and 4.23uW which is because the number of MOS transistors increases for its implementation. There are three important factors in CMOS i.e the gate size area, power dissipation and speed of operation which always compromise between them when it is implemented in the field of IC circuit design. The main objective of this paper is to implement all the basic flip flops using CMOS transistors with voltage and Gate size scaling technique to reduce power dissipation without distorting the normal function of the basic flip flops. In any circuit design which is powered by a battery source, if the total power dissipation is low, the heat dissipation is also low which leads to more circuit reliability and durability without any circuit breakdown. Key words: Power dissipation, flip-flop, level and negative edge trigger, delay, master slave, W/L ratio. 1. Introduction Designing IC chip basically consists of a numerous numbers of logic gates which are integrated inside. Lowering the power dissipation of the circuit is always a big challenge to any circuit designer. Many related work has already carried out by different groups with different techniques. It is still a continuous work for circuit designer to design a very reliable circuit with very low power dissipation. There are different techniques for minimizing the power dissipation base on circuit level, architecture, layout, and process technology. Reasonable amount of circuit power savings can be attain at the circuit design level by properly choosing a logic style for implementing combinational circuits (Reto Zimmermann and Wolfgang Fichtner, July 1997). This is an effective approach as almost all the important parameters that govern power dissipation i.e. switching capacitance, transition activity, and short-circuit currents are strongly influenced by logic circuit choice. Using submicron technology, flip flop with less number of transistors for low power consumption is designed. In this method (B.Chinnarao, B.Francis and Y.Apparao, 2012) they used less number of transistors hence it required less area and therefore consumes lesser power as compare to conventional flip flops having more transistors. By Gate diffusion input technique power dissipation from the flip flop can also be reduced and moreover it can speed up the response of the flip flop. Using this technique (Soheil Ziabakhsh and Meysam Zoghi, 2009), they have designed high speed T F/F which operate at the speed of psec and consumed power at uw. Another conventional way but rather effective technique is by scaling down both the supply voltage and the gate size dimension i.e W/L ratio of MOS transistor. In CMOS device the total power is the summation of two powers i.e. dynamic power and static power. As these powers depend upon VDD at large, the total power can be minimize if supply voltage is reduced. The main objective of this paper is the reduction of power dissipation of CMOS flip flops by voltage reduction technique. *Corresponding author (e-mail: pipizs.kaps@gmail.com) 899 Received on March 28, 2014; Accepted on April 18, 2014; Published on August 30, 2014
2. General review of total power consumption in CMOS The basic equation governing the total power in CMOS device is given by PTotal = Pdynamic + Pstatic PTotal = ½ C LVDD 2 f + IscVDD + IstaticVDD (1) where C L is the load capacitance, f is the frequency of operation, is the activity factor, Isc is the short circuit current. This basic equation which govern CMOS power is given by (N. Geetha Rani, N. Praveen Kumar, Dr. B. Stephen Charles, Dr. P. Chandrasekhar Reddy, S.Md.Imran Ali, 2012) and (Subodh Wairya, Rajendra Kumar Nagaria, and Sudarshan Tiwari, 2012). The equation (1) shows that both the powers depend on the supply voltage VDD i.e. both are directly proportional to supply voltage. The discharging and charging of the capacitance and short circuit current mainly constitute the dynamic power consumption. When the pull down and pull up networks in a CMOS circuit at some instant are on simultaneously, the short circuit current flows as there exists a direct path from the supply voltage to ground. So this dominating power i.e the Dynamic power is proportional directly to the square of V DD. Hence when the supply voltage is reduced the dynamic power also reduces in a quadratic manner. If the supply voltage VDD is reduced the total power dissipation in the CMOS circuit can be reduce tremendously. The aim of this work is to design flip flops circuit with CMOS technology by scaling down the size of MOS transistor and VDD such that the total power dissipation is reduced without distorting the basic flip flops output.. 3. Circuit implementation The four basic flip flops (F/F) family includes SR F/F, D F/F, master slave JK F/F and T F/F. All the circuits are simulated with a supply voltage VDD of 1V. For simulation purpose input bits are string of bits such that each of the bits with 1V magnitude corresponds to high logic state i.e logic 1 and the ground state corresponds to logic 0. Logic 1 state has equal rise and fall time of 5 psec each. Simulation is done at a bit frequency of 50 MHz except D flip-flop which is at 100 MHz and with different clk frequencies for all the flip flops. 3.1 Clock SR latch In synchronous operation of the circuit, controlling the response of the circuit is obtained by applying a gating clock signal. When the clock pulse is in active high state the outputs will respond to the input levels which are called a level triggered circuit. The clocked NOR-based SR latch is shown in Figure 1. When the clock (Clk) takes the value of logic 0, the output is independent of input signals which mean the SR latch will hold its present output state. But when the clock input switch to logic 1, the inputs applied to the S and R inputs are allowed to accept to the SR latch (G. K. Kharate, 2010, 1 st Edition). Figure 2 shows a CMOS implementation of a clocked NOR-based SR latch circuit. Table 1 shows the working operation of the SR flip flop with different combination of S and R input. When both the inputs are logic 1 output is indeterminate whereas if both inputs are logic 0 it holds the present state. The output will set only when S input is logic 1 otherwise it will reset. The circuit is strictly level-sensitive during active phases only (i.e. any changes occurring in the S and R input voltages when CK level is equal to logic 1 will be reflected in the circuit outputs as shown in Table 1). 900
1. 1 - - clk rsff Time (us ) clk rsff Time (us ) clk rsff Time (us ) clk rsff Time (us ) v( cl k ) v( S) v( R) Figure 1: Clocked NOR based SR latch Figure 2: CMOS implementation of the clocked NOR-based SR latche circuit. Table 1: Circuit outputs Simulation of the circuit is carried out with bits stream R (0100) and S (100) with bit frequency of 50 MHz and the clock signal at 6.25 MHz with a supply voltage of 1V. The circuit current is only 24.9nA and power dissipation is 24.9nW which is acceptably very low. From the simulation waveform, output will holds its current value when the clock signal becomes zero or when both inputs are logic 0. From top in Figure 3 the first waveform is the clock cycle, the second is the output Q, the third is S input and the fourth is R input. Figure 3: Simulation result output waveform of clock SR F/F 901
3.2 Clocked D flip flop The gate level representation of the D-latch is simply obtained by modifying the clocked NOR-based SR latch circuit. It can be seen from Figure 4 that the output Q assumes the value of the input D when the clock is active (i.e. for Clk= 1 ). When the clock signal goes to zero, the output will simply preserve its present state. Thus, the Clk input acts as an enable signal which allows data to be accepted into the D-latch as stated by (M Moriss Mano, 1997, 1st Edition). The operation of D flip flop is shown in Table 2. Figure 4: Gate level D flip-flop Figure 5 is the implementation of the CMOS D-latch. The circuit contains two tri state inverters, driven by the clock signal and its inverse. The first tri-state inverter acts as the input switch, accepting the input signal when the clock is high. At this time, the second tri state inverter is at its high impedance state, and the output Q is following the input signal. When the clock goes low, the input buffer becomes inactive, and the second tri state inverter completes the two inverter loop, which preserves its state until the next clock pulse. Figure 5: CMOS implementation of D flip-flop Table 2: Operation table Here simulation of the circuit is carried out with input D which is a bit of stream (0101) at bit frequency 50 MHz and clock frequency at 100 MHz of 1V magnitude with supply voltage of 1V. The circuit current is 41.29nA and the power dissipation is of 41.29 nw. The resultant simulation waveform of the clk, output and input waveform is shown in Figure 6. 902
1.0 0.0 1.0-0.0-0.1 1.0 0.0 D ff 0.0 1.0 D ff 0.0 1.0 D ff 0.0 1.0 v( clk ) v( D) Figure 6: simulation result of D flip-flop 3.3 Master slave JK flip flop Figure 7 shows two cascaded NAND based latches activated with opposite clock phases. This configuration is referred to as a master-slave flip-flop configuration. The input latch is the first stage and is called the master and it is activated when the clock pulse is high. During this phase, the inputs J and K allow data to be entered into the flip-flop. When the clock pulse goes to zero, the master latch becomes inactive and the second-stage latch, called the slave becomes active. According to ( M. Morris Mano, 1997, 1 st Edition)The output levels of the flip-flop circuit are determined during this second phase, based on the master-stage outputs set in the previous phase. An important property of master-slave flip-flop is that at any point of time, a change occurring in the primary inputs is never reflected directly to the outputs. Figure 7: Master slave JK flip-flop When implementing the above Figure 7 which is all NAND based it require 36 MOS transistor as shown in the Figure 8. This master slave is a negative edge trigger which means the output will change on the trailing edge of the clock. Figure 8: Implementations of master slave JK flip flop 903
1.10 1.05 1.00 5 0 1.0 0.0 1.0 0.0 1. 5 1. 5 1. 5 1. 5 0.0 1.0 1.5 0.0 1.0 1.5 0.0 1.0 1.5 c lk jk ff c lk jk ff c lk jk ff c lk jk ff v( cl k ) v( J) v( k) v( T) v( cl k ) Table 3: Operation table The operation table of negative edge triggers JK flip flop is shown in Table 3. Simulation is carried out of bit streams J (011101101) and K (0101101) with bit frequency of 25 MHz and clock frequency of 50 MHz. 1V corresponds to logic 1 and 0V corresponds to logic 0. The Vdd supply of the circuit is only 1V. From the simulation result the total current is found to be 6.51uA and the power dissipation is 6.51uW. The waveform of the master slave JK flip flop is shown in Figure 9. From top of the waveform the first waveform corresponds to output Q, the second is the clock cycle and the last two are J and K inputs respectively. Figure 9: Simulation result of master slave JK flip-flop 3.4 T flip flop The T-type flip-flop is simply a JK flip-flop with the J and K connected to the same input T which can be either logic 1 or logic 0 (G. K. Kharate, 2010, 1 st Edition). If T takes the value of logic 1, the output Q will then change state on trailing edge, which will result in a waveform with a frequency one half of the applied clock as shown in Figure 10. The CMOS implementation of T flip flop is shown in Figure 11 where both J and K input are tied to common input i.e T input. Vol tage (V) Volt age (V) Vol tage (V) Figure 10: Output waveform with a frequency one half of the applied clock 904
0.0 1. 0 1. 5 0.0 1. 0 1. 5 0.0 1. 0 1. 5 v( T) v( clk ) When a stream of random bits of 0 and 1 are given to T input, on the negative edge of the clock cycle it will toggle the output if T takes value of logic 1 else it will holds the present value as shown in table 4. Table 4: Operation table Figure 11: CMOS implementation of master slave negative edge trigger T flip flop The circuit simulation is carried out at clock frequency of 50MHz with T bit stream (11100010) and a supply voltage Vdd of 1V. The circuit current is 4.23uA and power dissipation in 4.23uW. The output, input and clock waveform is shown in simulation result Figure 12. Table.5 shows all result the basic flip flops which is simulated with 1V supply voltage. JK and T flip flops dissipates power in uw range which is higher than SR and D flip flop as number of CMOS transistor increase to implement the circuit. Table 5: Summary of Ckt current and power dissipation of all the flip flops Flip flop Vdd current power Propagation delay SR 1V 24.9nA 24.9nW 0.02usec D 1V 41.29nA 41.29nW 0.01usec JK 1V 6.51uA 6.51uW 0.02usec T 1V 4.23uA 4.23uW 0.04usec Figure 12: Simulation result of master slave T flip-flop 905
4. Conclusions CMOS 180nm technology is used for implementing the MOS transistors and the software used for simulating the circuits is TANNER software. Under power dissipation constrain, the gate size of the MOS device is optimized precisely for faithful output. By minimizing the supply voltage VDD down to 1V the dissipation of circuit power can thus be reduce considerably. From the simulation result SR & D flip flop dissipates in the range of nano-watt but for JK & T flip flop it dissipate in micro-watt range as the number of transistors increases for the circuit implementation. The summery of all the total current and power for each of the flip-flop is also shown in Table 5. As the circuit supply voltage VDD is directly proportional to power dissipation, lowering the supply voltage imply less power dissipation. Scaling down the Gate s dimension i.e W/L of the transistor at appropriate proportion, the power dissipation of the flip flops are thus minimized without distorting the overall circuit outputs as shown in the entire simulation waveform 5. References 1. Reto Zimmermann and Wolfgang Fichtner. Low-Power Logic Styles: CMOS versus Pass Transistor Logicǁ IEEE Journal of solid-state circuits, 32(7), pp.1079-1090. 2. Chinnarao, Francis and Apparao, 2012. Design of a low power flip-flop using CMOS deep submicron technology, International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231-5969, 2(1), pp. 99-103. 3. Soheil Ziabakhsh and Meysam Zoghi, 2009. Design of a Low-Power High-Speed T-Flip-Flop Using the Gate-Diffusion Input Technique, 17th Telecommunications forum TELFOR 2009, Serbia, Belgrade, November 24-26, pp.1470-1473. 4. Geetha Rani, Praveen Kumar, Stephen Charles, Chandrasekhar Reddy, S.Md.Imran Ali, 2012. Design of Near- Threshold CMOS Logic Gates, International Journal of VLSI design & Communication Systems, 3(2), pp. 193-201. 5. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, 2012. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits for Low Voltage VLSI Design International Journal of VLSI design and Communication Systems, 3(2), pp. 221-242. 6. Kharate G. K., Digital Electronics, Oxford university press, 2010, 1sh Edition, ISBN 13:978-0-19-806183-0. 7. Morris Mano M. 1979. Digital Logic and Computer Design Prentice-Hall of India, Eastern Economy Edition, 1th Edition, ISBN 81-203-0417-9 906