A VHDL-AMS Simulation Methodology for Tranient Supply Current Extraction Richard Perdriau */**, Damien Lambert */***, Anne-Marie Trulleman **, Mohamed Ramdani * and Jean-Luc Levant *** * Ecole Supérieure d Electronique de l Ouet 4, rue Merlet-de-la-Boulaye - BP 926-49009 Anger Cedex 01 - France ** DICE - Laboratoire de Microélectronique - Univerité Catholique de Louvain Place du Levant, 3-1348 Louvain-la-Neuve - Belgium *** ATMEL La Chantrerie - Route de Gachet - 44000 Nante - France Correponding author : Richard Perdriau Tel. (33/0) 2 41 86 67 03 - E-mail : richard.perdriau@eeo.fr Abtract Tranient upply current extraction play a very important role in etimating performance level in the IC EMC field. A far a complex circuit uch a microcontroller are concerned, tranitor-level (SPICE-baed) imulation lead to very long CPU time, mainly becaue of memory array which often repreent more than 80 % of the tranitor in a µc. A convenient way of cutting out imulation time i to decribe memorie at the behavioral level, while keeping the microcontroller core itelf at the tructural level. In the firt tep, the dynamic upply current conumption of the microcontroller core alone i imulated by coupling purely digital (VITAL) VHDL model for Flah and RAM block to the tranitor-level core. The next tep conit in adding VHDL-AMS behavioral model of the conumption of the memory block themelve to the VITAL decription. Thi allow the deigner to imulate the whole microcontroller without dramatically increaing imulation time. Thi work i upported by the MESDIE project and complie with the ICEM propoal. 1 Introduction When deigning complex integrated circuit uch a microcontroller (µc), extreme care mut be taken about their compliance to electromagnetic compatibility (EMC) rule; in fact, the later thee rule are taken into account in the deign phae, the more non-recurrent engineering (NRE) cot may increae, at firt becaue of foundry cot. Therefore, a methodology allowing the deigner to predict conducted emiion level before ending the deign to the foundry would be of great interet. The recent Integrated Circuit Electromagnetic Model (ICEM) propoal [5], repreented in figure 5, ue an equivalent current generator to model internal activity. Conequently, extraction of dynamic upply current by the mean of imulation diplay an accurate image of thi activity; even if only one given activity i needed in the propoal itelf, being able to provide oftware-dependent current open new perpective. The firt idea coming to mind in order to obtain intantaneou current i to perform a tranitor-level imulation on the complete netlit, uing SPICE-like tool. However, many microcontroller include on-chip, Flah EPROM and/or EEPROM. Thee memory block often contain many more tranitor than the CPU core itelf; hence, imulating million of tranitor at SPICE level would be tediou and time-conuming. Moreover, EMC tudie do not require a much accuracy a the one provided by thee imulation; indeed, reult might be acceptable when the dicrepancy between imulation reult and meaurement i a high a 20 %. On the contrary, many author have already demontrated the advantage of behavioral imulation model over tructural one for complex ytem, mainly in term of imulation time. For that purpoe, many high-level, mixed-ignal language have been developed in the lat decade, including HDL-A, MAST and more recently VHDL-AMS and Verilog-AMS. Nonethele, a i well known, microcontroller core mod-
el are written in purely digital VHDL or Verilog in order to be yntheized; in addition, VITAL (VHDL Initiative Toward ASIC Librarie) behavioral model of memory block are often available. In fact, VITAL i a tandard (IEEE 1076.4-1995, enhanced in 1999) which (among other feature) allow memory read/write operation to be imulated in VHDL, including timing and path delay. The ue of a imilar, compatible modeling language eem thu to match the requirement of a global imulation. VHDL-AMS, decribed in [1], i a mixed-ignal, multitechnology extenion to VHDL, covering variou domain including electronic, mechanic and optic. Moreover, purely digital VHDL model may be imported, compiled and imulated with no modification, and furthermore the available tet model are written in VHDL. Nonethele, the ICEM propoal allow the deigner to pecify the equivalent generator quoted above a a VHDL-AMS decription. Therefore, it eemed that the VHDL-AMS language wa bet uited to our application. Conequently, thi paper introduce another technique, baed on mixed-level (behavioral and tructural) imulation, which may eventually reduce CPU time in a ignificant way, while preerving enough accuracy to meet the goal of an EMC-oriented tudy. 2 Preentation 2.1 The methodology From what ha jut been tated, we can ugget a 3-tep proce in order to model the equivalent upply current generator of a microcontroller. At firt, the equivalent upply current of the core can be extracted by uing a tranitor-level netlit of the core alone; thi can be obtained after either the ynthei tep (netlit with active device only) or the RC extraction tep (netlit with detailed paraitic depending on floorplanning and routing). Thi netlit can then be coupled with digital-only, VITAL VHDL model of the memory block by the mean of analog-to-digital and digital-to-analog converter pecified in VHDL-AMS; in addition, a given executable code can be taken into account by the (E)(E)PROM model, driving data pin according to it content. Thi proce i depicted on figure 1. Obviouly, thi imulation doe not include the current conumed by the memory block, but allow u to validate the method and the tool. The econd tep conit in performing an analyi of the current conumed by the memory block themelve, and then trying to find a VHDL-AMS behavioral model of thi current. Eventually, thee model may be coupled with the core netlit in the ame manner, thu giving the whole tranient upply current (figure 2). Of coure, previou VITAL code MEMORIES VITAL (VHDL) (E)(E)PROM A2D D2A CORE tructural netlit (.CIR) Figure 1. Simulation etup with VITAL memory model model may be re-ued a far a the digital behavioral part i concerned, ince VHDL-AMS i upward-compatible. code MEMORIES VHDL-AMS (E)(E)PROM A2D D2A CORE tructural netlit (.CIR) Figure 2. Simulation etup with VHDL-AMS memory model Memory activity may not repreent a ubtantial part of the current conumed by imple (8 or 16-bit) microcontroller; however, more complex (32-bit) microproceor alway include cache memorie, which are acceed at every clock cycle or o. Conequently, thee may play more important a role in the total conumption of thoe high-performance device. 2
The final tudy (and the mot difficult one) might reult in a global VHDL-AMS model of the current conumed by the core depending on it activity (intruction, input/output port). Obviouly, thi hould lead to far horter imulation time, but at the expene of further theoretical reearch (figure 3). code MEMORIES VHDL-AMS (E)(E)PROM CORE behavioral model VHDL-AMS Figure 3. Simulation etup with full VHDL-AMS model 2.2 Example : current generator in VHDL-AMS In order to better demontrate the interet of the VHDL- AMS language, a cloely related example will be examined. The ICEM model pecifie an equivalent piece-wie linear (PWL) current generator for the chip itelf; therefore, a generic VHDL-AMS behavioral model of thi generator wa written, which i introduced below. (I,t) value are obtained from two real vector, the yntax of which complie with the SPICE/Eldo definition. - PWL current generator - Ti(0) = 0 LIBRARY DISCIPLINES; USE DISCIPLINES.ELECTROMAGNETIC_SYSTEM. ALL; ENTITY IbPWLGenerator IS GENERIC (Ti : real_vector; Ii : real_vector); PORT (TERMINAL Vdd_n2, V_n2 : electrical); END ENTITY IbPWLGenerator; ARCHITECTURE a OF IbPWLGenerator IS QUANTITY Vb ACROSS Ib THROUGH V_n2 TO Vdd_n2; SIGNAL Itart : real := Ii(Ii low); SIGNAL Ttart : real := 0.0; SIGNAL Tend : real := Ti(Ti low+1); SIGNAL deltai : real := Ii(Ii low+1)-ii(ii low); BEGIN ASSERT Ti(Ti low) = 0.0 REPORT "Error : Ti(Ti low) hould be equal to 0.0." SEVERITY ERROR; ASSERT Ii(Ii high) = Ii(Ii low) REPORT "Error : firt and lat I value hould be the ame." SEVERITY ERROR; PROCESS VARIABLE PeriodStart : real := 0.0; BEGIN LOOP FOR n IN Ti low+1 TO Ti high LOOP Itart <= Ii(n-1); deltai <= Ii(n)- Ii(n-1); Ttart <= PeriodStart + Ti(n-1); Tend <= PeriodStart + Ti(n); WAIT FOR Ti(n)-Ti(n-1); END LOOP; PeriodStart:=PeriodStart + Ti(Ti high); END LOOP; END PROCESS; IF domain = quiecent_domain USE Ib == Itart; ELSE Ib == Itart + deltai * (now-ttart)/(tend-ttart); END USE; BREAK ON Ttart; END ARCHITECTURE a; Thi example how the trong relationhip between event defined within a proce in the "digital" domain, and analog olution point (ASP) in the analog domain; moreover, it demontrate VHDL-AMS implicity (the model i nothing but an implementation of a plain linear interpolation algorithm). 3
3 Validation and reult 3.1 Simulation with VITAL model Core imulation : red = 200-p tr, green = 5-n tr A I(R_VCCCORE1)_51:1 I(R_VCCCORE1)_51:2 0.025 0.020 0.015 The validation of the methodology propoed above wa carried out on a 8051 microcontroller core from Atmel (DIVA project), including a 32KB code EEPROM and 2 data (1KB and 256B); the core repreent about 25000 equivalent NAND gate, both repreent about 18000, and finally, the EEPROM alone repreent more than 150000... The toolet ued wa ADVance-MS Mach from Mentor Graphic. ADVance-MS i a VHDL-AMS tool baed on the Eldo imulation core, which i very accurate but very low for 100000-tranitor netlit; on the contrary, Mach i deigned for million-tranitor netlit and thu much fater (10 to 12 time), but at the expene of accuracy. ADVance- MS Mach i claimed to combine both core in a unique environment. Unfortunately, ADVance-MS former releae (1.5 at the time thi article wa initially written) did not allow coupling between VHDL-AMS model and the Mach core, becaue of non-functional A/D and D/A converter; conequently, an Eldo imulation had to be performed intead. It lated about 80 hour (on a dual-proceor Sun Blade 1000 worktation) for only 1 µ imulated time; thu, only the RESET phae could be tudied. Much time wa wated with thi releae before receiving the latet one (1.6) in October 2002. Finally, we managed to perform an ADVance-MS Mach imulation with two different et of rie and fall time for the XT AL1A clock ignal (200 p in red and 5 n in green). The reult are diplayed in figure 4, in which I R_V CCCORE repreent the current flowing in the power upply line of the core, and I R_V CCBUF the ame for the I/O buffer. Delay time depend on clock rie and fall time, a tated in Hirata work [2]; conequently, the internal clock generator play an important role in the correlation between imulation and meaurement; for thi reaon, the ability to imulate the clock generator (with it added complexity) with the ret of the core hould ignificantly increae the validity of the reult. Moreover, thi imulation cover only the RE- SET tate, and general rule may not be inferred from uch a hort equivalent time. However, it can be een that peak value of the current generated on the core power line are four time a high a the one generated on the I/O buffer power line (25 ma intead of 6 ma). Thi method hould be validated a oon a poible. For that purpoe, the ICEM model may be ued; a chematic of the power upply line model i preented in figure 5. Previou reearch decribed in [3] proved the validity of uch a model in "low" frequency band (below 2 GHz). Since lumped element were perfectly identified for our mi- 0.010 0.005 0.000-0.005-6 2.4 2.5 2.6 2.7 2.8 2.9 3.0e-7 A I(R_VCCBUF1)_50:1 I(R_VCCBUF1)_50:2 6e-3 4 2 0-2 -4-0.5 2.4 2.5 2.6 2.7 2.8 2.9 3.0e-7 V V(XTAL1A)_1:1 V(XTAL1A)_1:2 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.5 2.6 2.7 2.8 2.9 3.0e-7 Figure 4. Simulation of the core in the RESET phae Rp V DD Lp V DD M Rp V SS Lp V SS R V DD C d R V SS L V DD C b L V SS Figure 5. The ICEM model for upply line I b crocontroller, the predicted external current can be computed by imulating the core (repreented by I b ) with thee additional element, and thu thee reult can be correlated with external current meaurement. However, the effect of internal paraitic element (reulting from the place-and-route tep) are not included at thi time, and a method for DSPF (Detailed Standard Paraitic File) import in ADVance-MS Mach i currently being invetigated (compatibility iue between format ued by CAD tool). 4
3.2 Simulation with tranitor-level memorie In order to validate the mixed-ignal imulation concept, the impler memory block wa choen, i.e. the. For that purpoe, an intereting approach of power conumption iue i propoed by Saillé [4]. Even if only energy (and not tranient ignal) i addreed, the article clearly demontrate the role of each building block (including addre decoder, cell, ene amplifier). The correponding current waveform hould thu depend on ucceive addree a well a on memory content. In order to tate thi, the tranitor-level netlit wa driven by a VHDL digital tetbench browing every decoded addre, a hown in figure 6. imulation : red = 200-p tr, green = 5-n tr A I(VDD)_20:2 I(VDD)_20:1 0.005 0.000-0.005-0.010-0.015-0.020-0.025 VHDL tet bench A2D D2A tructural netlit (.CIR) -0.030-0.035 2.558 2.556 2.560 2.554 2.562 2.552 2.564e-5 tet_ramv:ytetbench:add_23:2 x1fe x1ff x200 2.554 2.558 2.562 2.556 2.560 2.552 2.564e-5 tet_ramv:ytetbench:me_25:2 2.558 2.556 2.560 2.554 2.562 2.552 2.564e-5 Figure 7. Simulation of accee Figure 6. Setup for tranitor-level imulation For that purpoe, two different et of rie and fall time for incoming ignal (200 p in red and 5 n in green) were choen, in order to better demontrate the influence of thi parameter on the amplitude and timing of the generated current. The reult are diplayed in figure 7 for two given accee (addre $1FF after $1FE, addre $200 after $1FF) differing by the number of witching bit (1 then 10) between ucceive addree. ME repreent the active-high memory enable (chip elect) ignal. On thee imulation, two different current pule for each acce can be clearly een : a firt pule which may correpond to addre decoding; a can be een, it amplitude widely depend on the Hamming ditance between ucceive addree, which i an expected reult; moreover, both it amplitude and rie time depend on the rie time of the addre ignal. a econd pule which hould correpond to the memory cell themelve; it hape depend neither on the addre itelf, and mot remarkably, nor on rie/fall time of the incoming control ignal; however, the delay between the tranition of the MemoryEnable ignal and the pule itelf depend on rie/fall time of thi control ignal, which i a general reult already quoted in [6]. Moreover, peak value are nearly the ame order of magnitude a the one of the current generated by the core (i.e. 25 ma, ee previou ection), which how that memory accee hould not be omitted in a global imulation of a microcontroller. The influence of memory content till remain to be tudied. However, a few concluion may be inferred from thee reult : the reulting VHDL-AMS model hould be parameterized by rie and fall time of the incoming ignal, or converely include a tet bench meauring thee characteritic the addreing cheme play a very important role in the the dynamic current frequency pectrum, and will be of coure included in the model 5
A a general reult, adjuting rie and fall time (by deign or place-and-route) of addre and control ignal might help to deynchronize current pule generated by the core and it aociated memorie, thu reducing the amplitude of ome frequency component in the reulting pectrum and conequently improving EMC performance. [6] S.J.E. Wilton and N.P. Jouppi. An enhanced acce and cycle time model for on-chip cache. Digital WRL reearch report 93/5, Digital Equipment Corporation, July 1994. 4 Concluion Thi paper ugget a methodology for extracting power upply current in a microcontroller by uing mixed-mode imulation. For thi purpoe, the ue of the VHDL-AMS language, permitting high-level memory modeling, i propoed. Thi methodology i about to be validated by meaurement on the core, but thi operation wa delayed becaue of improper operation of the CAD tool ued at that time. However, the reult obtained on block how the feaibility of a dynamic current conumption macromodel. Our immediate objective, which hould be met at the end of year 2002, are : the incluion of RC paraitic in core imulation the validation of core imulation by the mean of meaurement coupled with the ICEM model the development of the behavioral model of the intantaneou current conumed by memory block Thee reult may provide guideline for EMC-oriented microcontroller deign. Reference [1] E. Chriten, K. Bakalar, A.M. Dewey, and E. Moer. Analog and mixed-ignal modeling uing the VHDL- AMS language. In 36th Deign Automation Conference, June 1999. [2] A. Hirata, H. Onodera, and K. Tamaru. Etimation of propagation delay conidering hort-circuit current for tatic CMOS gate. IEEE Tranaction on Circuit and Sytem, CAS-45(11):1194 1198, November 1998. [3] J.L. Levant, M. Ramdani, and R. Perdriau. ICEM modeling of microcontroller current activity. In Submitted to EMC Compo 2002, September 2002. [4] D. Saillé, D. Chillet, and O. Sentiey. Modéliation de la conommation pour le mémoire. In FTFC 01, page 27 33, 2001. [5] IEC EMC Tak Force. IEC62014-3 : Integrated circuit electromagnetic model. Draft technical report, IEC, November 2001. http://intrage.inatle.fr/ etienne/emc/icemcdv.pdf. 6