A Low Power Dgtal Phase Locked Loop Wth ROM-Free Numercally Controlled Oscllator M. Saber mohsaber@tsubak.csce.kyushu-u.ac.jp Department o Inormatcs Kyushu Unersty 744 Motooka, Nsh-ku, Fukuoka-sh,89-395,Japan Y. Jtsumatsu jtsumatsu@n.kyushu-u.ac.jp Department o Inormatcs Kyushu Unersty 744 Motooka, Nsh-ku, Fukuoka-sh,89-395,Japan M. T. A. Khan tahr@apu-u.ac.jp Rtsumekan Asa Pacc Unersty, College o Asa Pacc Studes - Jumonjbaru, Beppu, Ota, 874-8577, Japan Abstract Ths paper analyzes and desgns a second order dgtal phase-locked loop (DPLL), and presents low power archtecture or DPLL. The proposed archtecture reduces the hgh power consumpton o conentonal DPLL, whch results rom usng a read only memory (ROM) n mplementaton o the numercally controlled oscllator (NCO). The proposed DPLL utlzes a new desgn or NCO, n whch no ROM s used. DPLL s desgned and mplemented usng FPGA, consumes 37 mw, whch means more than 5% sang n power consumpton, and works at aster clock requency compared to tradtonal archtecture. Keywords: Dgtal Phase locked loop (DPLL), Feld Programmable Gate Array (FPGA), Sotware Dened Rado (SFDR), Read Only Memory (ROM), Spurous Free Dynamc Range (SFDR).. INTRODUCTION Sotware Dened Rados (SDRs) are leadng the ntegraton o dgtal sgnal processng (DSP) and rado requency (RF) capabltes. Ths ntegraton allows sotware to control communcatons parameters such as the requency range, lterng, modulaton type, data rates, and requency hoppng schemes. SDR technology can be seen n wreless deces used or derent applcatons n mltary, cl applcatons, and commercal network. Compared to conentonal RF transceer technologes, the adantage o SDR s ts lexblty. SDR prodes the ablty to recongure system perormance and unctons on the ly []. In order to take adantage o such dgtal processng, analog sgnals must be conerted to and rom the dgtal doman. Ths s done usng analog-to-dgtal (ADC) and dgtal-to-analog (DAC) conerters. To take ull adantage o dgtal processng, SDRs keep the sgnal n dgtal doman as much as possble, dgtzng and reconstructng as close as possble to the antenna. Despte an ADC or DAC connected drectly to an antenna s a requred end goal, there are ssues wth selectty and senstty that need an analog ront []. Phase-locked loop (PLL) s one o the most mportant buldng blocks necessary or modern dgtal communcatons, whch s used as a requency syntheszer n RF crcuts, or to recoer tme and carrer n the baseband dgtal sgnal processng. A complete understandng o the concept o PLL ncludes many study areas such as RF crcuts, dgtal sgnal processng, dscrete tme control systems, and communcaton theory [3]. Tradtonal PLL conssts o three parts; phase requency detector (PFD), loop lter, and oltage controlled oscllator (VCO). Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 4
The tradtonal analog PLL aces many desgn problems such as oltage supply nose, temperature nose, and large area consumed by loop lter components lke resstors and capactors. On the other hand DPLL, ormed o all dgtal components, prodes a hgh mmunty to supply oltage nose and temperature araton. Moreoer, DPLL can be desgned by usng hardware descrpton language (HDL) wth any standard cell lbrary. Thus, the tme or redesgn and check or errors s reduced. Thereore, DPLL prodes a good soluton to analog PLL desgn problems. Unortunately, DPLL has a crtcal dsadantage,.e., hgh power consumpton resultng rom the numercally-controlled oscllator (NCO) [4]. The hgh power consumpton o NCO s the result o usng ROM, whch contans the sampled ampltudes o a snusodal waeorm. As accuracy o the generated sgnal ncreases, the sze o ROM ncreases, whch causes hgh power consumpton and reduces the speed o the crcut. We propose a DPLL archtecture n whch the tradtonal NCO s replaced by a crcut whch generates a cosne waeorm usng a pecewse-lnear approxmaton. In secton, PLL operaton s explaned. The tradtonal NCO s descrbed n secton 3. Secton 4 llustrates a moded NCO whch can sole the problems o tradtonal NCO. In secton 5 mathematcal model o DPLL n both Z-doman and S-doman s llustrated. In secton 6 smulaton results. In secton 7 hardware mplementaton o moded NCO and moded DPLL s presented and n the end some conclusons are gen.. PHASE LOCKED LOOP PLL s an mportant component n many types o communcaton systems. It works n two derent manners; to synchronze a carrer n requency and phase or to operate as a syntheszer. The block dagram o DPLL s shown n Fg.. It conssts o three man blocks, phase/requency detector (PD), loop lter and NCO. Input sgnal (n), ω (n), θ (n) Phase/ Frequency Detector (n), ω ± ω, θ ± θ d Loop Flter Generated synchronzed sgnal (n), ω, θ NCO (n), ω ω, θ θ FIGURE : Dgtal phase locked loop n dscrete tme doman. The operaton o DPLL s as ollows: wthout nput sgnal appled to the system, NCO generates a sgnal wth a center requency ( c ), whch s called the ree runnng requency. The nput sgnal appled to the system s (n) = A sn( ω n + θ ), () where A s the ampltude, ω s the angular requency, and θ s the phase o the nput sgnal. Feedback loop mechansm o PLL wll orce NCO to generate a snusodal sgnal (n) (n) = A sn( ω n + θ ), () o Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 43
where Ao s the ampltude, θ generated by NCO. s gen by N = ω s the angular requency and θ s the phase o the sgnal θ (n) = k (), (3) where k s the NCO gan constant and (n) s the lter output. I k m denotes the phase detector (multpler) gan, then output o the phase detector s kmaao d(n) = sn( ω n + θ )cos( ω n + θ ) kmaa o [sn(( ) n ) sn(( ) n ], = ω + ω + θ + θ + ω ω + θ θ (4) The rst term n (4) corresponds to hgh requency component, and the second term corresponds to the phase derence between (n) and (n). Loop lter wll remoe the rst term n (4). I ω = ω, then phase derence can be obtaned as (n) = k [sn( θ θ )], (5) d where k k A A m o d =. I ( θ θ ), then V (n) s approxmated by kdaao (n) ( θ θ ). (6) Ths derence oltage s appled to the NCO. Thus, the control oltage (n) orces the NCO output requency to change up or down to reduce the requency derence between ω and ω. The equaton o the generated requency o NCO s ω (n) = ω + (n), (7) c where ωc s the center requency o NCO. I the nput requency ω s close to ω, the eedback manner o PLL causes NCO to synchronze or lock wth the mng sgnal. Once t s locked, the generated sgnal o NCO wll synchronze the nput sgnal n phase and requency. 3. TRADITIONAL NCO Voltage Controlled Oscllator (VCO), whch s used n analog PLL generates a snusodal waeorm whose requency depends on the nput oltage. NCO, whch s used n DPLL, generates a dgtal (sampled) snusodal waeorm wth a undamental requency determned by the dgtal nput alue (n-bts). As shown n Fg., NCO conssts o ROM, and accumulator. The output sgnal o the accumulator s used as address to the ROM. The nput sgnal to the accumulator conssts o the sum o an oset ( ω c ) correspondng to the ree runnng requency, and whch s the output o the loop lter [5]. The general equaton o generated requency rom NCO s = ( + ω j c ) clk. (8) where s the generated requency, ω c s the center requency, s an nteger alue and les n j j the range ( ), j s number o bts or wdth o the accumulator, whch s 6 bts, and s the clock requency. clk Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 44
The operaton o NCO s as ollows: rst assumng that the system clock requency s 5MHz, j=6 and ω c = 3, the ree runnng requency s MHz. Then, as shown n Fg. 3 there are 5 samplng ponts n one cycle o MHz snusodal waeorm. NCO generates exactly one cycle o snusodal waeorm when the nput alue ( ) s equal to zero. Snce the oset alue s 3, eery clock cycle the accumulator accumulates the oset alue. Then n 5 cycles the accumulated alue wll ncrease by one. The accumulator output wll address ths alue to the ROM and extract the cosne ampltudes alues stored n t. When the nput alue s greater than zero, the accumulaton speed becomes hgher. Thus n less than 5 cycles o clock requency the accumulator ncreases by, ths wll generate a hgher requency than MHz. When the nput alue s less than, a requency lower than MHz s generated. The problem wth usng a ROM s that, ts sze ncreases to achee a hgh spectral purty o the generated waeorm. Ths leads to hgh power consumpton and slow operaton o the system. Cos Waeorm Cos ROM ω c D Q Clock Delay Accumulator FIGURE : Numercally controlled oscllator structure. Samplng requency 5MHz.5 Ampltude -.5-5 samples n one cycle.5 Tme (s).5 x -6 FIGURE 3: Output waeorm o NCO. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 45
3. Preous Work NCO whch generates sne or cosne output as shown n Fg. ders mostly n the mplementaton o ROM block. Ths block s the slowest and consumes hgh power. The problem o ROM s that, ts sze grows exponentally wth the wdth o the phase accumulator. Snce one normally desres a large number o bts to achee ne requency tunng and hgh spectral purty, seeral technques hae been nented to lmt the ROM sze whle mantanng sutable perormance. One technque uses the quarter wae symmetry o sne uncton to reduce the number o saed samples by 4, n whch ROM saes only the ampltudes o rst quarter and through addtonal hardware the other quarters are generated [6]. Truncatng accumulator output (remoe number o most sgncant bts (MSBs)) s a common method to reduce the sze o ROM but ths method ntroduces spurous harmoncs [7]. Derent angular decomposton technques proposed to reduce the ROM sze consst o splttng the ROM nto a number o smaller ROMs, each ROM s addressed by a porton o truncated accumulator output. Generated samples o each ROM are added to orm a complete snusodal waeorm. In order to ntroduce more reducton n the ROM sze, many technques hae been proposed to make an ntal approxmaton o the sne ampltude rom the alue o the phase angle, and to use the ROM or a combnaton o ROMs to store correcton alues [8:]. Although these methods reduce the power consumpton but they stll use ROM whch causes a resdual o hgh power consumpton. Many other technques hae been proposed usng pecewse contnuous polynomals to approxmate the rst quadrant o the sne uncton. One o them s based on a Taylor-seres expanson [], a smpled 4th degree polynomal [3] and 4th degree Chebyshe polynomals [4]. The drawbacks o the aboe technques are that they requre addtonal hardware to make extra computatons whch ncrease the complexty o the crcut. The addtonal hardware consumes power consumpton whch supposed to reduce. 4. MODIFIED NCO 4. Proposed Archtecture In proposed archtecture no ROM s used, to prode ast swtchng, and less power consumpton. Instead o usng a ROM a pecewse lnear approxmaton s used, that s representng the rst quarter o the cosne waeorm as lnear lnes, each lne ts a lnear equaton wth slope and bas. Dependng on the symmetry o the cosne waeorm (hae 4 quarters), t can easly deduce the other 3 quarters o the cosne waeorm rom only the rst quarter. The rst quarter o the cosne uncton s dded nto eght pecewse lnear segments o equal length o the orm: + cos(t) a t + b, π t < π, =,,...7, 6 6 (9) where a s the segment slope and s lmted to 4 bts, and b s the constant or bas lmted to 8 bts. Slopes and bases are chosen usng the mnmum mean square error (MMSE) crteron, that mnmzes the ntegrated mean square error between the deal cos(t) and the approxmated cosne unctonp (t). π/ mmse = [cos(t) p(t)] dt. () t= Fg. 4 shows a comparson between deal and approxmated cosne waeorms. It seems to be the same except the top and bottom o the waeorm, that s because o the lnear segments. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 46
.5 Ampltude -.5 cos(t) p(t) - 5 5 Tme (s) FIGURE 4: Approxmated and Ideal cosne waeorms. The moded NCO conssts o two man components and two negaton unts. Fg. 5 shows the block dagram o each component and the correspondng waeorm. Accumulator recees the nput sgnal (n) whch represents the phase derence between θ and θ. The accumulator works as a crcular counter. A complete rotaton o the accumulator represents one cycle o the output waeorm. The accumulator recees a sgnal wth eght bts-length, and the wdth o the accumulator s j=6 bts, so truncaton s done to the output sgnal o the accumulator to be X sgnal wth L= bts length. The rst two most sgncant (MSBs) bts o the accumulator are used to control the operaton o NCO. nd MSB controls the sgn o sgnal X beore perormng the pecewse lnear calculaton. Ths negate sgn s needed to substtute n the lnear uncton to generate all quarters o the cosne waeorm. Second negaton s done at the output stage to correct poston o second and thrd quarters. Ths negaton s controlled usng XOR uncton between st, and nd MSB. st MSB nd MSB nd, and 3 rd quarters cos( ω n) (n) Accumulator (j bts) X (L bts) Negaton X or -X Pecewse lnear uncton Negaton Clock X output sgnal rom accumulator output sgnal rom st negaton output sgnal rom lnear uncton output sgnal rom NCO Ampltude L Ampltude Ampltude Ampltude Tme Tme Tme Tme FIGURE 5: Structure o moded NCO. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 47
4. Spurous Free Dynamc Range (SFDR) SFDR s dened as the rato between the RMS alue o the undamental requency (maxmum sgnal component) and the RMS alue o the next largest nose or harmonc dstorton component, (whch s reerred to as a spurous or a spur ) at ts output. SFDR s usually measured n dbc (.e. wth respect to the carrer requency ampltude) or n dbfs (.e. wth respect to the ADC's ull-scale range). Dependng on the test condton, SFDR s obsered wthn a predened requency wndow or rom DC up to Nyqust s requency o the conerter (ADC or DAC). Fg. 6 shows how SFDR s measured [5]. Snce the moded NCO depends on lnear approxmaton to generate dgtal samples o cosne waeorm, the spectrum o the generated waeorm contans spurs at all the spectrum requences, and SFDR s used to measure the spectral purty o the generated requences. Ampltude (db) Fundamental SFDR Largest Frequency / s FIGURE 6: SFDR measure. 5. DPLL MATHEMATICAL MODEL A mathematcal model or DPLL s bult n z-doman, and s-doman to study the ablty o the system to mantan phase trackng when exted by phase steps, requency steps, or other exctaton sgnals. Fg. 7 and Fg. 8 shows mathematcal model o the system n both Z-doman and S-doman respectely. (z) θ (z) Phase Detector θ (z) d d(z) k d Loop Flter.65 (z + ) F(z) = z.9375 θ (z) NCO z + G(z) = 64 (z ) (z) FIGURE 7: DPLL n Z-doman. (s) θ (s) Phase Detector θ (s) d k d d(s) Loop Flter F(s) = 5.5 s+.5 NCO θ (s) G(s) = 64 s (s) FIGURE 8: DPLL n S-doman. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 48
The phase transer uncton o the system n Z-doman s θ(z) k d F(z) G(z) + z + z = = θ (z) + K F(z) G(z) 5 98 z + 96 z d. () To get the step response o the system a relaton between (z) and (z) s needed. Assumng the nput sgnal s a unt step o requency at constant phase (z) F(z) 64 ( z ) = = (z) + F(z) G(z) 5 98 z + 96 z. () Usng blnear transormaton, the preous equatons are obtaned n S-doman θ (s) k F(s) G(s) = = d θ(s) + k d F(s) G(s) 99 s + 3 s + (3) (s) F(s) 64 s = = (s) + G(s) F(s) 99 s + 3 s + (4) In the test or stablty, DPLL s subjected to a test sgnal representng a unt step o requency at constant phase usng (4) wth s = 5 MHz [6-7]. As shown n Fg. 9, the system s stable wth oershoots at the transent state.. Step Response.8 Ampltude.6.4. -..5.5.5 3 3.5 4 Tme (sec) x -6 6. SIMULATION RESULTS FIGURE 9: DPLL n S-doman. 6. SFDR o Moded NCO To measure the SFDR a dscrete Fourer transorm (DFT) s done or a long repetton perod o the generated sgnal rom moded NCO. Derence between the ampltude o the undamental output requency and the ampltude o the largest spurs n the dynamc range s noted. Fg. shows the output spectrum or nput word o alue 37 representng (n), at a clock requency Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 49
o 5 MHz and an accumulator wdth j=6. The undamental requency s approxmately MHz wth -3.57 db, and the spurous appears at 4.46 MHz wth -89.95 db, so SFDR=59.868 dbc. - -3-4 Power (db) -5-6 -7-8 -9 5 5 5 Frequency (MHz) FIGURE : SFDR or undamental requency o MHz. 6. DPLL Synchronzaton In ths secton, we nestgate the perormances o proposed DPLL s usng computer smulatons. The proposed DPLL has the ollowng parameters: s = MHz, km =, k 4, = o A = A =, ω = MHz, and θ =. Two types o smulatons are done. In the rst one, DPLL recees a sgnal wth phase derence ( ω = MHz, θ = π / 4 ), DPLL response s shown n Fg.. In the second case nput sgnal has both phase derence and requency derence ( ω =. MH z, θ = π / 4 ), DPLL response s shown n Fg....5 F..5 -.5 3 4 5 Tme (s) x -5 FIGURE : DPLL response n case o phase derence. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
.5.45.4.35.3 V F.5..5..5 3 4 5 Tme (s) x -5 FIGURE : DPLL response n case o phase and requency derence. 6.3 Proposed DPLL s. Tradtonal DPLL The man objecte o ths smulaton s to compare the perormance o the proposed DPLL wth tradtonal DPLL; to be sure that replacng ROM wth lnear approxmaton dd not aect the operaton o DPLL. In ths smulaton both archtectures hae the same parameters. s = MHz, km =, k = 4, A = Ao =, ω = MHz, and θ =. An nput sgnal wth ω =. MHz and θ = π /. s appled to both archtectures. Both responses are shown n Fg.3 whch ndcates that the perormance o the proposed DPLL s not aected by the moded NCO..e. the ablty o lockng phase or requency o the nput sgnal s not aected. Ths means the proposed DPLL saes power consumpton compared to tradtonal DPLL wthout aectng the perormance o DPLL..5.5.45.45.4.4.35.35.3.3 V F.5 V F.5...5.5...5.5 3 4 5 Tme (s) x -5 a) 3 4 5 Tme (s) x -5 b) FIGURE 3: DPLL response n case o phase and requency derence a) Response o tradtonal DPLL. b) Response o proposed DPLL. 7. HARDWARE IMPLEMENTATION Hardware mplementaton o moded NCO, and moded DPLL s done usng VHDL code usng Xlnx system generator Smulnk tool [8:]. The archtecture o moded NCO s shown n Fg. 4. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
FIGURE 4: Moded NCO model Implementaton o lnear segments requres slopes and constants. The slopes are chosen usng MMSE as mentoned beore and the slopes accuracy s lmted to a racton our bts. m represents the ull truncated output rom the accumulator, m s hal m, m4 s hal m (quarter m) and m8 s hal m4 (eghth m). The rst three MSBs generated rom the accumulator are used to control three multplexers. The rst two multplexers are ormng the slope alue, and the thrd multplexer orm the constant alue. Accordng to the selected sgnal, the lnear equatons are chosen through the multplexers to orm the complete lnear equaton. The archtecture o moded DPLL s shown n Fg. 5; the archtecture uses the moded NCO nstead o tradtonal NCO. The smulaton s done at clock requency 5 MHz. All sgnals are bnary sgnals wth derent wdths. The nput sgnal s a bnary sgnal o 8 bts wdth representng a snusodal sgnal at requency MHz. Fg.6 shows the smulaton waeorms as an analog sgnal, the nput sgnal (nput) o requency MHz s multpled by the moded NCO sgnal (nput), and the output sgnal s passed through the dgtal lter. The nal output shows that dgtal mplementaton agrees wth the smulaton waeorm. FIGURE 5: Moded DPLL model. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 5
nput sgnal.5 -.5 Output sgnal Multpler o/p.5 -.5.5.5.5.5 3 3.5 4 4.5.5.5.5 3 3.5 4 4.5 x -5 x -5 Flter o/p.4..5.5.5 3 3.5 4 4.5 x -5 -..5.5.5 Tme (s) 3 3.5 4 4.5 5 x -5 FIGURE 6: VHDL smulatons o DPLL. To recognze how much the moded NCO reduces the power consumpton, logc elements and operaton wth aster requency. A comparson between tradtonal NCO, whch uses ROM block and moded NCO, s done by mplementng both archtectures on the same FPGA dece (Xlnx- Spartan-3A DSP Xc3d34a-5g676). Ths comparson ges an dea o how much could be the mproements n power consumpton, reducton n the occuped number o logc elements and aster requency. As llustrated n Table, the moded NCO reduces about 4% o total logc elements used n tradtonal NCO, and dd not use memory bts, whch leads to sae the power consumpton by about 5% and operaton at a aster requency about.8 tmes the speed o tradtonal NCO. Comparson s also done wth the tradtonal DPLL (whch uses a tradtonal NCO) and moded DPLL (whch uses moded NCO). Table shows the result o comparson; t s clear that the moded DPLL consumed less power, occuped less area and worked aster than the tradtonal DPLL, wth no degradaton n system operaton such as lockng range. Tradtonal NCO Moded NCO Slces 8 64 Flp Flops 7 Block RAMs 6 Look up table (LUT) 6 IOBs 4 4 Maxmum Frequency 5.46 MHz 84.738 MHZ Power consumpton.64 Watt.97 Watt TABLE : Implementaton results comparson o NCO. Tradtonal DPLL Moded DPLL Slces 6 64 Flp Flops 37 7 Block RAMs 6 Look up table (LUT) 99 6 IOBs 4 4 Maxmum Frequency.4 MHz 5.79 MHZ Power consumpton.34 Watt.37 Watt TABLE : Implementaton results comparson o DPLL. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 53
8. CONCLUSION Second order DPLL archtecture has been descrbed, analyzed and mplemented to be sutable or any applcaton. The problem o hgh power consumpton o DPLL has been soled by replacng the tradtonal NCO (the man component n DPLL) wth a moded ROM. The tradtonal NCO uses ROM, whch results n hgh power consumpton as well as slower operaton. The proposed archtecture reduces power consumpton, area consumpton and works at a hgher requency than the tradtonal one. 9. ACKNOWLEDGEMENT Ths research s partally supported by Grant-n-Ad or Scentc Research (B) no.3674, and the Ahara Project, the Frst program rom JSPS, ntated by CSTP.. REFERENCES [] M. Dllnger. K. Madan, N. Alonstot. Sotware Dened rado: Archtectures, systems, and unctons. John Wlley & Sons Inc., 3. [] T. J. Rouphael. RF and Dgtal Sgnal Processng For Sotware-Dened Rado: A Mult standard Mult-Mode Approch. John Wlly & Sons Inc., 8 [3] R. E. Best. Phase-Locked Loops: Desgn, Smulaton, and Applcaton. 6 th ed, McGraw-Hll, 7. [4] S. Goldman. Phase Locked-Loop Engneerng Hand Book o Integrated Crcut. Artech House Publshers, 7 [5] B. Goldberg. Dgtal Frequency Synthess Demysted: DDS and Fractonal-N PLLs. Newnes,999. [6] V.F. Kroupa, Ed. Drect Dgtal Frequency Syntheszers. IEEE Press,999. [7] V.F. Kroupa, V. Czek, J. Stursa, H. Sandoa. Spurous sgnals n drect dgtal requency syntheszers due to the phase truncaton. IEEE Transactons on Ultrasoncs, Ferroelectrcs, and Frequency Control, ol. 47, no. 5, pp. 66-7, September. [8] H.T. Ncholas III, H. Samuel and B. Km. The optmzaton o drect dgtal requency syntheszer perormance n the presence o nte word length eects, n Proc. o the 4nd Annual Frequency Control Symposum, 988, pp. 357-363. [9] A. Yamagsh, M. Ishkawa, T. Tsukahara, and S. Date. "A -V, -GHz low-power drect dgtal requency syntheszer chpset or wreless communcaton." IEEE Journal o Sold- State Crcuts, ol. 33, pp.-7, February 998. [] A. M. Sodagar, G. R. Lahj, Mappng rom phase to sne-ampltude n drect dgtal requency syntheszers usng parabolc approxmaton. n IEEE Transactons on Crcuts and Systems-II: Analog and Dgtal Sgnal Processng, ol. 47, pp. 45-457, December. [] J.M.P. Langlos, D. Al-Khall. ROM sze reducton wth low processng cost or drect dgtal requency synthess, n Proc. o the IEEE Pacc Rm Conerence on Communcatons, Computers and Sgnal Processng, August, pp. 87-9. [] L.A. Weaer, R.J. Kerr. Hgh resoluton phase to sne ampltude conerson. U.S. patent 4 95 77, Feb. 7,99. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 54
[3] A.M. Sodagar, G.R. Lahj. A noel archtecture or ROM-less sne-output drect dgtal requency syntheszers by usng the nd-order parabolc approxmaton, n Proc. o the IEEE/IEA Internatonal Frequency Control Symposum and Exhbton, 7-9 June, pp. 84-89. [4] K.I. Palomak, J. Ntylaht. Drect dgtal requency syntheszer archtecture based on Chebyshe approxmaton, n Proc. o the 34th Aslomar Conerence on Sgnals, Systems and Computers, Oct. 9th No. st.,, pp. 639-643. [5] J. Rudy. CMOS Integrated Analog-to-Dgtal and Dgtal-to-Analog Conerters. Sprnger, 3. [6] J. G. Proaks, G. Dmtr, Manolaks. Dgtal Sgnal Processng. Prentce Hall,996. [7] Naresh K. Snha. Lnear Systems. John Wley & Sons Inc.,99. [8] Xlnx Inc. system generator or DSP user gude. Xlnx, 9. [9] W.Y. Yang. Matlab/Smulnk or Dgtal Communcaton. A-Jn, 9. [] P. Chu. FPGA Prototypng by VHDL Examples: Xlnx Spartan-3 Verson. Wley-Interscence, 8. Sgnal Processng: An Internatonal Journal (SPIJ), Volume (5) : Issue (4) : 55